/* * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC * * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> * * Licensed under GPLv2 only. */ #include "skeleton.dtsi" #include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/at91.h> / { model = "Atmel AT91SAM9263 family SoC"; compatible = "atmel,at91sam9263"; interrupt-parent = <&aic>; aliases { serial0 = &dbgu; serial1 = &usart0; serial2 = &usart1; serial3 = &usart2; gpio0 = &pioA; gpio1 = &pioB; gpio2 = &pioC; gpio3 = &pioD; gpio4 = &pioE; tcb0 = &tcb0; i2c0 = &i2c0; ssc0 = &ssc0; ssc1 = &ssc1; pwm0 = &pwm0; spi0 = &spi0; }; cpus { cpu { compatible = "arm,arm926ej-s"; device_type = "cpu"; }; }; memory { reg = <0x20000000 0x08000000>; }; clocks { main_xtal: main_xtal { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; slow_xtal: slow_xtal { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; }; sram0: sram@00300000 { compatible = "mmio-sram"; reg = <0x00300000 0x14000>; }; sram1: sram@00500000 { compatible = "mmio-sram"; reg = <0x00500000 0x4000>; }; ahb { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; u-boot,dm-pre-reloc; apb { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; u-boot,dm-pre-reloc; aic: interrupt-controller@fffff000 { #interrupt-cells = <3>; compatible = "atmel,at91rm9200-aic"; interrupt-controller; reg = <0xfffff000 0x200>; atmel,external-irqs = <30 31>; }; pmc: pmc@fffffc00 { compatible = "atmel,at91rm9200-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupt-controller; #address-cells = <1>; #size-cells = <0>; #interrupt-cells = <1>; u-boot,dm-pre-reloc; main_osc: main_osc { compatible = "atmel,at91rm9200-clk-main-osc"; #clock-cells = <0>; interrupts-extended = <&pmc AT91_PMC_MOSCS>; clocks = <&main_xtal>; }; main: mainck { compatible = "atmel,at91rm9200-clk-main"; #clock-cells = <0>; clocks = <&main_osc>; }; plla: pllack@0 { compatible = "atmel,at91rm9200-clk-pll"; #clock-cells = <0>; interrupts-extended = <&pmc AT91_PMC_LOCKA>; clocks = <&main>; reg = <0>; atmel,clk-input-range = <1000000 32000000>; #atmel,pll-clk-output-range-cells = <4>; atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, <190000000 240000000 2 1>; }; pllb: pllbck@1 { compatible = "atmel,at91rm9200-clk-pll"; #clock-cells = <0>; interrupts-extended = <&pmc AT91_PMC_LOCKB>; clocks = <&main>; reg = <1>; atmel,clk-input-range = <1000000 32000000>; #atmel,pll-clk-output-range-cells = <4>; atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, <190000000 240000000 2 1>; }; mck: masterck { compatible = "atmel,at91rm9200-clk-master"; #clock-cells = <0>; interrupts-extended = <&pmc AT91_PMC_MCKRDY>; clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; atmel,clk-output-range = <0 120000000>; atmel,clk-divisors = <1 2 4 0>; u-boot,dm-pre-reloc; }; usb: usbck { compatible = "atmel,at91rm9200-clk-usb"; #clock-cells = <0>; atmel,clk-divisors = <1 2 4 0>; clocks = <&pllb>; }; prog: progck { compatible = "atmel,at91rm9200-clk-programmable"; #address-cells = <1>; #size-cells = <0>; interrupt-parent = <&pmc>; clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; prog0: prog@0 { #clock-cells = <0>; reg = <0>; interrupts = <AT91_PMC_PCKRDY(0)>; }; prog1: prog@1 { #clock-cells = <0>; reg = <1>; interrupts = <AT91_PMC_PCKRDY(1)>; }; prog2: prog@2 { #clock-cells = <0>; reg = <2>; interrupts = <AT91_PMC_PCKRDY(2)>; }; prog3: prog@3 { #clock-cells = <0>; reg = <3>; interrupts = <AT91_PMC_PCKRDY(3)>; }; }; systemck { compatible = "atmel,at91rm9200-clk-system"; #address-cells = <1>; #size-cells = <0>; uhpck: uhpck@6 { #clock-cells = <0>; reg = <6>; clocks = <&usb>; }; udpck: udpck@7 { #clock-cells = <0>; reg = <7>; clocks = <&usb>; }; pck0: pck0@8 { #clock-cells = <0>; reg = <8>; clocks = <&prog0>; }; pck1: pck1@9 { #clock-cells = <0>; reg = <9>; clocks = <&prog1>; }; pck2: pck2@10 { #clock-cells = <0>; reg = <10>; clocks = <&prog2>; }; pck3: pck3@11 { #clock-cells = <0>; reg = <11>; clocks = <&prog3>; }; }; periphck { compatible = "atmel,at91rm9200-clk-peripheral"; #address-cells = <1>; #size-cells = <0>; clocks = <&mck>; u-boot,dm-pre-reloc; pioA_clk: pioA_clk@2 { #clock-cells = <0>; reg = <2>; u-boot,dm-pre-reloc; }; pioB_clk: pioB_clk@3 { #clock-cells = <0>; reg = <3>; u-boot,dm-pre-reloc; }; pioCDE_clk: pioCDE_clk@4 { #clock-cells = <0>; reg = <4>; u-boot,dm-pre-reloc; }; usart0_clk: usart0_clk@7 { #clock-cells = <0>; reg = <7>; }; usart1_clk: usart1_clk@8 { #clock-cells = <0>; reg = <8>; }; usart2_clk: usart2_clk@9 { #clock-cells = <0>; reg = <9>; }; mci0_clk: mci0_clk@10 { #clock-cells = <0>; reg = <10>; }; mci1_clk: mci1_clk@11 { #clock-cells = <0>; reg = <11>; }; can_clk: can_clk@12 { #clock-cells = <0>; reg = <12>; }; twi0_clk: twi0_clk@13 { #clock-cells = <0>; reg = <13>; }; spi0_clk: spi0_clk@14 { #clock-cells = <0>; reg = <14>; }; spi1_clk: spi1_clk@15 { #clock-cells = <0>; reg = <15>; }; ssc0_clk: ssc0_clk@16 { #clock-cells = <0>; reg = <16>; }; ssc1_clk: ssc1_clk@17 { #clock-cells = <0>; reg = <17>; }; ac97_clk: ac97_clk@18 { #clock-cells = <0>; reg = <18>; }; tcb_clk: tcb_clk@19 { #clock-cells = <0>; reg = <19>; }; pwm_clk: pwm_clk@20 { #clock-cells = <0>; reg = <20>; }; macb0_clk: macb0_clk@21 { #clock-cells = <0>; reg = <21>; }; g2de_clk: g2de_clk@23 { #clock-cells = <0>; reg = <23>; }; udc_clk: udc_clk@24 { #clock-cells = <0>; reg = <24>; }; isi_clk: isi_clk@25 { #clock-cells = <0>; reg = <25>; }; lcd_clk: lcd_clk@26 { #clock-cells = <0>; reg = <26>; }; dma_clk: dma_clk@27 { #clock-cells = <0>; reg = <27>; }; ohci_clk: ohci_clk@29 { #clock-cells = <0>; reg = <29>; }; }; }; ramc0: ramc@ffffe200 { compatible = "atmel,at91sam9260-sdramc"; reg = <0xffffe200 0x200>; }; ramc1: ramc@ffffe800 { compatible = "atmel,at91sam9260-sdramc"; reg = <0xffffe800 0x200>; }; pit: timer@fffffd30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&mck>; }; tcb0: timer@fff7c000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfff7c000 0x100>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&tcb_clk>, <&slow_xtal>; clock-names = "t0_clk", "slow_clk"; }; rstc@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&slow_xtal>; }; shdwc@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; clocks = <&slow_xtal>; }; pinctrl@fffff200 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff200 0xfffff200 0xa00>; reg = <0xfffff200 0x200 0xfffff400 0x200 0xfffff600 0x200 0xfffff800 0x200 0xfffffa00 0x200 >; atmel,mux-mask = < /* A B */ 0xfffffffb 0xffffe07f /* pioA */ 0x0007ffff 0x39072fff /* pioB */ 0xffffffff 0x3ffffff8 /* pioC */ 0xfffffbff 0xffffffff /* pioD */ 0xffe00fff 0xfbfcff00 /* pioE */ >; /* shared pinctrl settings */ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; }; }; usart0 { pinctrl_usart0: usart0-0 { atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA26 periph A with pullup */ AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */ }; pinctrl_usart0_rts: usart0_rts-0 { atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA28 periph A */ }; pinctrl_usart0_cts: usart0_cts-0 { atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA29 periph A */ }; }; usart1 { pinctrl_usart1: usart1-0 { atmel,pins = <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */ AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD1 periph A */ }; pinctrl_usart1_rts: usart1_rts-0 { atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD7 periph B */ }; pinctrl_usart1_cts: usart1_cts-0 { atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD8 periph B */ }; }; usart2 { pinctrl_usart2: usart2-0 { atmel,pins = <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A with pullup */ AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD3 periph A */ }; pinctrl_usart2_rts: usart2_rts-0 { atmel,pins = <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD5 periph B */ }; pinctrl_usart2_cts: usart2_cts-0 { atmel,pins = <AT91_PIOD 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD6 periph B */ }; }; nand { pinctrl_nand: nand-0 { atmel,pins = <AT91_PIOA 22 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PA22 gpio RDY pin pull_up*/ AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD15 gpio enable pin pull_up */ }; }; macb { pinctrl_macb_rmii: macb_rmii-0 { atmel,pins = <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */ AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */ AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */ AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */ AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */ AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */ AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */ AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */ AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */ AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */ }; pinctrl_macb_rmii_mii: macb_rmii_mii-0 { atmel,pins = <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */ AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */ AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC22 periph B */ AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC23 periph B */ AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC24 periph B */ AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */ AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */ AT91_PIOE 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE22 periph B */ }; }; mmc0 { pinctrl_mmc0_clk: mmc0_clk-0 { atmel,pins = <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA12 periph A */ }; pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { atmel,pins = <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA0 periph A with pullup */ }; pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { atmel,pins = <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */ AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */ AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */ }; pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { atmel,pins = <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA17 periph A with pullup */ }; pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { atmel,pins = <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ }; }; mmc1 { pinctrl_mmc1_clk: mmc1_clk-0 { atmel,pins = <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */ }; pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 { atmel,pins = <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA8 periph A with pullup */ }; pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { atmel,pins = <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */ AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */ AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */ }; pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 { atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA21 periph A with pullup */ AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA22 periph A with pullup */ }; pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 { atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA23 periph A with pullup */ AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */ AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA25 periph A with pullup */ }; }; ssc0 { pinctrl_ssc0_tx: ssc0_tx-0 { atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB0 periph B */ AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB1 periph B */ AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */ }; pinctrl_ssc0_rx: ssc0_rx-0 { atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B */ AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B */ AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B */ }; }; ssc1 { pinctrl_ssc1_tx: ssc1_tx-0 { atmel,pins = <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ }; pinctrl_ssc1_rx: ssc1_rx-0 { atmel,pins = <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */ AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ }; }; spi0 { pinctrl_spi0: spi0-0 { atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA0 periph B SPI0_MISO pin */ AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA1 periph B SPI0_MOSI pin */ AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA2 periph B SPI0_SPCK pin */ }; }; spi1 { pinctrl_spi1: spi1-0 { atmel,pins = <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A SPI1_MISO pin */ AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A SPI1_MOSI pin */ AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A SPI1_SPCK pin */ }; }; tcb0 { pinctrl_tcb0_tclk0: tcb0_tclk0-0 { atmel,pins = <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; pinctrl_tcb0_tclk1: tcb0_tclk1-0 { atmel,pins = <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; pinctrl_tcb0_tclk2: tcb0_tclk2-0 { atmel,pins = <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; }; pinctrl_tcb0_tioa0: tcb0_tioa0-0 { atmel,pins = <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; pinctrl_tcb0_tioa1: tcb0_tioa1-0 { atmel,pins = <AT91_PIOE 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; pinctrl_tcb0_tioa2: tcb0_tioa2-0 { atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; pinctrl_tcb0_tiob0: tcb0_tiob0-0 { atmel,pins = <AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; pinctrl_tcb0_tiob1: tcb0_tiob1-0 { atmel,pins = <AT91_PIOE 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; pinctrl_tcb0_tiob2: tcb0_tiob2-0 { atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; }; fb { pinctrl_fb: fb-0 { atmel,pins = <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A */ AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A */ AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A */ AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB9 periph B */ AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A */ AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A */ AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A */ AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 periph A */ AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 periph A */ AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A */ AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A */ AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A */ AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A */ AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC12 periph B */ AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC18 periph A */ AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A */ AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A */ AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A */ AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC24 periph A */ AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC17 periph B */ AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC26 periph A */ AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC27 periph A */ }; }; can { pinctrl_can_rx_tx: can_rx_tx { atmel,pins = <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* CANRX, conflicts with IRQ0 */ AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* CANTX, conflicts with PCK0 */ }; }; ac97 { pinctrl_ac97: ac97-0 { atmel,pins = <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A AC97FS pin */ AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A AC97CK pin */ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A AC97TX pin */ AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A AC97RX pin */ }; }; }; pioA: gpio@fffff200 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff200 0x200>; interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&pioA_clk>; u-boot,dm-pre-reloc; }; pioB: gpio@fffff400 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&pioB_clk>; u-boot,dm-pre-reloc; }; pioC: gpio@fffff600 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff600 0x200>; interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&pioCDE_clk>; u-boot,dm-pre-reloc; }; pioD: gpio@fffff800 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff800 0x200>; interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&pioCDE_clk>; u-boot,dm-pre-reloc; }; pioE: gpio@fffffa00 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffffa00 0x200>; interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; clocks = <&pioCDE_clk>; u-boot,dm-pre-reloc; }; dbgu: serial@ffffee00 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xffffee00 0x200>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; clocks = <&mck>; clock-names = "usart"; status = "disabled"; }; usart0: serial@fff8c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff8c000 0x200>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; clocks = <&usart0_clk>; clock-names = "usart"; status = "disabled"; }; usart1: serial@fff90000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff90000 0x200>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; clocks = <&usart1_clk>; clock-names = "usart"; status = "disabled"; }; usart2: serial@fff94000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff94000 0x200>; interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; clocks = <&usart2_clk>; clock-names = "usart"; status = "disabled"; }; ssc0: ssc@fff98000 { compatible = "atmel,at91rm9200-ssc"; reg = <0xfff98000 0x4000>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; clocks = <&ssc0_clk>; clock-names = "pclk"; status = "disabled"; }; ssc1: ssc@fff9c000 { compatible = "atmel,at91rm9200-ssc"; reg = <0xfff9c000 0x4000>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; clocks = <&ssc1_clk>; clock-names = "pclk"; status = "disabled"; }; ac97: sound@fffa0000 { compatible = "atmel,at91sam9263-ac97c"; reg = <0xfffa0000 0x4000>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ac97>; clocks = <&ac97_clk>; clock-names = "ac97_clk"; status = "disabled"; }; macb0: ethernet@fffbc000 { compatible = "cdns,at91sam9260-macb", "cdns,macb"; reg = <0xfffbc000 0x100>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; clocks = <&macb0_clk>, <&macb0_clk>; clock-names = "hclk", "pclk"; status = "disabled"; }; usb1: gadget@fff78000 { compatible = "atmel,at91sam9263-udc"; reg = <0xfff78000 0x4000>; interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; clocks = <&udc_clk>, <&udpck>; clock-names = "pclk", "hclk"; status = "disabled"; }; i2c0: i2c@fff88000 { compatible = "atmel,at91sam9260-i2c"; reg = <0xfff88000 0x100>; interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; #address-cells = <1>; #size-cells = <0>; clocks = <&twi0_clk>; status = "disabled"; }; mmc0: mmc@fff80000 { compatible = "atmel,hsmci"; reg = <0xfff80000 0x600>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; clocks = <&mci0_clk>; clock-names = "mci_clk"; status = "disabled"; }; mmc1: mmc@fff84000 { compatible = "atmel,hsmci"; reg = <0xfff84000 0x600>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; clocks = <&mci1_clk>; clock-names = "mci_clk"; status = "disabled"; }; watchdog@fffffd40 { compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffd40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&slow_xtal>; atmel,watchdog-type = "hardware"; atmel,reset-type = "all"; atmel,dbg-halt; status = "disabled"; }; spi0: spi@fffa4000 { #address-cells = <1>; #size-cells = <0>; compatible = "atmel,at91rm9200-spi"; reg = <0xfffa4000 0x200>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; clocks = <&spi0_clk>; clock-names = "spi_clk"; status = "disabled"; }; spi1: spi@fffa8000 { #address-cells = <1>; #size-cells = <0>; compatible = "atmel,at91rm9200-spi"; reg = <0xfffa8000 0x200>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; clocks = <&spi1_clk>; clock-names = "spi_clk"; status = "disabled"; }; pwm0: pwm@fffb8000 { compatible = "atmel,at91sam9rl-pwm"; reg = <0xfffb8000 0x300>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>; #pwm-cells = <3>; clocks = <&pwm_clk>; clock-names = "pwm_clk"; status = "disabled"; }; can: can@fffac000 { compatible = "atmel,at91sam9263-can"; reg = <0xfffac000 0x300>; interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can_rx_tx>; clocks = <&can_clk>; clock-names = "can_clk"; }; rtc@fffffd20 { compatible = "atmel,at91sam9260-rtt"; reg = <0xfffffd20 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&slow_xtal>; status = "disabled"; }; rtc@fffffd50 { compatible = "atmel,at91sam9260-rtt"; reg = <0xfffffd50 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&slow_xtal>; status = "disabled"; }; gpbr: syscon@fffffd60 { compatible = "atmel,at91sam9260-gpbr", "syscon"; reg = <0xfffffd60 0x50>; status = "disabled"; }; }; fb0: fb@0x00700000 { compatible = "atmel,at91sam9263-lcdc"; reg = <0x00700000 0x1000>; interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fb>; clocks = <&lcd_clk>, <&lcd_clk>; clock-names = "lcdc_clk", "hclk"; status = "disabled"; }; nand0: nand@40000000 { compatible = "atmel,at91rm9200-nand"; #address-cells = <1>; #size-cells = <1>; reg = <0x40000000 0x10000000 0xffffe000 0x200 >; atmel,nand-addr-offset = <21>; atmel,nand-cmd-offset = <22>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; gpios = <&pioA 22 GPIO_ACTIVE_HIGH &pioD 15 GPIO_ACTIVE_HIGH 0 >; status = "disabled"; }; usb0: ohci@00a00000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00a00000 0x100000>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; }; i2c-gpio-0 { compatible = "i2c-gpio"; gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ &pioB 5 GPIO_ACTIVE_HIGH /* scl */ >; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; i2c-gpio,delay-us = <2>; /* ~100 kHz */ #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; };