/* * Internal Definitions */ #include #define BOOTFLASH_START 0xF0000000 /* * DDR Setup */ #define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CFG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #define CFG_83XX_DDR_USES_CS0 /* * Manually set up DDR parameters */ #define CFG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */ /* * The reserved memory */ #define CFG_SYS_FLASH_BASE 0xF0000000 /* Reserve 768 kB for Mon */ /* * Initial RAM Base Address Setup */ #define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CFG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ /* * Init Local Bus Memory Controller: * * Bank Bus Machine PortSz Size Device * ---- --- ------- ------ ----- ------ * 0 Local GPCM 16 bit 256MB FLASH * 1 Local GPCM 8 bit 128MB GPIO/PIGGY * */ /* * FLASH on the Local Bus */ #define CFG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } /* I2C */ #define CFG_SYS_NUM_I2C_BUSES 4 #define CFG_SYS_I2C_MAX_HOPS 1 #define CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ {1, {I2C_NULL_HOP} } } #if defined(CONFIG_CMD_NAND) #define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE #endif /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ #define CFG_SYS_BOOTMAPSZ (8 << 20) /* * Environment */ /* * Environment Configuration */ #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ #define CONFIG_KM_DEF_ENV "km-common=empty\0" #endif #ifndef CONFIG_KM_DEF_ARCH #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_KM_DEF_ENV \ CONFIG_KM_DEF_ARCH \ "newenv=" \ "prot off " __stringify(CONFIG_ENV_ADDR) " +0x40000 && " \ "era " __stringify(CONFIG_ENV_ADDR) " +0x40000\0" \ "unlock=yes\0" \ "" /* * QE UEC ethernet configuration */ #define CONFIG_UEC_ETH