// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. */ #include <common.h> #include <i2c.h> #include <hwconfig.h> #include <init.h> #include <log.h> #include <asm/global_data.h> #include <asm/mmu.h> #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> #include <asm/fsl_law.h> #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; if (ctrl_num > 2) { printf("Not supported controller number %d\n", ctrl_num); return; } if (!pdimm->n_ranks) return; /* * we use identical timing for all slots. If needed, change the code * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; */ if (popts->registered_dimm_en) pbsp = rdimms[0]; else pbsp = udimms[0]; /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; while (pbsp->datarate_mhz_high) { if (pbsp->n_ranks == pdimm->n_ranks && (pdimm->rank_density >> 30) >= pbsp->rank_gb) { if (ddr_freq <= pbsp->datarate_mhz_high) { popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; goto found; } pbsp_highest = pbsp; } pbsp++; } if (pbsp_highest) { printf("Error: board specific timing not found for data\n" "rate %lu MT/s\n" "Trying to use the highest speed (%u) parameters\n", ddr_freq, pbsp_highest->datarate_mhz_high); popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; } else { panic("DIMM is not supported by this board"); } found: debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n" "wrlvl_ctrl_3 0x%x\n", pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, pbsp->wrlvl_ctl_3); /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ popts->half_strength_driver_enable = 0; /* * Write leveling override */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xf; /* * Rtt and Rtt_WR override */ popts->rtt_override = 0; /* Enable ZQ calibration */ popts->zq_en = 1; /* DHC_EN =1, ODT = 75 Ohm */ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); /* optimize cpo for erratum A-009942 */ popts->cpo_sample = 0x64; } int dram_init(void) { phys_size_t dram_size; puts("Initializing....using SPD\n"); #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) dram_size = fsl_ddr_sdram(); #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; gd->ram_size = dram_size; return 0; }