// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU216 * * (C) Copyright 2017 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@amd.com> */ /dts-v1/; #include "zynqmp.dtsi" #include "zynqmp-clk-ccf.dtsi" #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> #include <dt-bindings/phy/phy.h> / { model = "ZynqMP ZCU216 RevA"; compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = <KEY_DOWN>; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &psgtr { status = "okay"; /* nc, nc, usb3, sata */ clocks = <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref2", "ref3"; }; &dcc { status = "okay"; }; &fpd_dma_chan1 { status = "okay"; }; &fpd_dma_chan2 { status = "okay"; }; &fpd_dma_chan3 { status = "okay"; }; &fpd_dma_chan4 { status = "okay"; }; &fpd_dma_chan5 { status = "okay"; }; &fpd_dma_chan6 { status = "okay"; }; &fpd_dma_chan7 { status = "okay"; }; &fpd_dma_chan8 { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { status = "okay"; gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &gpu { status = "okay"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; }; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u409B */ reg = <0x5b>; }; }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; }; }; }; &qspi { status = "okay"; is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &rtc { status = "okay"; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; disable-wp; /* * This property should be removed for supporting UHS mode */ no-1-8-v; xlnx,mio-bank = <1>; }; &uart0 { status = "okay"; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; };