// SPDX-License-Identifier: GPL-2.0+ #include /{ chosen { bootargs = "root=/dev/ram rdinit=/linuxrc"; }; aliases { /* Aliases for gpios so as to use sequence */ gpio0 = &gpioa; gpio1 = &gpiob; gpio2 = &gpioc; gpio3 = &gpiod; gpio4 = &gpioe; gpio5 = &gpiof; gpio6 = &gpiog; gpio7 = &gpioh; gpio8 = &gpioi; gpio9 = &gpioj; gpio10 = &gpiok; mmc0 = &sdio2; spi0 = &qspi; }; button1 { compatible = "st,button1"; button-gpio = <&gpioa 0 0>; }; led1 { compatible = "st,led1"; led-gpio = <&gpioj 5 0>; }; panel: panel { compatible = "orisetech,otm8009a"; reset-gpios = <&gpioj 15 1>; status = "okay"; port { panel_in: endpoint { remote-endpoint = <&dsi_out>; }; }; }; soc { dsi: dsi@40016c00 { compatible = "st,stm32-dsi"; reg = <0x40016c00 0x800>; resets = <&rcc STM32F7_APB2_RESET(DSI)>; clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>, <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>, <&clk_hse>; clock-names = "pclk", "px_clk", "ref"; bootph-all; status = "okay"; ports { port@0 { dsi_out: endpoint { remote-endpoint = <&panel_in>; }; }; port@1 { dsi_in: endpoint { remote-endpoint = <&dp_out>; }; }; }; }; }; }; <dc { clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; bootph-all; ports { port@0 { dp_out: endpoint { remote-endpoint = <&dsi_in>; }; }; }; }; &fmc { /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ bank1: bank@0 { bootph-all; st,sdram-control = /bits/ 8 ; st,sdram-timing = /bits/ 8 ; /* refcount = (64msec/total_row_sdram)*freq - 20 */ st,sdram-refcount = < 1542 >; }; }; &pinctrl { ethernet_mii: mii@0 { pins { pinmux = , /* ETH_RMII_TXD0 */ , /* ETH_RMII_TXD1 */ , /* ETH_RMII_TX_EN */ , /* ETH_MDIO */ , /* ETH_MDC */ , /* ETH_RMII_REF_CLK */ , /* ETH_RMII_CRS_DV */ , /* ETH_RMII_RXD0 */ ; /* ETH_RMII_RXD1 */ slew-rate = <2>; }; }; fmc_pins: fmc@0 { pins { pinmux = , /* D31 */ , /* D30 */ , /* D29 */ , /* D28 */ , /* D27 */ , /* D26 */ , /* D25 */ , /* D24 */ , /* D23 */ , /* D22 */ , /* D21 */ , /* D20 */ , /* D19 */ , /* D18 */ , /* D17 */ , /* D16 */ , /* D15 */ , /* D14 */ , /* D13 */ , /* D12 */ , /* D11 */ , /* D10 */ , /* D9 */ , /* D8 */ , /* D7 */ , /* D6 */ , /* D5 */ , /* D4 */ , /* D3 */ , /* D2 */ , /* D1 */ , /* D0 */ , /* NBL3 */ , /* NBL2 */ , /* NBL1 */ , /* NBL0 */ , /* BA1 */ , /* BA0 */ , /* A11 */ , /* A10 */ , /* A9 */ , /* A8 */ , /* A7 */ , /* A6 */ , /* A5 */ , /* A4 */ , /* A3 */ , /* A2 */ , /* A1 */ , /* A0 */ , /* SDNE0 */ , /* SDNWE */ , /* SDNRAS */ , /* SDNCAS */ , /* SDCKE0 */ ; /* SDCLK> */ slew-rate = <2>; }; }; qspi_pins: qspi@0 { pins { pinmux = , /* CLK */ , /* BK1_NCS */ , /* BK1_IO0 */ , /* BK1_IO1 */ , /* BK1_IO3 */ ; /* BK1_IO2 */ slew-rate = <2>; }; }; usart1_pins_a: usart1-0 { bootph-all; pins1 { bootph-all; }; pins2 { bootph-all; }; }; }; &qspi { reg = <0xa0001000 0x1000>, <0x90000000 0x4000000>; flash0: mx66l51235l@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; spi-max-frequency = <108000000>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; reg = <0>; }; };