// SPDX-License-Identifier: (GPL-2.0+ OR MIT) // Copyright (C) 2016 ARM Ltd. // based on the Allwinner H3 dtsi: // Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> #include <dt-bindings/clock/sun50i-a64-ccu.h> #include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-r-ccu.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/reset/sun50i-a64-ccu.h> #include <dt-bindings/reset/sun8i-de2.h> #include <dt-bindings/reset/sun8i-r-ccu.h> #include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&gic>; #address-cells = <1>; #size-cells = <1>; chosen { #address-cells = <1>; #size-cells = <1>; ranges; simplefb_lcd: framebuffer-lcd { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "mixer0-lcd0"; clocks = <&ccu CLK_TCON0>, <&display_clocks CLK_MIXER0>; status = "disabled"; }; simplefb_hdmi: framebuffer-hdmi { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "mixer1-lcd1-hdmi"; clocks = <&display_clocks CLK_MIXER1>, <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; status = "disabled"; }; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0>; enable-method = "psci"; next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <1>; enable-method = "psci"; next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <2>; enable-method = "psci"; next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <3>; enable-method = "psci"; next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; }; L2: l2-cache { compatible = "cache"; cache-level = <2>; }; }; de: display-engine { compatible = "allwinner,sun50i-a64-display-engine"; allwinner,pipelines = <&mixer0>, <&mixer1>; status = "disabled"; }; gpu_opp_table: opp-table-gpu { compatible = "operating-points-v2"; opp-120000000 { opp-hz = /bits/ 64 <120000000>; }; opp-312000000 { opp-hz = /bits/ 64 <312000000>; }; opp-432000000 { opp-hz = /bits/ 64 <432000000>; }; }; osc24M: osc24M_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "osc24M"; }; osc32k: osc32k_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; clock-output-names = "ext-osc32k"; }; pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; sound: sound { #address-cells = <1>; #size-cells = <0>; compatible = "simple-audio-card"; simple-audio-card,name = "sun50i-a64-audio"; simple-audio-card,aux-devs = <&codec_analog>; simple-audio-card,routing = "Left DAC", "DACL", "Right DAC", "DACR", "ADCL", "Left ADC", "ADCR", "Right ADC"; status = "disabled"; simple-audio-card,dai-link@0 { format = "i2s"; frame-master = <&link0_cpu>; bitclock-master = <&link0_cpu>; mclk-fs = <128>; link0_cpu: cpu { sound-dai = <&dai>; }; link0_codec: codec { sound-dai = <&codec 0>; }; }; }; timer { compatible = "arm,armv8-timer"; allwinner,erratum-unknown1; arm,no-tick-in-suspend; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; thermal-zones { cpu_thermal: cpu0-thermal { /* milliseconds */ polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&ths 0>; cooling-maps { map0 { trip = <&cpu_alert0>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu_alert1>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { cpu_alert0: cpu_alert0 { /* milliCelsius */ temperature = <75000>; hysteresis = <2000>; type = "passive"; }; cpu_alert1: cpu_alert1 { /* milliCelsius */ temperature = <90000>; hysteresis = <2000>; type = "hot"; }; cpu_crit: cpu_crit { /* milliCelsius */ temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; gpu0_thermal: gpu0-thermal { /* milliseconds */ polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&ths 1>; }; gpu1_thermal: gpu1-thermal { /* milliseconds */ polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&ths 2>; }; }; soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; bus@1000000 { compatible = "allwinner,sun50i-a64-de2"; reg = <0x1000000 0x400000>; allwinner,sram = <&de2_sram 1>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1000000 0x400000>; display_clocks: clock@0 { compatible = "allwinner,sun50i-a64-de2-clk"; reg = <0x0 0x10000>; clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; clock-names = "bus", "mod"; resets = <&ccu RST_BUS_DE>; #clock-cells = <1>; #reset-cells = <1>; }; rotate: rotate@20000 { compatible = "allwinner,sun50i-a64-de2-rotate", "allwinner,sun8i-a83t-de2-rotate"; reg = <0x20000 0x10000>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&display_clocks CLK_BUS_ROT>, <&display_clocks CLK_ROT>; clock-names = "bus", "mod"; resets = <&display_clocks RST_ROT>; }; mixer0: mixer@100000 { compatible = "allwinner,sun50i-a64-de2-mixer-0"; reg = <0x100000 0x100000>; clocks = <&display_clocks CLK_BUS_MIXER0>, <&display_clocks CLK_MIXER0>; clock-names = "bus", "mod"; resets = <&display_clocks RST_MIXER0>; ports { #address-cells = <1>; #size-cells = <0>; mixer0_out: port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; mixer0_out_tcon0: endpoint@0 { reg = <0>; remote-endpoint = <&tcon0_in_mixer0>; }; mixer0_out_tcon1: endpoint@1 { reg = <1>; remote-endpoint = <&tcon1_in_mixer0>; }; }; }; }; mixer1: mixer@200000 { compatible = "allwinner,sun50i-a64-de2-mixer-1"; reg = <0x200000 0x100000>; clocks = <&display_clocks CLK_BUS_MIXER1>, <&display_clocks CLK_MIXER1>; clock-names = "bus", "mod"; resets = <&display_clocks RST_MIXER1>; ports { #address-cells = <1>; #size-cells = <0>; mixer1_out: port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; mixer1_out_tcon0: endpoint@0 { reg = <0>; remote-endpoint = <&tcon0_in_mixer1>; }; mixer1_out_tcon1: endpoint@1 { reg = <1>; remote-endpoint = <&tcon1_in_mixer1>; }; }; }; }; }; syscon: syscon@1c00000 { compatible = "allwinner,sun50i-a64-system-control"; reg = <0x01c00000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges; sram_c: sram@18000 { compatible = "mmio-sram"; reg = <0x00018000 0x28000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00018000 0x28000>; de2_sram: sram-section@0 { compatible = "allwinner,sun50i-a64-sram-c"; reg = <0x0000 0x28000>; }; }; sram_c1: sram@1d00000 { compatible = "mmio-sram"; reg = <0x01d00000 0x40000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x01d00000 0x40000>; ve_sram: sram-section@0 { compatible = "allwinner,sun50i-a64-sram-c1", "allwinner,sun4i-a10-sram-c1"; reg = <0x000000 0x40000>; }; }; }; dma: dma-controller@1c02000 { compatible = "allwinner,sun50i-a64-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_DMA>; dma-channels = <8>; dma-requests = <27>; resets = <&ccu RST_BUS_DMA>; #dma-cells = <1>; }; tcon0: lcd-controller@1c0c000 { compatible = "allwinner,sun50i-a64-tcon-lcd", "allwinner,sun8i-a83t-tcon-lcd"; reg = <0x01c0c000 0x1000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; clock-names = "ahb", "tcon-ch0"; clock-output-names = "tcon-pixel-clock"; #clock-cells = <0>; resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; reset-names = "lcd", "lvds"; ports { #address-cells = <1>; #size-cells = <0>; tcon0_in: port@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; tcon0_in_mixer0: endpoint@0 { reg = <0>; remote-endpoint = <&mixer0_out_tcon0>; }; tcon0_in_mixer1: endpoint@1 { reg = <1>; remote-endpoint = <&mixer1_out_tcon0>; }; }; tcon0_out: port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; tcon0_out_dsi: endpoint@1 { reg = <1>; remote-endpoint = <&dsi_in_tcon0>; allwinner,tcon-channel = <1>; }; }; }; }; tcon1: lcd-controller@1c0d000 { compatible = "allwinner,sun50i-a64-tcon-tv", "allwinner,sun8i-a83t-tcon-tv"; reg = <0x01c0d000 0x1000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; clock-names = "ahb", "tcon-ch1"; resets = <&ccu RST_BUS_TCON1>; reset-names = "lcd"; ports { #address-cells = <1>; #size-cells = <0>; tcon1_in: port@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; tcon1_in_mixer0: endpoint@0 { reg = <0>; remote-endpoint = <&mixer0_out_tcon1>; }; tcon1_in_mixer1: endpoint@1 { reg = <1>; remote-endpoint = <&mixer1_out_tcon1>; }; }; tcon1_out: port@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; tcon1_out_hdmi: endpoint@1 { reg = <1>; remote-endpoint = <&hdmi_in_tcon1>; }; }; }; }; video-codec@1c0e000 { compatible = "allwinner,sun50i-a64-video-engine"; reg = <0x01c0e000 0x1000>; clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, <&ccu CLK_DRAM_VE>; clock-names = "ahb", "mod", "ram"; resets = <&ccu RST_BUS_VE>; interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; allwinner,sram = <&ve_sram 1>; }; mmc0: mmc@1c0f000 { compatible = "allwinner,sun50i-a64-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; clock-names = "ahb", "mmc"; resets = <&ccu RST_BUS_MMC0>; reset-names = "ahb"; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; max-frequency = <150000000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; mmc1: mmc@1c10000 { compatible = "allwinner,sun50i-a64-mmc"; reg = <0x01c10000 0x1000>; clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; clock-names = "ahb", "mmc"; resets = <&ccu RST_BUS_MMC1>; reset-names = "ahb"; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; max-frequency = <150000000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; mmc2: mmc@1c11000 { compatible = "allwinner,sun50i-a64-emmc"; reg = <0x01c11000 0x1000>; clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; clock-names = "ahb", "mmc"; resets = <&ccu RST_BUS_MMC2>; reset-names = "ahb"; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; max-frequency = <150000000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; sid: eeprom@1c14000 { compatible = "allwinner,sun50i-a64-sid"; reg = <0x1c14000 0x400>; #address-cells = <1>; #size-cells = <1>; ths_calibration: thermal-sensor-calibration@34 { reg = <0x34 0x8>; }; }; crypto: crypto@1c15000 { compatible = "allwinner,sun50i-a64-crypto"; reg = <0x01c15000 0x1000>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; clock-names = "bus", "mod"; resets = <&ccu RST_BUS_CE>; }; msgbox: mailbox@1c17000 { compatible = "allwinner,sun50i-a64-msgbox", "allwinner,sun6i-a31-msgbox"; reg = <0x01c17000 0x1000>; clocks = <&ccu CLK_BUS_MSGBOX>; resets = <&ccu RST_BUS_MSGBOX>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <1>; }; usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-a33-musb"; reg = <0x01c19000 0x0400>; clocks = <&ccu CLK_BUS_OTG>; resets = <&ccu RST_BUS_OTG>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mc"; phys = <&usbphy 0>; phy-names = "usb"; extcon = <&usbphy 0>; dr_mode = "otg"; status = "disabled"; }; usbphy: phy@1c19400 { compatible = "allwinner,sun50i-a64-usb-phy"; reg = <0x01c19400 0x14>, <0x01c1a800 0x4>, <0x01c1b800 0x4>; reg-names = "phy_ctrl", "pmu0", "pmu1"; clocks = <&ccu CLK_USB_PHY0>, <&ccu CLK_USB_PHY1>; clock-names = "usb0_phy", "usb1_phy"; resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>; reset-names = "usb0_reset", "usb1_reset"; status = "disabled"; #phy-cells = <1>; }; ehci0: usb@1c1a000 { compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_BUS_EHCI0>, <&ccu CLK_USB_OHCI0>; resets = <&ccu RST_BUS_OHCI0>, <&ccu RST_BUS_EHCI0>; phys = <&usbphy 0>; phy-names = "usb"; status = "disabled"; }; ohci0: usb@1c1a400 { compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; reg = <0x01c1a400 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; resets = <&ccu RST_BUS_OHCI0>; phys = <&usbphy 0>; phy-names = "usb"; status = "disabled"; }; ehci1: usb@1c1b000 { compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; reg = <0x01c1b000 0x100>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_OHCI1>, <&ccu CLK_BUS_EHCI1>, <&ccu CLK_USB_OHCI1>; resets = <&ccu RST_BUS_OHCI1>, <&ccu RST_BUS_EHCI1>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; ohci1: usb@1c1b400 { compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; reg = <0x01c1b400 0x100>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_OHCI1>, <&ccu CLK_USB_OHCI1>; resets = <&ccu RST_BUS_OHCI1>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; ccu: clock@1c20000 { compatible = "allwinner,sun50i-a64-ccu"; reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; }; pio: pinctrl@1c20800 { compatible = "allwinner,sun50i-a64-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; interrupt-controller; #interrupt-cells = <3>; /omit-if-no-ref/ aif2_pins: aif2-pins { pins = "PB4", "PB5", "PB6", "PB7"; function = "aif2"; }; /omit-if-no-ref/ aif3_pins: aif3-pins { pins = "PG10", "PG11", "PG12", "PG13"; function = "aif3"; }; csi_pins: csi-pins { pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11"; function = "csi"; }; /omit-if-no-ref/ csi_mclk_pin: csi-mclk-pin { pins = "PE1"; function = "csi"; }; i2c0_pins: i2c0-pins { pins = "PH0", "PH1"; function = "i2c0"; }; i2c1_pins: i2c1-pins { pins = "PH2", "PH3"; function = "i2c1"; }; i2c2_pins: i2c2-pins { pins = "PE14", "PE15"; function = "i2c2"; }; /omit-if-no-ref/ lcd_rgb666_pins: lcd-rgb666-pins { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", "PD20", "PD21"; function = "lcd0"; }; mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; drive-strength = <30>; bias-pull-up; }; mmc1_pins: mmc1-pins { pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; function = "mmc1"; drive-strength = <30>; bias-pull-up; }; mmc2_pins: mmc2-pins { pins = "PC5", "PC6", "PC8", "PC9", "PC10","PC11", "PC12", "PC13", "PC14", "PC15", "PC16"; function = "mmc2"; drive-strength = <30>; bias-pull-up; }; mmc2_ds_pin: mmc2-ds-pin { pins = "PC1"; function = "mmc2"; drive-strength = <30>; bias-pull-up; }; pwm_pin: pwm-pin { pins = "PD22"; function = "pwm"; }; rmii_pins: rmii-pins { pins = "PD10", "PD11", "PD13", "PD14", "PD17", "PD18", "PD19", "PD20", "PD22", "PD23"; function = "emac"; drive-strength = <40>; }; rgmii_pins: rgmii-pins { pins = "PD8", "PD9", "PD10", "PD11", "PD12", "PD13", "PD15", "PD16", "PD17", "PD18", "PD19", "PD20", "PD21", "PD22", "PD23"; function = "emac"; drive-strength = <40>; }; spdif_tx_pin: spdif-tx-pin { pins = "PH8"; function = "spdif"; }; spi0_pins: spi0-pins { pins = "PC0", "PC1", "PC2", "PC3"; function = "spi0"; }; spi1_pins: spi1-pins { pins = "PD0", "PD1", "PD2", "PD3"; function = "spi1"; }; uart0_pb_pins: uart0-pb-pins { pins = "PB8", "PB9"; function = "uart0"; }; uart1_pins: uart1-pins { pins = "PG6", "PG7"; function = "uart1"; }; uart1_rts_cts_pins: uart1-rts-cts-pins { pins = "PG8", "PG9"; function = "uart1"; }; uart2_pins: uart2-pins { pins = "PB0", "PB1"; function = "uart2"; }; uart3_pins: uart3-pins { pins = "PD0", "PD1"; function = "uart3"; }; uart4_pins: uart4-pins { pins = "PD2", "PD3"; function = "uart4"; }; uart4_rts_cts_pins: uart4-rts-cts-pins { pins = "PD4", "PD5"; function = "uart4"; }; }; timer@1c20c00 { compatible = "allwinner,sun50i-a64-timer", "allwinner,sun8i-a23-timer"; reg = <0x01c20c00 0xa0>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&osc24M>; }; wdt0: watchdog@1c20ca0 { compatible = "allwinner,sun50i-a64-wdt", "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&osc24M>; }; spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun50i-a64-spdif", "allwinner,sun8i-h3-spdif"; reg = <0x01c21000 0x400>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; resets = <&ccu RST_BUS_SPDIF>; clock-names = "apb", "spdif"; dmas = <&dma 2>; dma-names = "tx"; pinctrl-names = "default"; pinctrl-0 = <&spdif_tx_pin>; status = "disabled"; }; lradc: lradc@1c21800 { compatible = "allwinner,sun50i-a64-lradc", "allwinner,sun8i-a83t-r-lradc"; reg = <0x01c21800 0x400>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; i2s0: i2s@1c22000 { #sound-dai-cells = <0>; compatible = "allwinner,sun50i-a64-i2s", "allwinner,sun8i-h3-i2s"; reg = <0x01c22000 0x400>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; clock-names = "apb", "mod"; resets = <&ccu RST_BUS_I2S0>; dma-names = "rx", "tx"; dmas = <&dma 3>, <&dma 3>; status = "disabled"; }; i2s1: i2s@1c22400 { #sound-dai-cells = <0>; compatible = "allwinner,sun50i-a64-i2s", "allwinner,sun8i-h3-i2s"; reg = <0x01c22400 0x400>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; clock-names = "apb", "mod"; resets = <&ccu RST_BUS_I2S1>; dma-names = "rx", "tx"; dmas = <&dma 4>, <&dma 4>; status = "disabled"; }; i2s2: i2s@1c22800 { #sound-dai-cells = <0>; compatible = "allwinner,sun50i-a64-i2s", "allwinner,sun8i-h3-i2s"; reg = <0x01c22800 0x400>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; clock-names = "apb", "mod"; resets = <&ccu RST_BUS_I2S2>; dma-names = "rx", "tx"; dmas = <&dma 27>, <&dma 27>; status = "disabled"; }; dai: dai@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun50i-a64-codec-i2s"; reg = <0x01c22c00 0x200>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; clock-names = "apb", "mod"; resets = <&ccu RST_BUS_CODEC>; dmas = <&dma 15>, <&dma 15>; dma-names = "rx", "tx"; status = "disabled"; }; codec: codec@1c22e00 { #sound-dai-cells = <1>; compatible = "allwinner,sun50i-a64-codec", "allwinner,sun8i-a33-codec"; reg = <0x01c22e00 0x600>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; clock-names = "bus", "mod"; status = "disabled"; }; ths: thermal-sensor@1c25000 { compatible = "allwinner,sun50i-a64-ths"; reg = <0x01c25000 0x100>; clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; clock-names = "bus", "mod"; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; resets = <&ccu RST_BUS_THS>; nvmem-cells = <&ths_calibration>; nvmem-cell-names = "calibration"; #thermal-sensor-cells = <1>; }; uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART0>; resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART1>; resets = <&ccu RST_BUS_UART1>; status = "disabled"; }; uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART2>; resets = <&ccu RST_BUS_UART2>; status = "disabled"; }; uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART3>; resets = <&ccu RST_BUS_UART3>; status = "disabled"; }; uart4: serial@1c29000 { compatible = "snps,dw-apb-uart"; reg = <0x01c29000 0x400>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART4>; resets = <&ccu RST_BUS_UART4>; status = "disabled"; }; i2c0: i2c@1c2ac00 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C0>; resets = <&ccu RST_BUS_I2C0>; pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@1c2b000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C1>; resets = <&ccu RST_BUS_I2C1>; pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; i2c2: i2c@1c2b400 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b400 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C2>; resets = <&ccu RST_BUS_I2C2>; pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; spi0: spi@1c68000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c68000 0x1000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; dmas = <&dma 23>, <&dma 23>; dma-names = "rx", "tx"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; resets = <&ccu RST_BUS_SPI0>; status = "disabled"; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@1c69000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c69000 0x1000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; clock-names = "ahb", "mod"; dmas = <&dma 24>, <&dma 24>; dma-names = "rx", "tx"; pinctrl-names = "default"; pinctrl-0 = <&spi1_pins>; resets = <&ccu RST_BUS_SPI1>; status = "disabled"; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; }; emac: ethernet@1c30000 { compatible = "allwinner,sun50i-a64-emac"; syscon = <&syscon>; reg = <0x01c30000 0x10000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; resets = <&ccu RST_BUS_EMAC>; reset-names = "stmmaceth"; clocks = <&ccu CLK_BUS_EMAC>; clock-names = "stmmaceth"; status = "disabled"; mdio: mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; }; }; mali: gpu@1c40000 { compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; reg = <0x01c40000 0x10000>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1", "pmu"; clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; clock-names = "bus", "core"; resets = <&ccu RST_BUS_GPU>; operating-points-v2 = <&gpu_opp_table>; }; gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, <0x01c84000 0x2000>, <0x01c86000 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; interrupt-controller; #interrupt-cells = <3>; }; pwm: pwm@1c21400 { compatible = "allwinner,sun50i-a64-pwm", "allwinner,sun5i-a13-pwm"; reg = <0x01c21400 0x400>; clocks = <&osc24M>; pinctrl-names = "default"; pinctrl-0 = <&pwm_pin>; #pwm-cells = <3>; status = "disabled"; }; mbus: dram-controller@1c62000 { compatible = "allwinner,sun50i-a64-mbus"; reg = <0x01c62000 0x1000>, <0x01c63000 0x1000>; reg-names = "mbus", "dram"; clocks = <&ccu CLK_MBUS>, <&ccu CLK_DRAM>, <&ccu CLK_BUS_DRAM>; clock-names = "mbus", "dram", "bus"; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x00000000 0x40000000 0xc0000000>; #interconnect-cells = <1>; }; csi: csi@1cb0000 { compatible = "allwinner,sun50i-a64-csi"; reg = <0x01cb0000 0x1000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_CSI>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI>; clock-names = "bus", "mod", "ram"; resets = <&ccu RST_BUS_CSI>; pinctrl-names = "default"; pinctrl-0 = <&csi_pins>; status = "disabled"; }; dsi: dsi@1ca0000 { compatible = "allwinner,sun50i-a64-mipi-dsi"; reg = <0x01ca0000 0x1000>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_MIPI_DSI>; resets = <&ccu RST_BUS_MIPI_DSI>; phys = <&dphy>; phy-names = "dphy"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; port { dsi_in_tcon0: endpoint { remote-endpoint = <&tcon0_out_dsi>; }; }; }; dphy: d-phy@1ca1000 { compatible = "allwinner,sun50i-a64-mipi-dphy", "allwinner,sun6i-a31-mipi-dphy"; reg = <0x01ca1000 0x1000>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_MIPI_DSI>, <&ccu CLK_DSI_DPHY>; clock-names = "bus", "mod"; resets = <&ccu RST_BUS_MIPI_DSI>; status = "disabled"; #phy-cells = <0>; }; deinterlace: deinterlace@1e00000 { compatible = "allwinner,sun50i-a64-deinterlace", "allwinner,sun8i-h3-deinterlace"; reg = <0x01e00000 0x20000>; clocks = <&ccu CLK_BUS_DEINTERLACE>, <&ccu CLK_DEINTERLACE>, <&ccu CLK_DRAM_DEINTERLACE>; clock-names = "bus", "mod", "ram"; resets = <&ccu RST_BUS_DEINTERLACE>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; interconnects = <&mbus 9>; interconnect-names = "dma-mem"; }; hdmi: hdmi@1ee0000 { compatible = "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi"; reg = <0x01ee0000 0x10000>; reg-io-width = <1>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; phys = <&hdmi_phy>; phy-names = "phy"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; hdmi_in: port@0 { reg = <0>; hdmi_in_tcon1: endpoint { remote-endpoint = <&tcon1_out_hdmi>; }; }; hdmi_out: port@1 { reg = <1>; }; }; }; hdmi_phy: hdmi-phy@1ef0000 { compatible = "allwinner,sun50i-a64-hdmi-phy"; reg = <0x01ef0000 0x10000>; clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, <&ccu CLK_PLL_VIDEO0>; clock-names = "bus", "mod", "pll-0"; resets = <&ccu RST_BUS_HDMI0>; reset-names = "phy"; #phy-cells = <0>; }; rtc: rtc@1f00000 { compatible = "allwinner,sun50i-a64-rtc", "allwinner,sun8i-h3-rtc"; reg = <0x01f00000 0x400>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; clock-output-names = "osc32k", "osc32k-out", "iosc"; clocks = <&osc32k>; #clock-cells = <1>; }; r_intc: interrupt-controller@1f00c00 { compatible = "allwinner,sun50i-a64-r-intc", "allwinner,sun6i-a31-r-intc"; interrupt-controller; #interrupt-cells = <2>; reg = <0x01f00c00 0x400>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; }; r_ccu: clock@1f01400 { compatible = "allwinner,sun50i-a64-r-ccu"; reg = <0x01f01400 0x100>; clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; #reset-cells = <1>; }; codec_analog: codec-analog@1f015c0 { compatible = "allwinner,sun50i-a64-codec-analog"; reg = <0x01f015c0 0x4>; status = "disabled"; }; r_i2c: i2c@1f02400 { compatible = "allwinner,sun50i-a64-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x01f02400 0x400>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; clocks = <&r_ccu CLK_APB0_I2C>; resets = <&r_ccu RST_APB0_I2C>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; r_ir: ir@1f02000 { compatible = "allwinner,sun50i-a64-ir", "allwinner,sun6i-a31-ir"; reg = <0x01f02000 0x400>; clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; clock-names = "apb", "ir"; resets = <&r_ccu RST_APB0_IR>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&r_ir_rx_pin>; status = "disabled"; }; r_pwm: pwm@1f03800 { compatible = "allwinner,sun50i-a64-pwm", "allwinner,sun5i-a13-pwm"; reg = <0x01f03800 0x400>; clocks = <&osc24M>; pinctrl-names = "default"; pinctrl-0 = <&r_pwm_pin>; #pwm-cells = <3>; status = "disabled"; }; r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun50i-a64-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; interrupt-controller; #interrupt-cells = <3>; r_i2c_pl89_pins: r-i2c-pl89-pins { pins = "PL8", "PL9"; function = "s_i2c"; }; r_ir_rx_pin: r-ir-rx-pin { pins = "PL11"; function = "s_cir_rx"; }; r_pwm_pin: r-pwm-pin { pins = "PL10"; function = "s_pwm"; }; r_rsb_pins: r-rsb-pins { pins = "PL0", "PL1"; function = "s_rsb"; }; }; r_rsb: rsb@1f03400 { compatible = "allwinner,sun8i-a23-rsb"; reg = <0x01f03400 0x400>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&r_ccu 6>; clock-frequency = <3000000>; resets = <&r_ccu 2>; pinctrl-names = "default"; pinctrl-0 = <&r_rsb_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; }; };