// SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2021 Rockchip Electronics Co., Ltd * (C) Copyright 2023 Akash Gajjar */ #include "rk356x-u-boot.dtsi" / { aliases { spi0 = &sfc; }; chosen { stdout-path = &uart2; }; }; &emmc_bus8 { bootph-all; }; &emmc_clk { bootph-all; }; &emmc_cmd { bootph-all; }; &emmc_datastrobe { bootph-all; }; &fspi_pins { bootph-all; }; &pinctrl { bootph-all; }; &pcfg_pull_none { bootph-all; }; &pcfg_pull_up_drv_level_2 { bootph-all; }; &pcfg_pull_up { bootph-all; }; &sdmmc0_bus4 { bootph-all; }; &sdmmc0_clk { bootph-all; }; &sdmmc0_cmd { bootph-all; }; &sdmmc0_det { bootph-all; }; &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; }; &sfc { bootph-pre-ram; u-boot,spl-sfc-no-dma; #address-cells = <1>; #size-cells = <0>; status = "okay"; flash@0 { bootph-pre-ram; compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <24000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; }; }; &sdmmc2 { status = "disabled"; }; &uart1 { status = "disabled"; }; &uart2m0_xfer { bootph-all; }; &uart2 { clock-frequency = <24000000>; bootph-all; status = "okay"; }; &vcc5v0_usb_host { regulator-boot-on; }; &vcc5v0_usb_hub { regulator-boot-on; };