// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2019 NXP * Copyright 2022 Linaro */ #include "imx8mp-u-boot.dtsi" / { wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>; bootph-pre-ram; }; }; &iomuxc { bootph-pre-ram; }; ®_usdhc2_vmmc { bootph-pre-ram; }; &pinctrl_uart2 { bootph-pre-ram; }; &pinctrl_uart3 { bootph-pre-ram; }; &pinctrl_usdhc2_gpio { bootph-pre-ram; }; &pinctrl_usdhc2 { bootph-pre-ram; }; &pinctrl_usdhc3 { bootph-pre-ram; }; &gpio1 { bootph-pre-ram; }; &gpio2 { bootph-pre-ram; }; &gpio3 { bootph-pre-ram; }; &gpio4 { bootph-pre-ram; }; &gpio5 { bootph-pre-ram; }; &uart2 { bootph-pre-ram; }; &uart3 { bootph-pre-ram; }; &i2c1 { bootph-pre-ram; }; &i2c2 { bootph-pre-ram; }; &i2c3 { bootph-pre-ram; }; &wdog1 { bootph-pre-ram; }; &pinctrl_wdog { bootph-pre-ram; }; &pinctrl_i2c1 { bootph-pre-ram; }; &pinctrl_i2c1_gpio { bootph-pre-ram; }; &pinctrl_pmic { bootph-pre-ram; }; &{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} { bootph-pre-ram; }; &{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} { bootph-pre-ram; }; &usdhc1 { bootph-pre-ram; assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; assigned-clock-rates = <400000000>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; }; &usdhc2 { bootph-pre-ram; sd-uhs-sdr104; sd-uhs-ddr50; assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; assigned-clock-rates = <400000000>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; }; &usdhc3 { bootph-pre-ram; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; assigned-clock-rates = <400000000>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; }; &binman { itb { fit { images { fip { description = "Trusted Firmware FIP"; type = "firmware"; arch = "arm64"; compression = "none"; load = <0x40310000>; fip_blob: blob-ext{ filename = "fip.bin"; }; }; }; }; }; }; /* This cannot work since it refers to a template node &binman_configuration { loadables = "atf", "fip"; }; */