#include "skeleton.dtsi" #include <dt-bindings/clock/tegra186-clock.h> #include <dt-bindings/gpio/tegra186-gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/tegra186-hsp.h> #include <dt-bindings/power/tegra186-powergate.h> #include <dt-bindings/reset/tegra186-reset.h> / { compatible = "nvidia,tegra186"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; gpio_main: gpio@2200000 { compatible = "nvidia,tegra186-gpio"; reg-names = "security", "gpio"; reg = <0x0 0x2200000 0x0 0x10000>, <0x0 0x2210000 0x0 0x10000>; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; ethernet@2490000 { compatible = "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"; reg = <0x0 0x02490000 0x0 0x10000>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, <&bpmp TEGRA186_CLK_EQOS_AXI>, <&bpmp TEGRA186_CLK_EQOS_RX>, <&bpmp TEGRA186_CLK_EQOS_PTP_REF>, <&bpmp TEGRA186_CLK_EQOS_TX>; clock-names = "slave_bus", "master_bus", "rx", "ptp_ref", "tx"; resets = <&bpmp TEGRA186_RESET_EQOS>; reset-names = "eqos"; phy-mode = "rgmii"; status = "disabled"; }; uarta: serial@3100000 { compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; reg = <0x0 0x03100000 0x0 0x10000>; reg-shift = <2>; status = "disabled"; }; gen1_i2c: i2c@3160000 { compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x3160000 0x0 0x100>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&bpmp TEGRA186_CLK_I2C1>; clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C1>; reset-names = "i2c"; status = "disabled"; }; cam_i2c: i2c@3180000 { compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x3180000 0x0 0x100>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&bpmp TEGRA186_CLK_I2C3>; clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C3>; reset-names = "i2c"; status = "disabled"; }; dp_aux_ch1_i2c: i2c@3190000 { compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x3190000 0x0 0x100>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&bpmp TEGRA186_CLK_I2C4>; clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C4>; reset-names = "i2c"; status = "disabled"; }; dp_aux_ch0_i2c: i2c@31b0000 { compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x31b0000 0x0 0x100>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&bpmp TEGRA186_CLK_I2C6>; clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C6>; reset-names = "i2c"; status = "disabled"; }; gen7_i2c: i2c@31c0000 { compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x31c0000 0x0 0x100>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&bpmp TEGRA186_CLK_I2C7>; clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C7>; reset-names = "i2c"; status = "disabled"; }; gen9_i2c: i2c@31e0000 { compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0x31e0000 0x0 0x100>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&bpmp TEGRA186_CLK_I2C9>; clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C9>; reset-names = "i2c"; status = "disabled"; }; sdhci@3400000 { compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03400000 0x0 0x200>; resets = <&bpmp TEGRA186_RESET_SDMMC1>; reset-names = "sdhci"; clocks = <&bpmp TEGRA186_CLK_SDMMC1>; interrupts = <GIC_SPI 62 0x04>; status = "disabled"; }; sdhci@3460000 { compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03460000 0x0 0x200>; resets = <&bpmp TEGRA186_RESET_SDMMC4>; reset-names = "sdhci"; clocks = <&bpmp TEGRA186_CLK_SDMMC4>; interrupts = <GIC_SPI 31 0x04>; status = "disabled"; }; gic: interrupt-controller@3881000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x3881000 0x0 0x1000>, <0x0 0x3882000 0x0 0x2000>, <0x0 0x3884000 0x0 0x2000>, <0x0 0x3886000 0x0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; interrupt-parent = <&gic>; }; hsp: hsp@3c00000 { compatible = "nvidia,tegra186-hsp"; reg = <0x0 0x03c00000 0x0 0xa0000>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "doorbell"; #mbox-cells = <2>; }; gen2_i2c: i2c@c240000 { compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0xc240000 0x0 0x100>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&bpmp TEGRA186_CLK_I2C2>; clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C2>; reset-names = "i2c"; status = "disabled"; }; gen8_i2c: i2c@c250000 { compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; reg = <0x0 0xc250000 0x0 0x100>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&bpmp TEGRA186_CLK_I2C8>; clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C8>; reset-names = "i2c"; status = "disabled"; }; gpio_aon: gpio@c2f0000 { compatible = "nvidia,tegra186-gpio-aon"; reg-names = "security", "gpio"; reg = <0x0 0xc2f0000 0x0 0x1000>, <0x0 0xc2f1000 0x0 0x1000>; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; pcie-controller@10003000 { compatible = "nvidia,tegra186-pcie"; device_type = "pci"; reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ reg-names = "pads", "afi", "cs"; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, /* MSI interrupt */ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; /* Wake interrupt */ interrupt-names = "intr", "msi", "wake"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; bus-range = <0x00 0xff>; #address-cells = <3>; #size-cells = <2>; ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07f00000 /* non-prefetchable memory (127 MiB) */ 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ clocks = <&bpmp TEGRA186_CLK_PCIE>, <&bpmp TEGRA186_CLK_AFI>; clock-names = "pex", "afi"; resets = <&bpmp TEGRA186_RESET_PCIE>, <&bpmp TEGRA186_RESET_AFI>, <&bpmp TEGRA186_RESET_PCIEXCLK>; reset-names = "pex", "afi", "pcie_x"; power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; status = "disabled"; pci@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; reg = <0x000800 0 0 0 0>; status = "disabled"; #address-cells = <3>; #size-cells = <2>; ranges; nvidia,num-lanes = <2>; }; pci@2,0 { device_type = "pci"; assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; reg = <0x001000 0 0 0 0>; status = "disabled"; #address-cells = <3>; #size-cells = <2>; ranges; nvidia,num-lanes = <1>; }; pci@3,0 { device_type = "pci"; assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; reg = <0x001800 0 0 0 0>; status = "disabled"; #address-cells = <3>; #size-cells = <2>; ranges; nvidia,num-lanes = <1>; }; }; sysram@30000000 { compatible = "nvidia,tegra186-sysram", "mmio-sram"; reg = <0x0 0x30000000 0x0 0x50000>; #address-cells = <2>; #size-cells = <2>; ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; sysram_cpu_bpmp_tx: shmem@4e000 { compatible = "nvidia,tegra186-bpmp-shmem"; reg = <0x0 0x4e000 0x0 0x1000>; }; sysram_cpu_bpmp_rx: shmem@4f000 { compatible = "nvidia,tegra186-bpmp-shmem"; reg = <0x0 0x4f000 0x0 0x1000>; }; }; bpmp: bpmp { compatible = "nvidia,tegra186-bpmp"; mboxes = <&hsp HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>; /* * In theory, these references, and the configuration in the * node these reference point at, are board-specific, since * they depend on the BCT's memory carve-out setup, the * firmware that's actually loaded onto the BPMP, etc. However, * in practice, all boards are likely to use identical values. */ shmem = <&sysram_cpu_bpmp_tx &sysram_cpu_bpmp_rx>; #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; bpmp_i2c: i2c { compatible = "nvidia,tegra186-bpmp-i2c"; nvidia,bpmp-bus-id = <5>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; };