Commit graph

5613 commits

Author SHA1 Message Date
Masahiro Yamada
845034e6b2 mtd: denali: add Denali NAND driver for SPL
The SPL-mode driver for Denali(Cadence) NAND Flash Memory Controller IP.

This driver requires two CONFIG macros:
 - CONFIG_SPL_NAND_DENALI
     Define to enable this driver.
 - CONFIG_SYS_NAND_BAD_BLOCK_POS
     Specify bad block mark position in the oob space. Typically 0.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Scott Wood <scottwood@freescale.com>
2014-10-05 14:10:09 +09:00
Masahiro Yamada
4b0abf9f3c mtd: denali: add Denali controller configs to Kconfig
Commit 3eb3e72a3f (nand/denali: Adding Denali NAND driver support)
introduced some new options, and some of them were documented by
commit f9860cf081 (nand/denali: Document CONFIG symbols).

This commit allows users to enable/disable them via Kconfig
with more detailed help docs.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Scott Wood <scottwood@freescale.com>
2014-10-05 14:10:09 +09:00
Pavel Machek
b966db0d72 dw_mmc: cleanups
dw_mmc driver was responding to errors with debug(). Change that to
prinf so that any errors are immediately obvious. Also adjust english
in comments.

Signed-off-by: Pavel Machek <pavel@denx.de>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-10-03 17:26:50 +03:00
Mario Schuknecht
786a27b7ec mmc: Fix mmc bus width
After setting the bus width, the extended CSD register is read. Some selected
fields are compared with previously read extended CSD register fields. In this
comparison the EXT_CSD_ERASE_GROUP_DEF field is compared. But this field is
previously written under certain circumstances. And then the comparison fails.

Only compare read-only fields. Therefore compare field EXT_CSD_HC_WP_GRP_SIZE
instead of field EXT_CSD_ERASE_GROUP_DEF.

Signed-off-by: Mario Schuknecht <mario.schuknecht@dresearch-fe.de>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-10-03 17:26:50 +03:00
Mario Schuknecht
bcd06989b8 mvebu_mmc: Driver addition
In function mvebu_mmc_write notice command timeout. It is possible that a
command is done, but a timeout occurred.

Enable timeout in set bus function.

Set window registers. Without that I could not use the driver on a Kirkwood
88F6282 SoC.

Set high capacity and 52MHz driver feature.

Signed-off-by: Mario Schuknecht <mario.schuknecht@dresearch-fe.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-10-03 17:26:50 +03:00
Peter Bigot
6dc93e7087 mmc: restore capacity when switching to partition 0
The capacity and lba for an MMC device with part_num 0 reflects the
whole device.  When mmc_switch_part() successfully switches to a
partition, the capacity is changed to that partition.  As partition 0
does not physically exist, attempts to switch back to the whole device
will indicate an error, but the capacity setting for the whole device
must still be restored to match the partition.

Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Tested-by: Tom Rini <trini@ti.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-10-03 17:26:50 +03:00
Hannes Petermaier
021a80559f mmc: fix ERASE_GRP_DEF handling
if we set manually this bit on the eMMC card using mmc_switch(...),
we also have to set it within our (before read) internal structure
'ext_csd'.

Otherwise following checks on this will fail.

Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
2014-10-03 17:26:49 +03:00
Sonic Zhang
282a82e8a1 mmc: set correct block size value in bfin sdh driver
Wait data transfer till the data end bit other than the data block end
bit is set.

Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2014-10-03 17:26:49 +03:00
Ye.Li
5546ad0734 usb: ehci-mx6: Rename the USB register base address
The mx6sl/mx6sx has 2 OTG and 1 host. So they have name
"USBO2H_USB_BASE_ADDR" in imx-regs.h. The driver hard codes
the USB base address name to "USBOH3", which causes the driver
failed to build for mx6sl/mx6sx.

This patch uniform the address name to "USB_BASE_ADDR" for all
mx6 series.

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-09-29 10:33:27 +02:00
Marek Vasut
dd24b57bb7 usb: ehci: mxs: Add board-specific callbacks
Add board-specific callbacks for enabling/disabling port power
into the MXS EHCI controller driver. This is in-line with the
names of callbacks on other systems.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2014-09-29 09:02:16 +02:00
Tom Rini
be9f643ae6 Merge branch 'for-tom' of git://git.denx.de/u-boot-dm 2014-09-26 20:10:48 -04:00
Simon Glass
110bdee00f sandbox: Convert SPI flash emulation to use sf_params
At present sandbox has its own table of supported SPI flash chips. Now that
the SPI flash system is fully consolidated and has its own list, sandbox
should use that.

This enables us to expand the number of chips that sandbox supports.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-26 15:00:36 -06:00
Tom Rini
2c2277f15c Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2014-09-26 09:57:52 -04:00
Tom Rini
2c3dc792b6 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-09-26 09:51:18 -04:00
Chin Liang See
3eb3e72a3f nand/denali: Adding Denali NAND driver support
To add the Denali NAND driver support into U-Boot.
This driver is leveraged from Linux with commit ID
fdbad98dff8007f2b8bee6698b5d25ebba0471c9. For Denali
controller 64 variance, you need to declare macro
CONFIG_SYS_NAND_DENALI_64BIT.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-25 13:43:16 -05:00
Stefan Roese
be16aba5ce mtd: nand: Fix length bug in ioread16_rep() and iowrite16_rep()
The ioread16_rep() and iowrite16_rep() implementations are U-Boot specific
and have been introduced with the Linux MTD v3.14 sync. While introducing
these functions, the length for the loop has been miscalculated. The ">> 1"
is already present in the caller. So lets remove it in the function.

Tested on omap3_ha.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Acked-by: Heiko Schocher <hs@denx.de>
2014-09-25 13:43:00 -05:00
Rostislav Lisovy
2f665945b3 mtd: nand: am335x: Fix 'bit-flip' errors in SPL
OMAP GPMC driver used with some NAND Flash devices
(e.g. Spansion S34ML08G1) causes that U-boot shows
hundreds of 'nand: bit-flip corrected' error messages.
Possible cause was discussed in the mailinglist thread:
http://lists.denx.de/pipermail/u-boot/2014-April/177508.html

The issue was partially fixed with the cc81a5291910d7a.git
however this has to be done to fix the SPL.

The original author of the code is Belisko Marek
<marek.belisko@gmail.com>

Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
2014-09-25 13:43:00 -05:00
York Sun
f80d6472b4 driver/ddr/fsl: Fix DDR4 driver
When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set
to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins
are not actually connected.

Also fix a bug when reading from DDR register to use proper accessor for
correct endianess.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-25 08:36:20 -07:00
York Sun
bb5783224b driver/ddr/fsl: Fix tXP and tCKE
The driver was written using old DDR3 spec which only covers low speeds.
The value would be suboptimal for higher speeds. Fix both timing according
to latest DDR3 spec, remove tCKE as an config option.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-25 08:36:18 -07:00
York Sun
1d71efbb03 driver/ddr: Restruct driver to allow standalone memory space
U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-25 08:36:18 -07:00
Prabhakar Kushwaha
5b8388a827 driver/mtd: Use generic timer API for FSL IFC, eLBC
Freescale's flash control driver is using architecture specific timer API
i.e. usec2ticks

Replace usec2ticks with get_timer() (generic timer API)

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-09-25 08:36:17 -07:00
Masahiro Yamada
f494e0a184 kbuild: refactor some makefiles
[1] Move driver/core/, driver/input/ and drivers/input/ entries
    from the top Makefile to drivers/Makefile

[2] Remove the conditional by CONFIG_DM in drivers/core/Makefile
    because the whole drivers/core directory is already selected
    by CONFIG_DM in the upper level

[3] Likewise for CONFIG_DM_DEMO in drivers/demo/Makefile

[4] Simplify common/Makefile - both CONFIG_DDR_SPD and
    CONFIG_SPD_EEPROM are boolean macros so they can directly
    select objects

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
2014-09-24 18:30:29 -04:00
Masahiro Yamada
c79cba37b3 cosmetic: replace MIN, MAX with min, max
The macro MIN, MAX is defined as the aliase of min, max,
respectively.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-24 18:30:29 -04:00
Masahiro Yamada
ed36323f6d kconfig: add blank Kconfig files
This would be useful to start moving various config options.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-09-24 18:30:28 -04:00
Marcel Ziswiler
a4277200a2 e1000: fix no nvm build
Fix the following build error in case CONFIG_E1000_NO_NVM is enabled:
	  CC      drivers/net/e1000.o
	drivers/net/e1000.c: In function ‘e1000_initialize’:
	drivers/net/e1000.c:5365:5: error: ‘struct e1000_hw’ has no
		member named ‘eeprom_semaphore_present’
	make[1]: *** [drivers/net/e1000.o] Error 1
	make: *** [drivers/net] Error 2
Acked-by: Marek Vasut <marex@denx.de>
2014-09-24 18:30:27 -04:00
Steve Rae
593cbd93f3 usb/gadget: fastboot: minor cleanup
- update static function
- additional debugging statements
- update "fastboot command" information
- add missing include file
- update spelling

Signed-off-by: Steve Rae <srae@broadcom.com>
2014-09-24 18:30:27 -04:00
Steve Rae
d1b5ed0753 usb/gadget: fastboot: add support for flash command
- implement 'fastboot flash' for eMMC devices

Signed-off-by: Steve Rae <srae@broadcom.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2014-09-24 18:30:27 -04:00
Priyanka Jain
5273aa3834 board/t1040qds: Add sgmii ports support in 0xA7 protocol
T1042QDS (T1042 is T1040 Personality without L2 switch) supports following
sgmii interfaces with serdes protocol 0xA7
-SGMII-MAC3 on Lane B - slot 7
-SGMII-MAC5 on Lane H - slot 7
-SGMII2.5G-MAC1 on Lane C - slot 6
-SGMII2.5G-MAC2 on Lane D - slot 5

Add support of above sgmii interfaces

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
2014-09-24 13:12:16 -07:00
Stefan Roese
bf9b86dc47 spi: kirkwood_spi.c: cosmetic: Fix minor coding style issues
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Tested-by: Luka Perkov <luka@openwrt.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24 17:48:56 +05:30
Stefan Roese
0299046e5b spi: kirkwood_spi.c: Make global variable static
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Tested-by: Luka Perkov <luka@openwrt.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24 17:48:27 +05:30
Stefan Roese
c032174f82 spi: kirkwood_spi.c: Some fixes and cleanup
This patch introduces the clrsetbits_le32() accessor functions in the
kirkwood SPI driver. Note that it also includes a fix:

-	 writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, &spireg->ctrl);
+	 writel(KWSPI_SMEMRDY, &spireg->ctrl);

Here the bit KWSPI_CSN_ACT (0x1) should have been cleared. Instead
0xfffffffe is written into this control register. This is the main
reason to use the clrsetbits() functions now. As they make clearing
bits much less error prone.

Additionally KWSPI_IRQUNMASK is not used in spi_cs_activate() and
spi_cs_deactivate() any more. Its the wrong macro but has the same
value as the correct one (KWSPI_CSN_ACT).

This is in preparation for use of this driver on the Marvell Armada XP
platform as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Tested-by: Luka Perkov <luka@openwrt.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24 17:47:53 +05:30
Stefan Roese
31969b8993 sf: Add M25PX64 SPI NOR flash ID
Add ID for this Numonix / STMicro chip.

Tested on Marvell DB-78460-BP board.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24 17:46:25 +05:30
Nikita Kiryanov
88e34e5ff7 spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_*
Currently, CONFIG_SPL_SPI_* #defines are used for controlling SPI boot in
SPL. These #defines do not allow the user to select SPI mode for the SPI flash
(there's no CONFIG_SPL_SPI_MODE, so the SPI mode is hardcoded in
spi_spl_load.c), and duplicate information already provided by
CONFIG_SF_DEFAULT_* #defines.

Kill CONFIG_SPL_SPI_*, and use CONFIG_SF_DEFAULT_* instead.

Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Hannes Petermaier <hannes.petermaier@br-automation.com>
Cc: Michal Simek <monstr@monstr.eu>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24 17:40:10 +05:30
Nikita Kiryanov
155fa9af95 spi: mxc: fix sf probe when using mxc_spi
MXC SPI driver has a feature whereas a GPIO line can be used to force CS high
across multiple transactions. This is set up by embedding the GPIO information
in the CS value:

cs = (cs | gpio << 8)

This merge of cs and gpio data into one value breaks the sf probe command:
if the use of gpio is required, invoking "sf probe <cs>" will not work, because
the CS argument doesn't have the GPIO information in it. Instead, the user must
use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force
cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must
type "sf probe 15872".

This is inconsistent with the description of the sf probe command, and forces
the user to be aware of implementaiton details.

Fix this by introducing a new board function: board_spi_cs_gpio(), which will
accept a naked CS value, and provide the driver with the relevant GPIO, if one
is necessary.

Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Eric Benard <eric@eukrea.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24 17:25:39 +05:30
Nikita Kiryanov
01d2aaf61b mtd: spi: add support for M25PE16 and M25PX16
Add support for M25PE16 and M25PX16

Cc: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24 17:25:16 +05:30
Robert Baldyga
cae025aab3 dm: avoid dev->req_seq overflow
Since dev->req_seq value is initialized from "reg" property of fdt node,
there is posibility, that address value contained in fdt is greater than
INT_MAX, and then value in dev->req_seq is negative which led to probe()
fail.

This patch fix this problem by ensuring that req_seq is positive, unless
it's one of errno codes.

Signed-off-by: Robert Baldyga <r.baldyga@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-09-23 12:44:31 -06:00
Simon Glass
59990bf0ea dm: serial: Don't require device tree to configure a console
Allow serial_find_console_or_panic() to work without a device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-23 12:44:30 -06:00
Simon Glass
91cbd792c4 dm: core: Allow device_bind() to used without CONFIG_OF_CONTROL
The sequence number support in driver model requires device tree control.
It should be skipped if CONFIG_OF_CONTROL is not defined, and should not
require functions from fdtdec.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-23 12:44:30 -06:00
Simon Glass
bf1a86fca0 sf: Add an empty entry to the parameter list
The list is supposed to be terminated with a NULL name, but is not. If a
board probes a chip which does not appear in the table, U-Boot will crash
(at least on sandbox).

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-23 12:44:30 -06:00
Stefano Babic
42817eb85d Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-09-22 15:51:01 +02:00
Boris BREZILLON
d357b94041 mtd: atmel_nand: Disable subpage NAND write when using Atmel PMECC
Disable subpage write when using PMECC to prevent buggy partial page write.

This fix has been taken from linux sources (see commit
90445ff6241e2a13445310803e2efa606c61f276)

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-19 00:11:22 +02:00
Bo Shen
97b2043da6 USB: ehci-atmel: use pcr to enable or disable clock
If the SoC has pcr, we use pcr (peripheral control register)
to enable or disable clock.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-19 00:11:21 +02:00
Bo Shen
01c8bf5a6f USB: ohci-at91: use pcr to enable or disable clock
If the SoC has pcr, we use pcr (peripheral control register)
to enable or disable clock.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-19 00:11:20 +02:00
Wu, Josh
14b3b44eda mtd: atmel-nand: use pmecc_readl(b)/pmecc_writel to access the pmecc register
We defined the macro pmecc_readl(b)/pmecc_writel for pmecc register access.
But in the driver we also use the readl(b)/writel.
To keep consistent, this patch make all use pmecc_readl(b)/pmecc_writel.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-19 00:11:13 +02:00
Tom Rini
e38b15b061 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-09-17 18:01:04 -04:00
Simon Glass
ad6e48e509 net: usb: Add SMSC copyright to smsc95xx driver
This driver was upstreamed without an SMSC copyright, even thought it seems
that SMSC was the original author.

See the kernel version for a code comparison:

http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=2f7ca802bdae2ca41022618391c70c2876d92190

It's not clear who actually moved this code, or whether the kernel was the
original source, or somewhere else, but it probably should still have the
SMSC copyright.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-16 12:23:59 -04:00
maxin.john@enea.com
5da163d665 mtdcore: Fix a build error with CONFIG_CMD_MTDPARTS_SPREAD
This patch fixes the build error for CONFIG_CMD_MTDPARTS_SPREAD

Signed-off-by: Maxin B. John <maxin.john@enea.com>
2014-09-16 12:23:59 -04:00
Khoronzhuk, Ivan
7206111e52 mtd: nand: davinci_nand: update write_page function for keystone RBL
After mtd was synced with Linux 3.14
(ff94bc40af)
the number of parameters for write_page function of nand_chip was
changed. The additional two var were needed for subpage write.
As keystone has no supbage write they are not needed. So correct
only function definition by upgrading it's parameter list.
That helps to get ritd of compilation warning.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-09-16 12:23:59 -04:00
Masahiro Yamada
3b61297024 kbuild: force to define __UBOOT__ in all the C sources
U-Boot has imported various source files from other projects,
mostly Linux.

Something like

  #ifdef __UBOOT__
    [ modification for U-Boot ]
  #else
    [ original code ]
  #endif

is an often used strategy for clarification of adjusted parts,
that is, easier re-sync in future.

Instead of defining __UBOOT__ in each source file,
passing it from the top Makefile would be easier.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
2014-09-16 12:23:56 -04:00
Thierry Reding
5d9f423ddb rtl8169: Defer network packet processing
When network protocol errors occur (such as a file not being found on a
TFTP server), the processing done by the NetReceive() function will end
up calling the driver's .halt() implementation. However, after that the
device no longer has access to the memory buffers and will cause errors
such as this in the rtl_recv() function when trying to hand descriptors
back to the device:

	pci_hose_bus_to_phys: invalid physical address

This can be fixed by deferring processing of network packets until the
descriptors have been handed back. That way rtl_halt() tearing down
network buffers is not going to prevent access to the buffers.

Reported-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-09-16 12:23:45 -04:00
Stefan Agner
72d7beabf7 mtd: nand: add Freescale vf610_nfc driver
This adds initial support for Freescale NFC (NAND Flash Controller)
found in ARM Vybrid SoC's, Power Architecture MPC5125 and others.
The driver is called vf610_nfc since this is the first supported
and tested hardware platform supported by the driver.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
2014-09-16 13:25:18 +02:00
Vasili Galka
9f680d2d97 openrisc: Fix a few type cast related warnings
Use size_t type for positive offsets instead of the loff_t type. The
later is defined as long long, which is larger than the pointer type
on OpenRISC architecture and therefore the following warning was
generated:

"warning: cast to pointer from integer of different size"

Signed-off-by: Vasili Galka <vvv444@gmail.com>
2014-09-15 13:32:56 -04:00
Tom Rini
8d028d404f Merge branch 'master' of git://git.denx.de/u-boot-dm 2014-09-13 16:32:52 -04:00
Tom Rini
114cc4290b Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-09-12 11:27:46 -04:00
Simon Glass
858530a8c0 dm: tegra: Enable driver model for serial
Use driver model for serial ports.

Since Tegra now uses driver model for serial, adjust the definition of
V_NS16550_CLK so that it is clear that this is only used for SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 13:00:02 -06:00
Simon Glass
12e431b277 dm: serial: Add driver model support for ns16550
Add driver model support so that ns16550 can support operation both with
and without driver model.

The driver needs a clock frequency so cannot stand alone unfortunately. The
clock frequency must be provided by a separate driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 13:00:01 -06:00
Simon Glass
8bbe33c829 dm: serial: Collect common baud rate code in ns16550
The same sequence is used in several places, so move it into a function.
Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 13:00:01 -06:00
Simon Glass
fa54eb1243 dm: serial: Move baud rate calculation to ns16550.c
Move the function that calculates the baud rate divisor into ns16550.c so
it can be used by that file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 13:00:01 -06:00
Simon Glass
72e98228c3 sandbox: serial: Support a coloured console
The current sandbox serial driver is a pretty trivial example and does not
have the featues that might be needed for other board serial drivers. To
help provide a better example, add a text colour property to the device
tree for sandbox. This uses platform data, a device tree node, driver
private data and a remove() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 13:00:00 -06:00
Simon Glass
890fcefe2e sandbox: Convert serial driver to use driver model
Adjust the sandbox serial driver to use the new driver model uclass. The
driver works much as before, but within the new framework.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 13:00:00 -06:00
Simon Glass
57d92753d4 dm: Add a uclass for serial devices
Serial devices support simple byte input/output and a few operations to find
out whether data is available. Add a basic uclass for serial devices to be
used by drivers that are converted to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 13:00:00 -06:00
Simon Glass
1f359e3611 dm: Adjust lists_bind_fdt() to return the bound device
Allow the caller to find out the device that was bound in response to this
call.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 12:59:59 -06:00
Simon Glass
addf9513d0 serial: Set up the 'priv' pointer when creating a serial device
The stdio_dev structure has a private pointer for its creator, but it is
not set up by the serial system. Set it to point to the serial device so
that it can be found by code called by stdio.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 12:59:59 -06:00
Simon Glass
2fccd2d96b tegra: Convert tegra GPIO driver to use driver model
This is an implementation of GPIOs for Tegra that uses driver model. It has
been tested on trimslice and also using the new iotrace feature.

The implementation uses a top-level GPIO device (which has no actual GPIOS).
Under this all the banks are created as separate GPIO devices.

The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7,
..., Z0..Z7, AA0..AA7, etc.

Since driver model is not yet available before relocation, or in SPL, a
special function is provided for seaboard's SPL code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 12:59:59 -06:00
Fabio Estevam
1b8ad74a6f pcie_imx: Add mx6solox support
Let PCI on mx6solox also be supported.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2014-09-09 17:24:49 +02:00
Stefan Agner
89e69fd4a9 arm: vf610: lpuart: disable FIFO on initializaton
UART does not use the UART FIFO, but we should also not rely that
the UART FIFO is diabled by default. For instance, when loading
U-Boot using the boot ROMs serial downloader protocol over UART,
FIFO is enabled at U-Boot start time.

This patch disables the RX and TX FIFO, sets back their thresholds
and flushes them.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-09-09 16:54:16 +02:00
Stefan Agner
a3db78d887 arm: vf610: lpuart: fix status register handling
The status register 1 (S1) is not writeable, hence we should not
write it. In order to clear the RDRF flag we only need to read
the data register.

Also, when stressing U-Boot a lot with serial input, an overflow can
occur which asserts the S1_OR flag (while not asserting the S1_RDRF
flag). To clear this flag we again just need to read the data
register, hence add this flag to the abort conditions for the while
loop.

Insert a compiler barrier to make sure reading the data register
gets executed after reading the status register.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-09-09 16:52:44 +02:00
Tim Harvey
0991866cf7 pci: add support for board_pci_fixup_dev function
Some board-level drivers may wish to have per-device fixup functions
for PCI devices.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09 16:15:02 +02:00
Nikita Kiryanov
dc383dd583 sata: dwc_ahsata: implement sata_port_status
Define the new common function sata_port_status() which can be
used to query the sata driver for the state of ports, and implement it
for dwc_ahsata.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:32:32 +02:00
Fabio Estevam
f599288d55 net: fec_mxc: Poll FEC_TBD_READY after polling TDAR
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
always cleared prior then the READY bit is cleared in the last BD, which causes
FEC packets reception to always fail.

As explained by Ye Li:

"The TDAR bit is cleared when the descriptors are all out from TX ring, but on
mx6solox we noticed that the READY bit is still not cleared right after TDAR.
These are two distinct signals, and in IC simulation, we found that TDAR always
gets cleared prior than the READY bit of last BD becomes cleared.
In mx6solox, we use a later version of FEC IP. It looks like that this
intrinsic behaviour of TDAR bit has changed in this newer FEC version."

Fix this by polling the READY bit of BD after the TDAR polling, which covers the
mx6solox case and does not harm the other SoCs.

No performance drop has been noticed with this patch applied when testing TFTP
transfers on several boards of different i.mx SoCs.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2014-09-09 15:06:12 +02:00
Fabio Estevam
db5b7f566e net: fec_mxc: Adjust RX DMA alignment for mx6solox
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
Other SoCs work with the standard 32 bytes alignment.

Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
which addresses the needs from mx6solox and also works for the other SoCs.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2014-09-09 15:05:37 +02:00
Albert ARIBAUD
b653516769 Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2014-09-09 00:21:24 +02:00
Wang Huan
327def5060 video: dcu: Add DCU driver support
This patch is to add DCU driver support. DCU also named
2D-ACE(Two Dimensional Animation and Compositing Engine)
is a system master that fetches graphics stored in internal
or external memory and displays them on a TFT LCD panel.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08 10:30:35 -07:00
Jingchang Lu
6209e14cb0 serial: lpuart: add 32-bit registers lpuart support
On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers
are 32-bit. This patch adds the support for 32-bit registers on
LS102xA.

Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
2014-09-08 10:30:35 -07:00
York Sun
ef87cab664 driver/ddr/fsl: Add support of overriding chip select write leveling
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-08 10:30:34 -07:00
York Sun
5cb27c5d44 driver/ddr/freescale: Fix DDR3 driver for ARM
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-08 10:30:34 -07:00
York Sun
d28cb67142 driver/ddr/freescale: Add support of accumulate ECC
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-08 10:30:34 -07:00
Wang Huan
19060bd886 ls102xa: esdhc: Add esdhc support for LS102xA
For LS1, esdhc is big-endian IP. Accessing the registers
should be in big-endian mode. So we use esdhc_read32()
to read Host controller capabilities register for LS1.

For LS1, when using CMD12, cmdtype need to be set to
ABORT, otherwise, next read command will hang.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08 10:30:34 -07:00
Alison Wang
52d00a812a ls102xa: etsec: Add etsec support for LS102xA
This patch is to add etsec support for LS102xA. First, Little-endian
descriptor mode should be enabled. So RxBDs and TxBDs are interpreted
with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET
are different from PowerPC, redefine them for LS1021xA.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08 10:30:33 -07:00
Alison Wang
d2614ea0ff net: mdio: Use mb() to be compatible for both ARM and PowerPC
Use mb() instead of sync assembly instruction to be
compatible for both ARM and PowerPC.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08 10:30:33 -07:00
Claudiu Manoil
93f26f130e net: Merge asm/fsl_enet.h into fsl_mdio.h
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.

To remove the arch dependency, merge the content of
asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h
only for phy.h. These were updated to include phy.h instead.

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
2014-09-08 10:30:33 -07:00
Wang Huan
df0a5b880d ls102xa: i2c: Add i2c support for LS102xA
The existing i.MX's I2C driver mxc_i2c.c is compatible
with the controller of LS102xA. As I2C's registers
are 8-bit on LS102xA, I2C_QUIRK_REG is enabled to
use 8-bit driver.

This patch is to add I2C 1,2,3 support for LS102xA.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08 10:30:32 -07:00
Wang Huan
d60a2099a2 arm: ls102xa: Add Freescale LS102xA SoC support
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.

Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-09-08 10:30:32 -07:00
Vadim Bendebury
9e8f664ecb video: Add driver for Parade PS8625 dP to LVDS bridge
The initialization table comes from the "Illustration of I2C command
for initialing PS8625" document supplied by Parade.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Ajay Kumar
45c480c9f6 video: exynos_fimd: Add framework to disable FIMD sysmmu
On Exynos5420 and newer versions, the FIMD sysmmus are in
"on state" by default.
We have to disable them in order to make FIMD DMA work.
This patch adds the required framework to exynos_fimd driver,
and disables FIMD sysmmu on Exynos5420.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Ajay Kumar
f0017175e3 exynos_fb: Remove usage of static defines
Previously, we used to statically assign values for vl_col, vl_row and
vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.

Introducing the function exynos_lcd_early_init() would take care of this
assignment on the fly by parsing FIMD DT properties, thereby allowing us
to remove LCD_XRES and LCD_YRES from the main config file.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Rostislav Lisovy
cc81a52919 mtd: nand: omap_gpmc: Fix 'bit-flip' errors
OMAP GPMC driver used with some NAND Flash devices (e.g. Spansion
S34ML08G1) causes that U-boot shows hundreds of 'nand: bit-flip
corrected' error messages. Possible cause was discussed in the
mailinglist thread:
http://lists.denx.de/pipermail/u-boot/2014-April/177508.html

Quote (Author: Pekon Gupta <pekon@ti.com>): "The issue is mainly
due to a NAND protocol violation in the omap driver since the
Random Data Output command (05h-E0h) expects to see only the
column address that should be addressed within the already loaded
read page into the read buffer. Only 2 address cycles with ALE
active should be provided between the 05h and E0h commands. The
Page read command expects the full address footprint (2bytes for
column address + 3bytes for row address), but once the page is
loaded into the read buffer, Random Data Output should be used
with only 2bytes for column address."

This patch combines the solution proposed in the mailinglist and
the patch provided by the Spansion company (GPLv2 code, source:
http://www.spansion.com/Support/Software/u-boot-psp-04.04.00.01-NAND.zip)

Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
2014-09-04 13:06:00 -04:00
Rostislav Lisovy
5c3f7e0ead mtd: nand: omap_gpmc: Enable multiple NAND flash devices
Since the CS of a device connected to the GPMC was
stored in the global variable, it was not possible to
use multiple devices. In this patch the CS is stored per
device in its 'struct omap_nand_info'. This makes it
possible to use up to 'GPMC_MAX_CS' NAND Flash devices
connected to U-boot.

Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
2014-09-04 13:06:00 -04:00
Khoronzhuk, Ivan
fc12a1f589 mtd: nand: davinci_nand: correct keystone RBL layout definition
In case when 4K page keystone RBL layout is used the compilation
error is appeared. That's because the #ifdef has to be placed under
struct name. This patch correct it.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-09-04 13:06:00 -04:00
Khoronzhuk, Ivan
e6c9428a2f keystone2: use readl/writel functions instead of redefinition
There is no reason to redefine pure readl/writel functions.
So remove this redundancy.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: Vitaly Andrianov <vitalya@ti.com>
2014-09-04 13:06:00 -04:00
Bo Shen
06fa91cd67 USB: gadget: s3c: get rid of debug compile warning
When enable debug option to compile, it will give the following
warning, this patch is used to get rid of it.
--->8---
warning: 'flags' is used uninitialized in this function [-Wuninitialized]
---8<---

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2014-09-02 14:32:15 +02:00
Bo Shen
f9abd4b415 USB: gadget: atmel: get rid of debug compile warning
When enable debug option to compile, it will give the following
warning, this patch is used to get rid of it.
--->8---
warning: 'flags' is used uninitialized in this function [-Wuninitialized]
---8<---

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2014-09-02 14:32:15 +02:00
Stephen Warren
842ef9a98e usb: ci_udc: implement dfu_usb_get_reset
This allows the USB code to determine whether a USB bus reset was issued,
which in turn allows the code to differentiate between a detach (return
to shell prompt) and a board reset/reboot request.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-09-02 14:29:28 +02:00
Lukasz Majewski
f2ec4e34aa udc: dfu: s3c_udc: Provide function to check if USB reset was asserted
New dfu_usb_get_reset() method is necessary to distinct two different
use cases of dfu-util program.
This method checks if the USB bus reset has been really performed after
DFU DETACH.

Without this function the previous DFU behavior is preserved.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2014-09-02 14:29:28 +02:00
Lukasz Majewski
1cc03c5c53 dfu: Provide means to find difference between dfu-util -e and -R
This commit provides distinction between DFU device detach and reset.
The -R behavior is preserved with proper handling of the dfu-util's -e
switch, which detach the DFU device.

By running dfu-util -e; one can force device to finish the execution of
dfu command on target and execute some other scripted commands.

Moreover, some naming has been changed - the dfu_reset() method now is known
as dfu_detach(). New name better reflects the purpose of the code.

It was also necessary to increase the number of usb_gadget_handle_interrupts()
calls since we also must wait for detection of the USB reset event.

Example usage:
1. -e (detach) switch
 dfu-util -a0 -D file1.bin;dfu-util -a3 -D uImage;dfu-util -e

 access to u-boot prompt.

2. -R (reset) switch
 dfu-util -a0 -D file1.bin;dfu-util -R -a3 -D uImage

 target board reset

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2014-09-02 14:29:28 +02:00
Tom Rini
0a64bc20f7 Merge branch 'master' of git://git.denx.de/u-boot-nios 2014-08-31 07:45:55 -04:00
Holger Brunck
292221e183 arm/kirkwood/nand: allow forced disabling for subpage writes
Make it configurable to disable subpage writes like the DaVinci NAND
driver already does.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Scott Wood <scottwood@freescale.com>
2014-08-30 07:46:41 -04:00
Jiandong Zheng
799e125cca arm: bcm281xx: net: Add Ethernet Driver
The Broadcom StarFighter2 Ethernet driver is used in multiple Broadcom
SoC(s) and:
- supports multiple MAC blocks,
- provides support for the Broadcom GMAC.
This driver requires MII and PHYLIB.

Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:39 -04:00
Pavel Machek
7860649716 socfpga: cleanup socfpga_dw_mmc
Cleanups as suggested by wd on mailing list.

Signed-off-by: Pavel Machek <pavel@denx.de>
Acked-by: Chin Liang See <clsee@altera.com>
2014-08-30 07:46:38 -04:00
Thomas Chou
3a55a56662 serial: move nios2-yanu.h into opencores_yanu driver
The nios2-yanu.h contains hardware registers and bits of
opencores yanu. As there is no other user of this header
, it should be moved into the driver.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
CC: Renato Andreola <renato.andreola@imagos.it>
2014-08-30 17:48:43 +08:00
Thomas Chou
8645071006 nios2: divide nios2-io.h into each specific drivers and remove it
The nios2-io.h defines hardware registers and bits of several FPGA
IP cores. It could be divided in to the specific drivers, including
altera timer, altera sysid, altera uart and altera jtag uart. The
altera pio and altera spi drivers use their own hardware definitions.
The removal of nios2-io.h will help modularity and maintenance.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2014-08-30 17:48:43 +08:00
Pavel Machek
51fb455f82 socfpga: fix clock manager register definition
Structure defining clock manager hardware was wrong, leading to
wrong registers being accessed and hang in MMC init.

This fixes structure to match hardware.

Signed-off-by: Pavel Machek <pavel@denx.de>
2014-08-29 15:50:50 -04:00
Tom Rini
5a1095a830 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-08-29 11:06:51 -04:00
Stefan Roese
5a834c1f9e net: cpsw: am335x: Drop constant link checking from rx/tx path's
We noticed on the DXR2 platform (AM335x with a SMSC LAN9303 switch connected
to the CPSW MAC) that the network performance in U-Boot is quite poor. Only
when the transfer is started without a cable connected, and the cable is
plugged after the first timeout "T" occured, an increased in performance
can be seen. Debugging has revealed, that the cpsw driver has constant
link checking builtin into the rx and tx functions. This results in the
bad performance and seems to be unnecessary. The link has already been
checked in the init function, before the transfer is started. This usually
is sufficient.

BTW: I have seen no other network driver in U-Boot so far, that constantly
checks for link in the rx / tx functions.

The performance numbers on the DXR2 board are:

0.56 MiB/s	cpsw_check_link() in rx and tx path
0.87 MiB/s	cpsw_check_link() only in tx path
1.0  MiB/s	cpsw_check_link() only in rx path
2.7  MiB/s	no cpsw_check_link() in rx and tx path

So with this patch the network performance on DXR2 increases from 0.56
to 2.7 MiB/s (nearly 5 times as fast).

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Samuel Egli <samuel.egli@siemens.com>
Tested-by: Heiko Schocher <hs@denx.de>
Cc: Vladimir Koutny <vladimir.koutny@streamunlimited.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Tom Rini <trini@ti.com>
2014-08-28 17:18:49 -04:00
Tom Rini
3e1b36bd58 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-08-28 13:03:25 -04:00
Heiko Schocher
4e67c57125 mtd,ubi,ubifs: sync with linux v3.15
snyc with linux v3.15:

commit 1860e379875dfe7271c649058aeddffe5afd9d0d
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Sun Jun 8 11:19:54 2014 -0700

    Linux 3.15

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
2014-08-25 19:25:56 -04:00
Heiko Schocher
ddf7bcfa6c mtd, ubi, ubifs: update for the sync with linux v3.14
while playing with the new mtd/ubi/ubifs sync, found some
small updates for it:

- add del_mtd_partition() to include/linux/mtd/mtd
- mtd: add a debug_printf
- remove some not used functions

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
2014-08-25 19:25:56 -04:00
Heiko Schocher
ff94bc40af mtd, ubi, ubifs: resync with Linux-3.14
resync ubi subsystem with linux:

commit 455c6fdbd219161bd09b1165f11699d6d73de11c
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Sun Mar 30 20:40:15 2014 -0700

    Linux 3.14

A nice side effect of this, is we introduce UBI Fastmap support
to U-Boot.

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Sergey Lapin <slapin@ossfans.org>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Joerg Krause <jkrause@posteo.de>
2014-08-25 19:25:55 -04:00
Heiko Schocher
0c06db5983 lib, linux: move linux specific defines to linux/compat.h
- move linux specific defines from usb and video code
  into linux/compat.h
- move common linux specific defines from include/ubi_uboot.h
  to linux/compat.h
- add for new mtd/ubi/ubifs sync new needed linux specific
  defines to linux/compat.h

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
[trini: Add spin_lock_irqsave/spin_unlock_irqrestore dummies from
usb/lin_gadet_compat.h]
Signed-off-by: Tom Rini <trini@ti.com>
2014-08-25 19:25:03 -04:00
Tom Rini
7bee1c91a9 Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging 2014-08-25 08:34:39 -04:00
Marek Vasut
951860634f e1000: add i210 support
Add i210 support to the e1000 driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-08-21 12:01:28 -04:00
Marek Vasut
873e8e0198 e1000: Implement dcache support
Implement proper support for cache flushing and invalidation into the
Intel e1000 NIC driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-08-21 12:01:28 -04:00
Masahiro Yamada
d1a4aafd71 powerpc: mpc8xx: remove svm_sc8xx board
This board has been orphaned for a while and old enough.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21 12:01:12 -04:00
Masahiro Yamada
62d636aa2a omap: remove omap5912osk board support
Emails to the board maintainer
"Rishi Bhattacharya <rishi@ti.com>"
have been bouncing.

Tom suggested to remove this board.

Remove also omap1510_udc.c because this is the last board
to enable it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suggested-by: Tom Rini <trini@ti.com>
2014-08-21 12:01:12 -04:00
Masahiro Yamada
368b4d2b49 drivers: net: remove dead drivers
The following configs are not defined at all:

 - CONFIG_INCA_IP_SWITCH
 - CONFIG_PBL2800_ETHER
 - CONFIG_PHY_ICPLUS

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21 12:01:11 -04:00
Tom Rini
67ee22b068 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-08-20 16:07:34 -04:00
Shaohui Xie
9bf499ace8 powerpc/T4240QDS/eth: some fix for XFI
XFI is supported on T4QDS-XFI board, which removed slot3, and four LANEs
of serdes2 are routed to a SFP+ cages, which to house fiber cable or
direct attach cable(copper), the copper cable is used to emulate the
10GBASE-KR scenario.

So, for XFI usage, there are two scenarios, one will use fiber cable,
another will use copper cable. For fiber cable, there is NO PHY, while
for copper cable, we need to use internal PHY which exist in Serdes to
do auto-negotiation and link training, which implemented in kernel.
We use hwconfig to define cable type for XFI, and fixup dtb based on the
cable type.

For copper cable, set below env in hwconfig:

fsl_10gkr_copper:<10g_mac_name>

the <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2. The
four <10g_mac_name>s do not have to be coexist in hwconfig. For XFI ports,
if a given 10G port will use the copper cable for 10GBASE-KR, set the
<10g_mac_name> of the port in hwconfig, otherwise, fiber cable will be
assumed to be used for the port.

For ex. if four XFI ports will both use copper cable, the hwconfig
should contain:

fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2

For fiber cable:

1. give PHY address to a XFI port, otherwise, the XFI ports will not be
available in U-boot, there is no PHY physically for XFI when using fiber
cable, this is just to make U-boot happy and we can use the XFI ports
in U-boot.
2. fixup dtb to use fixed-link in case of fiber cable which has no PHY.
Kernel requests that a MAC must have a PHY or fixed-link.

When using XFI protocol, the MAC 9/10 on FM1 should init as 10G interface.

Change serdes 2 protocol 56 to 55 which has same feature as 56 since 56
is not valid any longer.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-20 10:44:16 -07:00
Vijay Rai
12eeb1359a driver/qe: update status of QE microcode
This Patch updates error print for QE which should be easily understood

Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-20 10:44:16 -07:00
Tim Harvey
5a82e1a21d pci: mx6: fix occasional link failures
According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable
for SS function) must remain deasserted until the reference clock is running
at the appropriate frequency.

Without this patch we find a high link failure rate (>5%) on certain
IMX6 boards at various temperatures.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20 12:37:15 +02:00
Markus Niebel
412921d29e RTC: add support for DS1339 (using DS1307 driver)
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
2014-08-14 14:45:58 +02:00
vijay rai
5be1af0198 driver/qe: update status of QE microcode
This Patch updates error print for QE which should be easily understood

Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
2014-08-14 14:22:09 +02:00
Stephen Warren
d878c9a932 pci: fix overflow in __pci_hose_bus_to_phys w/ large RAM
If a 32-bit system has 2GB of RAM, and the base address of that RAM is
2GB, then start+size will overflow a 32-bit value (to a value of 0).

To avoid such an overflow, convert __pci_hose_bus_to_phys() to calculate
the offset of a bus address into a PCI region, rather than comparing a
bus address against the end of a PCI region.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-14 11:38:47 +02:00
Jeroen Hofstee
e6e9cff2dc video: ipu_disp: squash clang warning
Since rgb2ycbcr_coeff and friends are declared const, but assigned
to a void pointer, clang will warn that the const is implicity casted
away. If the pointer is changed to void const * gcc will warn when it
is implicitly casted to a const int array. Just add a correctly
typed pointer instead to prevent these casts and hence the warnings.

Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-08-11 17:52:21 +02:00
Liu Ying
e66866c542 video: ipu_disp: wait for DP SF end irq when disabling sync BG flows
Instead of waiting for DC triple buffer to be cleared, this patch
changes to wait for a relevant DP sync flow end interrupt to come
when disabling sync BG flows.  In this way, we align the implement
to the freescale internal IPUv3 driver.  After applying this patch,
an uboot hang up issue at the arch_preboot_os() stage, where we
disable a relevant ipu display channel, is not observed any more on
some MX6DL platforms.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2014-08-11 17:31:41 +02:00
Stefano Babic
e82abaeb7f Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
	boards.cfg

Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-08-11 10:21:03 +02:00
Hannes Petermaier
3c5fabd139 video: Add support for TI's AM335x LCD-Controller
- Adds support for a minimal framebuffer driver of TI's AM335x SoC
  to be compatible with Wolfgang Denk's LCD-Framework (CONFIG_LCD,
  common/lcd.c)

Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
2014-08-10 15:34:27 +02:00
Masahiro Yamada
8ac22a60e2 omap: clean-up dead configs
The following configs are not defined at all.

 - CONFIG_OMAP1510
 - CONFIG_OMAP_1510P1
 - CONFIG_OMAP_SX1
 - CONFIG_OMAP3_DMA
 - CONFIG_OMAP3_ZOOM2
 - CONFIG_OMAP_INNOVATOR

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
2014-08-09 11:17:04 -04:00
maxin.john@enea.com
79e86ccb37 vitesse: remove duplicated argument to ||
Remove the duplicated argument to || check

Signed-off-by: Maxin B. John <maxin.john@enea.com>
2014-08-09 11:17:02 -04:00
Nobuhiro Iwamatsu
53022c3113 serial: sh: Add support External Clock mode
R8A7780 and R7A7791 of rmobile supports External Clock mode, and these uses
different from Internal Clock mode registers and calculations to the baud rate
setting. This adds function for External Clock mode.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-08-09 11:17:01 -04:00
Nobuhiro Iwamatsu
1a223c9324 serial: sh: Add support DL and CKS register for R8A7794
R8A7794 has DL and CKS register, and these registers are used in external clock
mode. This adds support these for R8A7794.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-08-09 11:17:01 -04:00
Nobuhiro Iwamatsu
5906fadefa usb: ehci: rmobile: Remove xHCI address
echi-rmobile does not support xHCI. This removes xHCI address
from address table. And this revise a value of CONFIG_USB_MAX_CONTROLLER_COUNT
for lager board and koelsh board.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-08-09 11:17:01 -04:00
Nobuhiro Iwamatsu
ed7ce836cd usb: ehci: rmobile: Add support R8A7794
R8A7794 has same IP of USB controller as R8A7790 and R8A7791.
This addes support for R8A7794.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-08-09 11:17:01 -04:00
Stephen Warren
67ab0a5e9f dfu: fix readback buffer overflow test
The buffer is too small if it's < size to read, not if it's <= the size.
This fixes the 1MB test case on Tegra, which has a 1MB buffer.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:17:01 -04:00
Stephen Warren
6f12ebf6ea dfu: add SF backend
This allows SPI Flash to be programmed using DFU.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:59 -04:00
Stephen Warren
cb7bd2e07e dfu: add free_entity() to struct dfu_entity
This allows the backend to free any resources allocated during the
relevant dfu_fill_entity_*() call. This will soon be used by the
SF backend.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:59 -04:00
Stephen Warren
7ac1b410ac dfu: allow backend to specify a maximum buffer size
CONFIG_SYS_DFU_DATA_BUF_SIZE may be large to allow for FAT/ext layouts
to transfer large files. However, this means that individual write
operations will take a long time. Allow backends to specify a maximum
buffer size, so that each write operation is limited to a smaller data
block. This prevents the DFU protocol from timing out when e.g. writing
to SPI flash. I would guess that NAND might benefit from setting this
value too, but I can't test that.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:58 -04:00
Stephen Warren
dd64827eb6 dfu: defer parsing of device string to IO backend
Devices are not all identified by a single integer. To support
this, defer the parsing of the device string to the IO backed, so that
it can apply the appropriate rules.

SPI devices are specified as controller:chip_select. SPI/SF support will
be added soon.

MMC devices can also be specified as controller[.hwpart][:partition] in
many commands, although we don't support that syntax in DFU.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:58 -04:00
Stephen Warren
3ee9593fce dfu: add write error handling
Fix calls to dfu_write() and dfu_flush() to detect errors in the I/O
itself. This could happen due to problems with the storage medium, or
simply when trying to write a FAT/ext file that is larger than the buffer
dfu_mmc.c maintains for this purpose.

Signal the error by switching the DFU state/status. This will be picked
up by the DFU client when it sends the next DFU request. Note that errors
can't simply be returned from e.g. dnload_request_complete(), since that
function has no way to pass errors back to the DFU client; a call to
dnload_request_complete() simply means that a USB OUT completed.

This error state/status needs to be cleared when the next DFU client
connects. While there is a DFU_CLRSTATUS request, no DFU client seems to
send this. Hence, clear this when selecting the USB alternate setting on
the USB interface.

Finally, dfu.c relies on a call to dfu_flush() to clear up the internal
state of the write transaction. Now that errors in dfu_write() are
detected, dfu_flush() may no longer be called for every transaction.
Separate out the cleanup code into a new function, and call it whenever
dfu_write() fails, as well as from any call to dfu_flush().

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:58 -04:00
Stephen Warren
0e285b503c dfu: fix some issues with reads/uploads
DFU read support appears to rely upon dfu->read_medium() updating the
passed-by-reference len parameter to indicate the remaining size
available for reading.

dfu_read_medium_mmc() never does this, and the implementation of
dfu_read_medium_nand() will only work if called just once; it hard-codes
the value to the total size of the NAND device irrespective of read
offset.

I believe that overloading dfu->read_medium() is confusing. As such,
this patch introduces a new function dfu->get_medium_size() which can
be used to explicitly find out the medium size, and nothing else.
dfu_read() is modified to use this function to set the initial value for
dfu->r_left, rather than attempting to use the side-effects of
dfu->read_medium() for this purpose.

Due to this change, dfu_read() must initially set dfu->b_left to 0, since
no data has been read.

dfu_read_buffer_fill() must also be modified not to adjust dfu->r_left
when simply copying data from dfu->i_buf_start to the upload request
buffer. r_left represents the amount of data left to be read from HW.
That value is not affected by the memcpy(), but only by calls to
dfu->read_medium().

After this change, I can read from either a 4MB or 1.5MB chunk of a 4MB
eMMC boot partion with CONFIG_SYS_DFU_DATA_BUF_SIZE==1MB. Without this
change, attempting to do that would result in DFU read returning no data
at all due to r_left never being set.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:58 -04:00
Albert ARIBAUD
1899fac925 Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master' 2014-08-09 16:48:34 +02:00
Fabio Estevam
676ac24e07 pmic: pmic_pfuze100: Use a shorter name for PMIC name
It is redundant to use 'PFUZE100_PMIC' as the PMIC name because we already
know it is a PMIC.

Call it simply 'PFUZE100' instead.

Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-08 10:29:41 +02:00
Stefano Babic
c23154aab5 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-08-08 10:18:40 +02:00
Andy Fleming
b21f87a3e0 Change Andy Fleming's email address
Messages to afleming@freescale.com now bounce, and should be
directed to my personal address at afleming@gmail.com

Signed-off-by: Andy Fleming <afleming@gmail.com>
2014-08-06 09:12:30 -04:00
Tom Rini
336450f5fc Merge branch 'master' of git://git.denx.de/u-boot-spi 2014-08-06 08:38:19 -04:00
Heiko Schocher
f659b57361 spi, spi_mxc: do not hang in spi_xchg_single
if status register do never set MXC_CSPICTRL_TC, spi_xchg_single
endless loops. Add a timeout here to prevent endless hang.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Dirk Behme <dirk.behme@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Simon Glass
22052c6236 spi: Support half-duplex mode in FDT decode
This parameter should also be supported.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Simon Glass
a4e29db257 exynos: spi: Fix calculation of SPI transaction start time
The SPI transaction delay is supposed to be measured from the end of one
transaction to the start of the next. The code does not work that way, so
fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Simon Glass
2001b9a641 cros_ec: Fix two bugs in the SPI implementation
An incorrect message version is passed to the EC in some cases and the
parameters of one function are switched.

Fix these problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Marek Vasut
a52a178f0b sf: sf_ops: Stop leaking memory
It's usually a common pattern to free() the memory that we allocated.
Implement this here to stop leaking memory.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Bo Shen
da55c66ec9 MMC: atmel_mci: enable high speed mode support
If the MCI IP version >= 0x300, it supports hight speed mode
option, this patch enable it.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-08-01 20:01:33 +03:00