Commit graph

25 commits

Author SHA1 Message Date
Stefan Roese
9adfc9fb9a ppc4xx: Remove compiler warning in cpu/ppc4xx/44x_spd_ddr2.c
Signed-off-by: Stefan Roese <sr@denx.de>
2008-01-15 10:11:02 +01:00
Stefan Roese
5ba576c016 ppc4xx: Remove unused CONFIG_ECC_ERROR_RESET from 44x_spd_ddr2.c
Signed-off-by: Stefan Roese <sr@denx.de>
2008-01-05 09:13:46 +01:00
Stefan Roese
845c6c95db ppc4xx: Update Katmai/44x_spd_ddr2.c code for optimal DDR2 setup
On Katmai the complete auto-calibration somehow doesn't seem to
produce the best results, meaning optimal values for RQFD/RFFD.
This was discovered by GDA using a high bandwidth scope,
analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
so now on Katmai "only" RFFD is auto-calibrated.

This patch also adds RDCC calibration as mentioned on page 7 of
the AMCC PowerPC440SP/SPe DDR2 application note:
"DDR1/DDR2 Initialization Sequence and Dynamic Tuning"

Signed-off-by: Stefan Roese <sr@denx.de>
2008-01-05 09:12:41 +01:00
Stefan Roese
ea2e142843 ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAM
This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files
and to the Sequoia TLB init code. Now the cache can be enabled on 44x
boards by defining CONFIG_4xx_DCACHE in the board config file. This
option will disappear, when more boards use is successfully and no
more known problems exist.

This is tested successfully on Sequoia and Katmai. The only problem that
needs to be fixed is, that USB is not working on Sequoia right now, since
it will need some cache handling code too, similar to the 4xx EMAC driver.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:47 +01:00
Stefan Roese
087dfdb79b ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx
This patch moves some common 4xx macros and the PPC405_SYS_INFO/
PPC440_SYS_INFO structure into the common ppc4xx.h header.

Lot's of other macros are good candidates to be consolidated this way
in the future.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Kim Phillips
79f240f7ec lib_ppc: make board_add_ram_info weak
platforms wishing to display RAM diagnostics in addition to size,
can do so, on one line, in their own board_add_ram_info()
implementation.

this consequently eliminates CONFIG_ADD_RAM_INFO.

Thanks to Stefan for the hint.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-18 21:39:46 +02:00
Stefan Roese
6ed14addf9 ppc4xx: Add new weak functions to support boardspecific DDR2 configuration
The new "weak" functions ddr_wrdtr() and ddr_clktr() are added to better
support non default, boardspecific DDR(2) controller configuration.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-16 09:57:00 +02:00
Wolfgang Denk
bf6a9ca9b2 Merge with /home/hs/Atronic/u-boot 2007-07-09 23:41:45 +02:00
Heiko Schocher
a5d71e290f [PCS440EP] get rid of CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG
Signed-off-by: Heiko Schocher <hs@denx.de>
2007-06-25 19:11:37 +02:00
Wolfgang Denk
1636d1c852 Coding stylke cleanup; rebuild CHANGELOG 2007-06-22 23:59:00 +02:00
Heiko Schocher
566a494f59 [PCS440EP] upgrade the PCS440EP board:
- Show on the Status LEDs, some States of the board.
                - Get the MAC addresses from the EEProm
                - use PREBOOT
                - use the CF on the board.
                - check the U-Boot image in the Flash with a SHA1
                  checksum.
                - use dynamic TLB entries generation for the SDRAM

Signed-off-by: Heiko Schocher <hs@denx.de>
2007-06-22 19:11:54 +02:00
Stefan Roese
dbca208518 [ppc4xx] Extend program_tlb() with virtual & physical addresses
Now program_tlb() allows to program a TLB (or multiple) with
different virtual and physical addresses. With this change, now one
physical region (e.g. SDRAM) can be mapped 2 times, once with caches
diabled and once with caches enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-14 11:14:32 +02:00
Stefan Roese
7187db7349 ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)
Add config option for 180 degree advance clock control as needed
for the AMCC Luan eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01 13:45:00 +02:00
Wolfgang Denk
43f6226db0 Merge with /home/wd/git/u-boot/custodian/u-boot-74xx-7xx 2007-04-18 17:00:09 +02:00
Stefan Roese
cabee756a6 ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)
Additional RAM information is now printed upon powerup, like
DDR2 frequency and CAS latency.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-31 13:15:06 +02:00
Stefan Roese
94f54703c3 ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)
Fix a bug in the auto calibration routine. This driver now runs
more reliable with the tested modules. It's also tested with
167MHz PLB frequency (667MHz DDR2 frequency) on the Katmai.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-31 08:46:08 +02:00
Wolfgang Denk
efa013df33 Merge with /home/git/u-boot 2007-03-08 11:41:19 +01:00
Wolfgang Denk
35ded29fd9 Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx 2007-03-08 11:38:58 +01:00
Stefan Roese
df29449747 ppc4xx: Update 440SP/440SPe DDR SPD setup code to support 440SP
Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-08 10:06:09 +01:00
Wolfgang Denk
ad5bb451ad Restructure POST directory to support of other CPUs, boards, etc. 2007-03-06 18:08:43 +01:00
Wolfgang Denk
647d3c3eed Some code cleanup. 2007-03-04 01:36:05 +01:00
Stefan Roese
c8556d0e0b Merge with /home/stefan/git/u-boot/denx-merge-sr 2007-03-01 21:16:02 +01:00
Stefan Roese
ba58e4c9a9 [PATCH] Update AMCC Katmai 440SPe eval board support
This patch updates the recently added Katmai board support. The biggest
change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2
driver.

Please note, that still some problems are left with some memory
configurations. See the driver for more details.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-01 21:11:36 +01:00
Wolfgang Denk
743571145b Minor code cleanup. 2007-02-27 14:26:04 +01:00
Stefan Roese
4037ed3b63 [PATCH] PPC4xx: Add 440SP(e) DDR2 SPD DIMM support
This patch adds support for the DDR2 controller used on the
440SP and 440SPe. It is tested on the Katmai (440SPe) eval
board and works fine with the following DIMM modules:

- Corsair CM2X512-5400C4 (512MByte per DIMM)
- Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM)
- Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM)

This patch also adds the nice functionality to dynamically
create the TLB entries for the SDRAM (tlb.c). So we should
never run into such problems with wrong (too short) TLB
initialization again on these platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 10:43:34 +01:00