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59260 commits

Author SHA1 Message Date
Adam Ford
25e4ff45b1 ARM: omap3_logic: Enable OMAP EHCI support for SOM-LV Boards
The SOM-LV boards support the OMAP EHCI driver using port 2.
With the driver updated to support device tree, this patch sets
the corresponding pin muxing for the tranceiver as well as the
reset pin.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-27 13:36:52 -04:00
Tom Rini
df9a7a195b u-boot-imx-20190719
- CCF for i.MX6
 - nandbcb command to write SPL into NAND
 - Switch to DM (i.MX28)
 - Boards: Toradex, engicam, DH
 - Fixes for i.MX8
 - Fixes for i.MX7ULP
 
 Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/561147504
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Merge tag 'u-boot-imx-20190719' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20190719

- CCF for i.MX6
- nandbcb command to write SPL into NAND
- Switch to DM (i.MX28)
- Boards: Toradex, engicam, DH
- Fixes for i.MX8
- Fixes for i.MX7ULP

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/561147504
2019-07-27 09:35:05 -04:00
Tom Rini
222701e157 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spi
- fix for fsl_qspi read timeout (Thomas)
- spi-mem read data size fix (Ye Li)
- SiFive SPI driver, mmc_spi flags (Bhargav, Anup)
- Micron spi-nor parts (Ashish)
- MT7629 spi-mem driver(Weijie)
2019-07-27 09:34:07 -04:00
Adam Ford
67a4df9daf ARM: am3517-evm: Remove non-DM legacy code
With both SPL and U-Boot now supporting DM, we can start removing
legacy code.  This patch removes the legacy MMC initalization and
legacy I2C initialization since both are now available via DM and
device tree.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-26 22:24:13 -04:00
Adam Ford
9eed1ca15b ARM: am3517-evm: Migrate to SPL_OF_CONTROL
Like the other Logic PD OMAP35/DM37 boards, this board has device
tree enabled for U-Boot.  This patch converts the board to enable
SPL_OF_CONTROL and further shrinks the device tree in SPL to limit
it to UART3 (console), MMC1, i2c1, and GPIO4 (for mmc1 CD and WP).

There appears to be a bug in minicom so users may need to
switch the minicom terminal emulation to ANSI from VT102 due
to the junk that gets pushed out of the UART on startup.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-26 22:24:12 -04:00
Adam Ford
e054be5bab ARM: da850-evm: Remove repeated pinmuxing calls
arch_cpu_init() initializes the pinmuxing which is called fairly
early in the start sequences, so the board_init function doesn't
need to do it again.  This patch removes the call from board_init.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-26 22:24:12 -04:00
Adam Ford
938359c570 ARM: da850-evm: Remove duplicate UART initialization
The Low Level init functions start the UART, so it doesn't need
to happen during board_init.  This patch removes it from
board_init.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-26 22:24:12 -04:00
Adam Ford
9de4695f75 ARM: am3517-evm: Remove manual ethernet reset code
The reset line going to the ethernet controller is controlled
by a global reset controlling multiple peripherals.  There
is no need to manually invoke the reset.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-26 22:24:11 -04:00
Adam Ford
2448e42d73 ARM: am3517-evm: Enable DM_PMIC and DM_REGULATOR functions
The PBIAS regulator is available on OMAP3's, and it's shared on
the AM35, so this patch enables that in U-Boot along with GPIO
based regulators.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-26 22:24:11 -04:00
Faiz Abbas
637fc2c991 ARM: dts: dra76x: Update MMC2_HS200_MANUAL1 iodelay values
Update the MMC2_HS200_MANUAL1 iodelay values to match with the latest
dra76x data manual[1].

Also this particular pinctrl-array is using spaces instead of tabs for
spacing between the values and the comments. Fix this as well.

[1] http://www.ti.com/lit/ds/symlink/dra76p.pdf

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-07-26 22:24:11 -04:00
Faiz Abbas
6b66d2ee47 ARM: dts: am57xx: Disable voltage switching for SD card
If UHS speed modes are enabled, a compatible SD card switches down to 1.8V
during enumeration. If after this a software reboot/crash takes place and
on-chip ROM tries to enumerate the SD card, the difference in
IO voltages (host @ 3.3V and card @ 1.8V) may end up damaging the card.

The fix for this is to have support for power cycling the card in
hardware (with a PORz/soft-reset line causing a power cycle of the card).
Because the beaglebone X15 (rev A,B and C), am57xx-evms and am57xx-idks don't
have this capability, disable voltage switching for these boards.

The major effect of this is that the maximum supported speed mode is now
high speed(50 MHz) down from SDR104(200 MHz).

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-07-26 22:24:11 -04:00
Faiz Abbas
684af0be94 ARM: dts: am574x-idk: Add pinmuxes for mmc1 and mmc2
Sync with kernel dts by adding pinmuxes for mmc1 and mmc2. This fixes an
issue where mmc2 (eMMC) was coming up in HS52 mode instead of the
highest DDR52 mode.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-07-26 22:24:10 -04:00
Faiz Abbas
461918d7df ARM: dts: dra7-mmc-iodelay: Add a new pinctrl group for clk line without pullup
During a short period when the bus voltage is switched from 3.3v to 1.8v,
(to enumerate UHS mode), the mmc module is disabled and the mmc IO lines
are kept in a state according to the programmed pad mux pull type.

According to 4.2.4.2 Timing to Switch Signal Voltage in "SD Specifications
Part 1 Physical Layer Specification Version 5.00 February 22, 2016", the
host should hold CLK low for at least 5ms.

In order to keep the card line low during voltage switch, the pad mux of
mmc1_clk line should be configured to pull down.

Add a new pinctrl group for clock line without pullup to be used in boards
where mmc1_clk line is not connected to an external pullup.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-07-26 22:24:10 -04:00
Lokesh Vutla
697a689d76 configs: j721e_evm_a72: Add initial support
Add initial defconfig support for J721e that runs on A72.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Add MAINTAINERS entry]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-07-26 22:24:00 -04:00
Lokesh Vutla
f9fe3412c6 configs: j721e_evm_r5: Add initial support
Add initial defconfig support for J721e that runs on R5.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Add MAINTAINERS file]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-07-26 22:22:14 -04:00
Lokesh Vutla
aebb2a499e arm: dts: k3-j721e: Add r5 specific dt support
Add initial support for dt that runs on r5.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2019-07-26 21:49:29 -04:00
Lokesh Vutla
9a5e553cb4 arm: dts: k3-j721e: Add initial support for common processor board
Common Processor board is the baseboard that has most of the actual connectors,
power supply etc. A SOM (System on Module) is plugged on to the common
processor board and this contains the SoC, PMIC, DDR and basic highspeed
components necessary for functionality. Add initial dt support for this
common processor board.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:29 -04:00
Lokesh Vutla
eeb2e8b6eb arm: dts: ti: Add Support for J721E SoC
Add initial SoC definition for J721E SoC.
Kernel dts posted here:
https://lore.kernel.org/lkml/20190522161921.20750-1-nm@ti.com/

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:28 -04:00
Lokesh Vutla
382f1dda97 dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721E
Add pinctrl macros for J721E SoC. These macro definitions are
similar to that of AM6, but adding new definitions to avoid
any naming confusions in the soc dts files.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2019-07-26 21:49:28 -04:00
Faiz Abbas
794453f91d mmc: am654_sdhci: Separate J721E compatible into 8bit and 4bit versions
The j721e 4 bit instances don't have a hard DLL and therefore don't need
any DLL related configurations. Split the compatibles into an 8 bit and a
4 bit one. Add a private flags field which can be used to check if the
DLL is present and don't register the set_ios_post callback for the 4 bit
compatible instances.

Also update the compatibles in k3-j721e-main.dtsi to avoid breaking boot
with the new compatibles.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:28 -04:00
Suman Anna
d146af5b0e board: ti: j721e: Enable fixing up msmc sram node
Create a ft_board_setup() api that gets called as part of
DT fixup before jumping to kernel. In this ft_board_setup()
call fdt_fixup_msmc_ram that update msmc sram node.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:28 -04:00
Lokesh Vutla
f81850322a board: ti: j721e: Add board support for j721e evm
Add board specific initialization for j721e evm

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2019-07-26 21:49:27 -04:00
Suman Anna
5bc22e3277 armv8: K3: j721e: Add custom MMU support
The A72 U-Boot code loads and boots a number of remote processors
including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various
Main R5FSS Cores. Change the memory attributes for the DDR regions used
by the remote processors so that the cores can see and execute the
proper code.

A separate table based on the current AM65x table is added for J721E SoCs,
since the number of remote processors and their DDR usage will be different
between the two SoC families.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:27 -04:00
Andreas Dannenberg
9d1303b38b armv7R: K3: j721e: Load SYSFW binary and config from boot media
Use the System Firmware (SYSFW) loader framework to load and start
the SYSFW as part of the J721E early initialization sequence. While
at it also initialize the MCU_UART0 pinmux as it is used by SYSFW
to print diagnostic messages.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:27 -04:00
Lokesh Vutla
9c0ff866b3 armv7R: K3: j721e: Shut down R5 core after ATF startup on A72
Populate the release_resources_for_core_shutdown() api with
shutting down r5 cores so that it will by called just after
jumping to ATF.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:26 -04:00
Andreas Dannenberg
f94a07c8a1 armv7R: K3: j721e: Store boot index from ROM
Obtain the boot index as left behind by the device boot ROM and store
it in scratch pad SRAM for later use before it may get overwritten.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2019-07-26 21:49:26 -04:00
Andreas Dannenberg
b73fcbced9 armv7R: K3: j721e: Unlock all applicable control MMR registers
To access various control MMR functionality the registers need to
be unlocked. Do that for all control MMR regions in the MCU and MAIN
domains. We may want to go back later and limit the unlocking that's
being done.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2019-07-26 21:49:26 -04:00
Lokesh Vutla
0a704924f3 armv7R: K3: j721e: Add support for boot device detection
J721E allows for booting from primary or backup boot media.
Both media can be chosen individually based on switch settings.
ROM looks for a valid image in primary boot media, if not found
then looks in backup boot media. In order to pass this boot media
information to boot loader, ROM stores a value at a particular
address. Add support for reading this information and determining
the boot media correctly.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-07-26 21:49:26 -04:00
Lokesh Vutla
c2562d7c9e arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.

Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
  capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
  C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
  and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
  PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
  up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
  addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
  capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
  16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
  I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
  management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
  capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
  Management (DMSC)

See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1

Add base support for J721E SoC

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-07-26 21:49:25 -04:00
Lokesh Vutla
54e4311fa1 remoteproc: k3_rproc: Rename to ti_k3_arm64_rproc
k3_rproc driver is specifically meant for controlling an arm64
core using TISCI protocol. So rename the driver, Kconfig symbol,
compatible and functions accordingly.

While at it drop this remoteproc selection for a53 defconfig.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:25 -04:00
Lokesh Vutla
44de37a00e remoteproc: k3_rproc: Update the driver to use ti_sci_proc helpers
Update the k3_rproc driver to use the generic ti_sci_proc helper
apis which simplifies the driver a bit.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:25 -04:00
Lokesh Vutla
4fa23ebe73 remoteproc: tisci: add TI-SCI processor control helper functions
Texas Instruments' K3 generation SoCs has specific modules/register
spaces used for configuring the various aspects of a remote processor.
These include power, reset, boot vector and other configuration features
specific to each compute processor present on the SoC. These registers
are managed by the System Controller such as DMSC on K3 AM65x SoCs.

The Texas Instrument's System Control Interface (TI-SCI) Message Protocol
is used to communicate to the System Controller from various compute
processors to invoke specific services provided by the firmware running
on the System Controller.

Add a common processor control interface header file that can be used by
multiple remoteproc drivers. The helper functions within this header file
abstract the various TI SCI protocol ops for the remoteproc drivers, and
allow them to request the System Controller to be able to program and
manage various remote processors on the SoC. The common macros required
by the R5 remoteproc driver were also added. The remoteproc drivers are
expected to manage the life-cycle of their ti_sci_proc_dev local
structures.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
2019-07-26 21:49:24 -04:00
Lokesh Vutla
96f41f9cde cmd: remoteproc: Allow list command to print the probed devices
'rproc list' is currently allowed only after probing all the
available remoteproc devices. Given that 'rproc init' is updated
to probe and initialize devices individually, allow the 'rproc list'
command to print all probed devices at any point.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:24 -04:00
Lokesh Vutla
75a11cc771 cmd: remoteproc: Add support for initializing devices individually
'rproc init' does the probe and initialization of all the available
remoteproc devices in the system. This doesn't allow the flexibility
to initialize the remote cores needed as per use case. In order
to provide flexibility, update 'rproc init' command to accept one
more parameter with rproc id which when passed initializes only
that specific core. If no id is passed, command will initializes
all the cores which is compatible with the existing behaviour.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:24 -04:00
Lokesh Vutla
355be915ed arm: dts: k3-am654: Update power-domains property for each node
Update the power-domain-cells to 2 and add the permissions
to each node. Mark the following nodes accessed by r5 as shared:
- DDR node
- main uart 0

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:23 -04:00
Lokesh Vutla
cd041c8041 power: domain: ti_sci_power_domains: Add support for exclusive and shared access
TISCI protocol supports for enabling the device either with exclusive
permissions for the requesting host or with sharing across the hosts.
There are certain devices which are exclusive to Linux context and
there are certain devices that are shared across different host contexts.
So add support for getting this information from DT by increasing
the power-domain cells to 2.

For keeping the DT backward compatibility intact, defaulting the
device permissions to set the exclusive flag set. In this case the
power-domain-cells is 1.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:23 -04:00
Lokesh Vutla
c163af6cb8 dt-bindings: ti_sci_pm_domains: Add support for exclusive and shared access
TISCI protocol supports for enabling the device either with exclusive
permissions for the requesting host or with sharing across the hosts.
There are certain devices which are exclusive to Linux context and
there are certain devices that are shared across different host contexts.
So add support for getting this information from DT by increasing
the power-domain cells to 2.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:23 -04:00
Lokesh Vutla
fd4e7be5f3 power-domain: Add private data to power domain
Certain drivers want to attach private data corresponding to each
power domain. This data might be specific be to the drvier. So add
a priv entry into the power_domain structure.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:22 -04:00
Lokesh Vutla
c0669d28ee armv7R: k3: Release all the exclusive devices
Release all the exclusive devices held by SPL.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:22 -04:00
Andreas Dannenberg
f9380a730d armv7R: K3: am654: Shut down R5 core after ATF startup on A53
Rather than simply parking the R5 core in WFE after starting up ATF
on A53 instead use SYSFW API to properly shut down the R5 CPU cores
as well as associated timer resources that were pre-allocated. This
allows software further downstream to properly and gracefully bring
the R5 cores back online if desired.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:22 -04:00
Lokesh Vutla
9566b777ae firmware: ti_sci: Add a command for releasing all exclusive devices
Any host while requesting for a device can request for its exclusive
access. If an exclusive permission is obtained then it is the host's
responsibility to release the device before the software entity on
the host completes its execution. Else any other host's request for
the device will be nacked. So add a command that releases all the
exclusive devices that is acquired by the current host. This should
be used with utmost care and can be called only at the end of the
execution.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:22 -04:00
Andreas Dannenberg
410adcc9e2 firmware: ti_sci: Add processor shutdown API method
Add and expose a new processor shutdown API that wraps the two TISCI
messages involved in initiating a core shutdown. The API will first
queue a message to have the DMSC wait for a certain processor boot
status to happen followed by a message to trigger the actual shutdown-
with both messages being sent without waiting or requesting for a
response. Note that the processor shutdown API call will need to be
followed up by user software placing the respective core into either
WFE or WFI mode.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2019-07-26 21:49:21 -04:00
Lokesh Vutla
ae0b8a2bc8 firmware: ti_sci: Allow for device shared and exclusive requests
Sysfw provides an option for requesting exclusive access for a
device using the flags MSG_FLAG_DEVICE_EXCLUSIVE. If this flag is
not used, the device is meant to be shared across hosts. Once a device
is requested from a host with this flag set, any request to this
device from a different host will be nacked by sysfw. Current tisci
driver enables this flag for every device requests. But this may not
be true for all the devices. So provide a separate commands in driver
for exclusive and shared device requests.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:21 -04:00
Kever Yang
bfcf15aad2 rockchip: declear boot_devices in bootrom.h
boot_devices may defined in soc file, and used in board file,
we need to delear it in header file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-26 17:30:26 +08:00
Kever Yang
cd59501f21 rockchip: intruduce common BROM_BOOTSOURCE_ID_ADDR
The boot source from BootRom is store at a fix offset of IRAM,
update to use the common macro instead of rk3399 specific one.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-26 17:30:26 +08:00
Kever Yang
5f24680867 rockchip: add CONFIG_IRAM_BASE for all SoCs
Rockchip SoCs have internal sram for bootrom data area and for
sdram init program space. Introduce the base address in case
we need to use it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-26 17:30:26 +08:00
Kever Yang
7a9dd60749 rockchip: remove redundant CONFIG_SYS_NS16550_MEM32
The CONFIG_SYS_NS16550_MEM32 already defined in
rockchip_common.h, no need to define again in soc
level header.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-26 17:30:26 +08:00
Shyam Saini
70c2f590c8 include: configs: Increase CONFIG_SYS_BOOTM_LEN to 16MB
The default value of CONFIG_SYS_BOOTM_LEN is 0x800000 i.e, 8MB which
causes board reset because of larger uImage size.

This was tested on rk3288 Amarula Vyasa and rk3288 Asus Tinker
boards.

Error log snippet:
   Booting using the fdt blob at 0x1f00000
   Loading Kernel Image ... Image too large: increase CONFIG_SYS_BOOTM_LEN
Must RESET board to recover
resetting ...

Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-26 16:11:03 +08:00
Tom Rini
bfe28bc70f Merge https://gitlab.denx.de/u-boot/custodians/u-boot-net
- DaVinci emac DM work
- NXP driver work
- macb updates for RISC-V
2019-07-25 15:02:36 -04:00
Emmanuel Vadot
d53e522255 net: sun8i_emac: Test the correct phy
H3/H5 can either use the internal phy or an external one.
Before getting clock and resets for the internal phy,
test that we are using it because otherwise it break emac
when using an external phy.

Tested-on: OrangePi PC2 (H5)
Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support)
Signed-off-by: Emmanuel Vadot <manu@freebsd.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25 13:36:13 -05:00