Commit graph

17728 commits

Author SHA1 Message Date
Nishanth Menon
fdb7d45c76 arm: mach-k3: arm64-mmu: Refactor to be independent of board
Refactor J721E J7200 definition to make this independent of board
macros.

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 12:04:14 -05:00
Nishanth Menon
3c11584c21 board: ti: j721e: Select SOC_K3_J721E_J7200 for J7200evm
Enable SOC_K3_J721E_J7200 when board is J7200 EVM - this allows us to
differentiate J7200 platform cleanly in board independent codebase.

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 12:04:14 -05:00
Nishanth Menon
97bf082c9f arm: mach-k3: Kconfig: Introduce a symbol to indicate J7200
J7200 shares quite a few characteristics with J721E. However a few sets
are different. Introduce a Kconfig to differentiate the two to allow for
new boards to be introduced in a seamless manner.

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-22 12:04:14 -05:00
Nishanth Menon
110b07c8bc arm: mach-k3: Move TI dummy keys out of board folder
This file is used to emulate customer keys on TI development board
ecosystems, move it out of board/ directory and into mach-k3. And
change the relative paths to absolute paths in the binman paths.

While at it, drop the reference in verdin-binman file which is
redundant.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Acked-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-11-22 12:04:14 -05:00
Nishanth Menon
f1c8e9c442 arm: mach-k3: Move K3 degenerate keys out of board folder
This file is common for all of K3, move it out of board/ directory and
into mach-k3. And change the relative paths to absolute paths in the
binman paths.

While at it, drop the reference in verdin-binman file which is
redundant.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Andrew Davis <afd@ti.com>
2023-11-22 12:04:14 -05:00
Andrew Davis
140d427cc9 arm: mach-k3: Move sysfw-loader into R5 directory
SYSFW is only ever loaded by the R5 core, move the code into that
directory. While here also move the related Kconfig symbols.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-11-22 12:04:14 -05:00
Andrew Davis
cf2a075b8c arm: mach-k3: Remove incorrect checks for SPL build
The kconfig option SPL means this build supports SPL but not that
this build is SPL, nor that this build is the SPL running on R5.
For options that are for R5 SPL use CPU_V7R.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-11-22 12:04:14 -05:00
Andrew Davis
ffda1089dd arm: mach-k3: Move R5 specific code into new r5/ directory
This makes it clear these are only to be used by the R5 builds of SPL.
And this will be used to later more cleanly split the two builds.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-11-22 12:04:13 -05:00
Andrew Davis
5710d0a853 arm: mach-k3: j721s2: Move board selection to mach-k3
Currently each set of board targets from a vendor is selected inside
the board directory for that vendor. This has the problem of multiple
targets, one from each vendor, being selectable at the same time.
For instance you can select both TARGET_AM654_A53_EVM and
TARGET_IOT2050_A53 in the same build.

To fix this we need to move the target board choice to a common location
for each parent SoC selection. Do this in arch/arm/mach-k3.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-11-22 09:37:23 -05:00
Andrew Davis
e4439cadb6 arm: mach-k3: am62ax: Move board selection to mach-k3
Currently each set of board targets from a vendor is selected inside
the board directory for that vendor. This has the problem of multiple
targets, one from each vendor, being selectable at the same time.
For instance you can select both TARGET_AM654_A53_EVM and
TARGET_IOT2050_A53 in the same build.

To fix this we need to move the target board choice to a common location
for each parent SoC selection. Do this in arch/arm/mach-k3.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-11-22 09:37:23 -05:00
Andrew Davis
f3bfec72d1 arm: mach-k3: am62x: Move board selection to mach-k3
Currently each set of board targets from a vendor is selected inside
the board directory for that vendor. This has the problem of multiple
targets, one from each vendor, being selectable at the same time.
For instance you can select both TARGET_AM654_A53_EVM and
TARGET_IOT2050_A53 in the same build.

To fix this we need to move the target board choice to a common location
for each parent SoC selection. Do this in arch/arm/mach-k3.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-11-22 09:37:23 -05:00
Andrew Davis
ed51c911a6 arm: mach-k3: am64x: Move board selection to mach-k3
Currently each set of board targets from a vendor is selected inside
the board directory for that vendor. This has the problem of multiple
targets, one from each vendor, being selectable at the same time.
For instance you can select both TARGET_AM654_A53_EVM and
TARGET_IOT2050_A53 in the same build.

To fix this we need to move the target board choice to a common location
for each parent SoC selection. Do this in arch/arm/mach-k3.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-11-22 09:37:23 -05:00
Andrew Davis
c3a9f9b2b9 arm: mach-k3: am65x: Move board selection to mach-k3
Currently each set of board targets from a vendor is selected inside
the board directory for that vendor. This has the problem of multiple
targets, one from each vendor, being selectable at the same time.
For instance you can select both TARGET_AM654_A53_EVM and
TARGET_IOT2050_A53 in the same build.

To fix this we need to move the target board choice to a common location
for each parent SoC selection. Do this in arch/arm/mach-k3.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-11-22 09:37:23 -05:00
Andrew Davis
1736b2f0fd arm: mach-k3: j721e: Move board selection to mach-k3
Currently each set of board targets from a vendor is selected inside
the board directory for that vendor. This has the problem of multiple
targets, one from each vendor, being selectable at the same time.
For instance you can select both TARGET_AM654_A53_EVM and
TARGET_IOT2050_A53 in the same build.

To fix this we need to move the target board choice to a common location
for each parent SoC selection. Do this in arch/arm/mach-k3.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-11-22 09:37:23 -05:00
Tom Rini
dca7a8958f Prepare v2024.01-rc3
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Merge tag 'v2024.01-rc3' into next

Prepare v2024.01-rc3
2023-11-20 09:19:50 -05:00
Chris Packham
0585c28fda Revert "arm64: Use FEAT_HAFDBS to track dirty pages when available"
This reverts commit 6cdf6b7a34. This is
part of a series trying to make use of the arm64 hardware features for
tracking dirty pages. Unfortunately this series causes problems for the
AC5/AC5X SoCs. Having exhausted other options the consensus seems to be
reverting this series is the best course of action.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2023-11-17 11:58:26 -05:00
Chris Packham
eed8294b75 Revert "arm64: Use level-2 for largest block mappings when FEAT_HAFDBS is present"
This reverts commit 836b8d4b20. This is
part of a series trying to make use of the arm64 hardware features for
tracking dirty pages. Unfortunately this series causes problems for the
AC5/AC5X SoCs. Having exhausted other options the consensus seems to be
reverting this series is the best course of action.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2023-11-17 11:58:26 -05:00
Chris Packham
ee23d7466c Revert "armv8: enable HAFDBS for other ELx when FEAT_HAFDBS is present"
This reverts commit c1da6fdb5c. This is
part of a series trying to make use of the arm64 hardware features for
tracking dirty pages. Unfortunately this series causes problems for the
AC5/AC5X SoCs. Having exhausted other options the consensus seems to be
reverting this series is the best course of action.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2023-11-17 11:58:26 -05:00
Marcel Ziswiler
ac33a7976a imx: spl_imx_romapi: fix emmc fast boot mode case
This fixes a regression in the eMMC fast boot mode case where the buffer
was missing 464 bytes.

The code figures out how many bytes must at least be fetched to honor
the current read, rounds that up to the ss->pagesize [which is a no-op
in the USB download case because that has ->pagesize==1], fetches that
many bytes, but then recorded the original upper bound as the new end of
the valid data. However, this did not take into account the rounding up
to the ss->pagesize. Fix this by recording the actual bytes downloaded.

Fixes: 4b4472438f ("imx: spl_imx_romapi: avoid tricky use of spl_load_simple_fit() to get full FIT size")
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-11-17 11:58:26 -05:00
Marcel Ziswiler
e2dcadbba4 imx: spl_imx_romapi: fix comment about stream(usb) download failure
Fix comment about Stream(USB) download failure.

Fixes: 1cbebc7862 ("imx: add rom api support")
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-11-17 11:58:26 -05:00
Sean Anderson
5271e359a4 spl: Only support bl_len when we have to
Aligning addresses and sizes causes overhead which is unnecessary when we
are not loading from block devices. Remove bl_len when it is not needed.

For example, on iot2050 we save 144 bytes with this patch (once the rest of
this series is applied):

add/remove: 0/0 grow/shrink: 0/3 up/down: 0/-144 (-144)
Function                                     old     new   delta
spl_load_simple_fit                          920     904     -16
load_simple_fit                              496     444     -52
spl_spi_load_image                           384     308     -76
Total: Before=87431, After=87287, chg -0.16%

We use panic() instead of BUILD_BUG_ON in spl_set_bl_len because we still
need to be able to compile it for things like mmc_load_image_raw_sector,
even if that function will not be used.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
afdd2d98c2 spl: Remove filename from spl_load_info
For filesystems, filename serves the same purpose as priv. However,
spl_load_fit_image also uses it to determine whether to use a DMA-aligned
buffer. This is beneficial for FAT, which uses a bounce-buffer if the
destination is not DMA-aligned. However, this is unnecessary now that
filesystems set bl_len to ARCH_DMA_MINALIGN instead. With this done, we can
remove filename entirely.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
73c40fcb73 spl: Refactor spl_load_info->read to use units of bytes
Simplify things a bit for callers of spl_load_info->read by refactoring it
to use units of bytes instead of bl_len. This generally simplifies the
logic, as MMC is the only loader which actually works in sectors. It will
also allow further refactoring to remove the special-case handling of
filename.  spl_load_legacy_img already works in units of bytes (oops) so it
doesn't need to be changed.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:14 -05:00
Sean Anderson
feaeb8fa6f spl: Remove NULL assignments in spl_load_info
Remove NULL assignments to fields in spl_load_info when .load doesn't
reference these fields. This can result in more efficient code. filename
must stay even if it is unused, since load_simple_fit uses it.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-11-16 13:49:13 -05:00
Sean Anderson
a9a7379973 arm: Enable SYS_THUMB_BUILD on AT91
Several AT91 boards are quite close to their SPL size limit. For example,
sama5d27_wlsom1_ek_mmc is just 173 bytes short of its limit and doesn't
even fit with older GCCs.

All AT91 processors should have thumb support. Enable SYS_THUMB_BUILD. This
shrinks SPL by around 30%.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-11-16 13:48:58 -05:00
Tom Rini
be0724601a Introduce STM32MP2 SoCs family support
Add STM32MP257F-EV1 board
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Merge tag 'u-boot-stm32-20231113' of https://source.denx.de/u-boot/custodians/u-boot-stm into next

Introduce STM32MP2 SoCs family support
Add STM32MP257F-EV1 board

[trini: Adjust some includes]
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-11-13 13:35:57 -05:00
Patrice Chotard
01a701994b stm32mp2: initial support
Add initial support for STM32MP2 SoCs family.

SoCs information are available here :
https://www.st.com/content/st_com/en/campaigns/microprocessor-stm32mp2.html

Migrate all MP1 related code into stm32mp1/ directory
Create stm32mp2 directory dedicated for STM32MP2 SoCs.

Common code to MP1, MP13 and MP25 is kept into
arch/arm/mach-stm32/mach-stm32mp directory :
  - boot_params.c
  - bsec
  - cmd_stm32key
  - cmd_stm32prog
  - dram_init.c
  - syscon.c
  - ecdsa_romapi.c

For STM32MP2, it also :
  - adds memory region description needed for ARMv8 MMU.
  - enables early data cache before relocation.
    During the transition before/after relocation, the MMU, initially setup
    at the beginning of DDR, must be setup again at a correct address after
    relocation. This is done in enables_caches() by disabling cache, force
    arch.tlb_fillptr to NULL which will force the MMU to be setup again but
    with a new value for gd->arch.tlb_addr. gd->arch.tlb_addr has been
    updated after relocation in arm_reserve_mmu().

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-11-13 10:55:38 +01:00
Patrice Chotard
970d1673b0 ARM: dts: stm32: Add STM32MP257F Evaluation board support
Add STM32MP257F Evaluation board support. It embeds a STM32MP257FAI SoC,
with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2 typeC,
SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...

Sync device tree with kernel v6.6-rc1.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-11-13 10:55:38 +01:00
Patrice Chotard
3e0b12af8a stm32mp: bsec: Fix AARCH64 compilation warnings
When building with AARCH64 defconfig, we got warnings, fix them.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-11-13 10:55:38 +01:00
Patrice Chotard
75ba0fd570 stm32mp: dram_init: Limit DDR usage under 4GB boundary for STM32MP
Limit DDR usage under 4GB boundary on STM32MP regardless of
memory size declared in device tree.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-11-13 10:55:38 +01:00
Patrick Delaunay
ee15c72da2 stm32mp: dram_init: Fix AARCH64 compilation warnings
When building with AARCH64 defconfig, we got warnings for debug
message
- format '%x' expects argument of type 'unsigned int',
   but argument 3 has type 'size_t' {aka 'long unsigned int'}).
- format '%lx' expects argument of type 'long unsigned int',
  but argument 2 has type 'phys_addr_t' {aka 'long long unsigned
  int'}

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-11-13 10:55:38 +01:00
Patrice Chotard
dba8d92a3d stm32mp: dram_init: Get RAM size from DT if no RAM driver found
In case there is no RAM driver retrieve RAM size from DT as fallback.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-11-13 10:55:38 +01:00
Patrice Chotard
2f9886c668 arm: caches: Make DCACHE_DEFAULT_OPTION accessible for ARM64 arch
This fixes the following compilation error in ARM64:
arch/arm/mach-stm32mp/dram_init.c: In function ‘board_get_usable_ram_top’:
arch/arm/mach-stm32mp/dram_init.c:59:45: error: ‘DCACHE_DEFAULT_OPTION’ undeclared (first use in this function)
   59 |  mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION);
      |                                             ^~~~~~~~~~~~~~~~~~~~~

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-11-13 10:55:38 +01:00
Mikhail Kalashnikov
4b02f0120a sunxi: H616: add LPDDR4 DRAM support
The H616 SoC family has support for several types of DRAM: DDR3,
LPDDR3, DDR4 and LPDDR4.
At the moment, the driver only supports DDR3 and LPDDR3 memory.
Let's extend the driver to support the LPDDR4 memory. This type
of memory widely used in device with T507(-H) SoC and new orangepi
zero3 with H618.
The compatibility with T507 is not yet complete, because there
is difference in the phy_init array.
The LPDDR4-2133 timings correspond to DRAM Rayson RS1G32LO4D2BDS-53BT
found on the NOR SPI from the Orangepi Zero 3 4GB.

Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Tested-by: Piotr Oniszczuk <piotr.oniszczuk@gmail.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
2023-11-12 18:04:32 +00:00
Andre Przywara
b71129ca3b sunxi: H616: DRAM: refactor mctl_phy_configure_odt()
The original H616 DDR3 ODT configuration code wrote board specific values
into a sequence of paired registers.
For LPDDR3 support we needed to special-case one group of registers,
because for that DRAM type we need to write 0 into the lower register of
each pair. That already made the code less readable.

LPDDR4 support will make things even messier, so let's refactor that
code now: We allow to write different values into the lower and upper
half of each pair. The masking is moved into a macro, and use in each
write statement.

The effect is not as obvious yet, as we don't need the full flexibility at
the moment, but the motivation will become clearer with LPDDR4 support.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Mikhail Kalashnikov <iuncuim@gmail.com>
2023-11-12 18:03:37 +00:00
Andre Przywara
d17d051c54 power: pmic: sunxi: add AXP313 SPL driver
On boards using the AXP313 PMIC, the DRAM rail is often not setup
correctly at reset time, so we have to program the PMIC very early in
the SPL, before running the DRAM initialisation.

Add a simple AXP313 PMIC driver that knows about DCDC2(CPU) and
DCDC3(DRAM), so that we can bump up the voltage before the DRAM init.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-11-12 16:47:16 +00:00
Ludwig Kormann
1f6c98c2d3 arm: dts: icnova-a20-adb4006: Add board support
Add board support for ICnova A20 SomPi compute module on
ICnova ADB4006 development board.

Specification:
SoM
- Processor: Allwinner A20 Cortex-A7 Dual Core at 1GHz
- 512MB DDR3 RAM
- Fast Ethernet (Phy: Realtek RTL8201CP)
ADB4006
- I2C
- 2x USB 2.0
- 1x Fast Ethernet port
- 1x SATA
- 2x buttons (PWRON, Boot)
- 2x LEDS
- serial console
- HDMI
- µSD-Card slot
- Audio Line-In / Line-Out
- GPIO pinheaders

https://wiki.in-circuit.de/index.php5?title=ICnova_ADB4006
https://wiki.in-circuit.de/index.php5?title=ICnova_A20_SODIMM

devicetree upstreamed with linux 6.5

Signed-off-by: Ludwig Kormann <ludwig.kormann@ict42.de>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-11-12 16:47:00 +00:00
Samuel Holland
43b573df33 sunxi: mmc: Move header to the driver directory
The MMC controller driver is (and ought to be) the only user of these
register definitions. Put them in a header next to the driver to remove
the dependency on a specific ARM platform's headers.

Due to the sunxi_mmc_init() prototype, the file was not renamed. None of
the register definitions were changed.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-11-12 16:45:08 +00:00
Tom Rini
da2e3196e4 Merge patch series "arm: dts: k3-am6: Fix Ethernet/DMA"
To quote the author:

Since commit [1], Ethernet is broken on TI AM62 and AM64 platforms.

The commit [1] is not the culprit. It just unearths the problem by fixing
the error check in k3-udma.c. This issue was silently being ignored earlier
due to wrong error check. [NULL instead of FDT_ADDR_T_NONE].

Fix the issue by adding the necessary register spaces for the u-boot K3-UDMA
driver for AM62 and AM64 platforms.

These properties will eventually make it into the SoC DTSi files [2] after
which these can be dropped from k3-*-u-boot.dtsi files.

[1] - 5fecea171de3dd ("treewide: use dev_read_addr_*_ptr() where appropriate")
[2] - https://lore.kernel.org/linux-arm-kernel/20230810174356.3322583-1-vigneshr@ti.com/
2023-11-10 15:25:47 -05:00
Siddharth Vadapalli
62be808183 arm: dts: k3-am642: Update main_bcdma and main_pktdma nodes
Update main_bcdma and main_pktdma nodes for native configuration in the
absence of DM services.

Drop duplicate main_pktdma node in k3-am642-sk-u-boot.dtsi.

Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
2023-11-10 15:25:25 -05:00
Roger Quadros
9a3f2b6798 arm: dts: k3-am625-verdin-wifi-dev-u-boot.dtsi: Fix DMA/Ethernet
Update main_bcdma and main_pktdma nodes for native configuration in the
absence of DM services. u-boot k3-udma driver expects these additional
register fields else probe will fail.

Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-11-10 15:25:25 -05:00
Siddharth Vadapalli
d4f148774b arm: dts: k3-am625-sk-u-boot.dtsi: Update main_bcdma and main_pktdma nodes
Update main_bcdma and main_pktdma nodes for native configuration in the
absence of DM services.

Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
2023-11-10 15:25:25 -05:00
Sean Anderson
47cfdb2192 arm: semihosting: Support semihosting fallback on 32-bit ARM
Add support for a semihosting fallback on 32-bit ARM. The assembly is
lightly adapted from the irq return code, except there is no offset
since lr already points to the correct instruction. The C side is mostly
like ARM64, except we have fewer cases to deal with.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2023-11-10 12:52:33 -05:00
Sean Anderson
6ef83ab6be arm: semihosting: Fix returning from traps on ARMv6 and lower
U-Boot runs in supervisor mode. On ARMv6 and lower, software interrupts
are taken in supervisor mode. When entering an interrupt, the link
register is set to the address of the next instruction. However, if we
are already in supervisor mode, this clobbers the link register. The
debugger can't help us, since by the time it notices we've taken a
software interrupt, the link register is already gone. Work around this
by moving the return address to another register.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2023-11-10 12:52:28 -05:00
Sean Anderson
298c26c5c7 arm: Fix software interrupt handler
When we take a software interrupt, we are already in supervisor mode.
get_bad_stack assumes we are not in supervisor mode so it can clobber
the stack pointer. This causes us to have an invalid stack once that
macro finishes. Revert back to the get_bad_stack_swi macro which was
previously removed.

Fixes: 41623c91b0 ("arm: move exception handling out of start.S files")
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2023-11-10 11:55:17 -05:00
Tom Rini
3b913c1482 Merge tag 'u-boot-stm32-20231110' of https://source.denx.de/u-boot/custodians/u-boot-stm
_ Fix compilation issue when SYS_DCACHE_OFF and/or SYS_DCACHE_SYS are enabled
_ Fix issue following DT sync with kernel 6.3 for stm32mp15xx-ev1 and DHSOM SoM
_ Enable TCP, IPv6, wget on DH STM32MP15 DHSOM
_ Limit u-boot.itb size to 0x160000 bytes on DH STM32MP15 DHSOM
_ Read auth stats and boot_partition from tamp
2023-11-10 11:01:51 -05:00
Tom Rini
bb7121f6aa Merge branch '2023-11-10-assorted-fixes'
- Fix some issues Coverity has reported, update MAINTAINERS file,
  another bootstd fix, typo fix in error message, gitignore fix and
  update TI's URL in many places.
2023-11-10 11:01:51 -05:00
Nishanth Menon
a94a4071d4 tree-wide: Replace http:// link with https:// link for ti.com
Replace instances of http://www.ti.com with https://www.ti.com

Signed-off-by: Nishanth Menon <nm@ti.com>
2023-11-10 11:01:50 -05:00
Johan Jonker
8ffa9ed295 rockchip: include: asm: fix entering download mode rk3066
Keep track of the re-entries with help of the lr register.
This binary can be re-used and called from various BROM functions.
Only when it's called from the part that handles SPI, NAND or EMMC
hardware it needs to early return to BROM ones.
In download mode when it handles data on USB OTG and UART0
this section must be skipped.

Unlike newer Rockchip SoC models the rk3066 BROM code does not have built-in
support to enter download mode on return to BROM. This binary must check
the boot mode register for the BOOT_BROM_DOWNLOAD flag and reset if it's set.
It then returns to BROM to the end of the function that reads boot blocks.
From there the BROM code goes into a download mode and waits for data
on USB OTG and UART0.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-11-10 10:58:56 -05:00
Tim Lunn
b01adfe59d rockchip: rv1126: Read cpuid from otp and set ethaddr
Provide configuration to read cpuid and generate a persistent
MAC address in ethaddr

Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-11-10 10:58:44 -05:00