Commit graph

10 commits

Author SHA1 Message Date
Tudor Laurentiu
8d3eaa9709 powerpc/mpc85xx: use correct dma compatible for several SoCs
Newer qoriq socs have an updated dma ip block with a
different compatible. Let's make sure we use the proper
string so that the dmas get their liodn.
In order to have the means to specify the compatible
string, the liodn setting macros were updated to receive
a new parameter for it.
The following SoCs were changed to use the new compatible:
 T1023/4, T1040, T2080/1, T4240, B4860.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:16 -08:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Cristian Sovaiala
1f06c9af31 powerpc/mpc85xx: Changed LIODN offset values
Extending LIODN offset range from 1-5 to 1-10
While using a qman portal with a higher index the LIODN offset
is incorrectly set, thus extending the range of offsets covers
all 10 qman portals

Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
Acked-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:57:34 -05:00
Timur Tabi
5c5befda58 powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNs
The SET_PCI_LIODN() macro takes a compatible property string as a parameter, so that it knows
which PCI device tree node to look for.  The calls to these macros are using a hard-coded string,
but we already have the CONFIG_SYS_FSL_PCIE_COMPAT macro which contains the same string, so we
should use that.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 18:32:16 -05:00
Kumar Gala
4d28db8a1e powerpc/85xx: Add support for RMan LIODN initialization
This patch is intended to initialize RMan LIODN related registers on
P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to
qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-18 00:36:48 -05:00
Kumar Gala
1a0c64219d powerpc/85xx: Update setting of SRIO LIODNs
Properly set the LIODN values associated with SRIO controller.  On
P4080/P3060 we have an LIODN per port and one for the RMU.  On
P2041/P3041/P5020 we have 2 LIODNs per port.

Update the tables for all of these devices to properly handle both
styles.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-18 00:36:15 -05:00
Haiying Wang
34fdbdf8d9 powerpc/p3041: fixup portal config info
P3041 has 10 qman portals, we need to configure all of them:
* As there are only 4 physical cores sdest can only be 0 to 3
* We assign dqrr & frame data LIODNs for all portals so if they
  are utilized the proper mapping tables can be setup uniquely
  (PAMU stashing)
* We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN
  assignments are tuned around an assumption of at most 5
  partitions.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-13 23:38:10 -05:00
Kumar Gala
58b2f96e38 powerpc/85xx: Fix compile errors if CONFIG_SYS_DPAA_QBMAN isn't set
Add ifdef protection for qp_info and liodn associated with Q/BMan.  Also
rearrange setting of _tbl_sz variables to utilize existing ifdef
protection for things like FMAN.

Also add protection around setup_portals() call in corenet_ds board
code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:19 -05:00
Laurentiu TUDOR
33e683541e powerpc/85xx: Fix setting of LIODN prop in PCIe nodes on P3041/P5020
We utilize the compatible string to find the node to add fsl,liodn
property to.  However P3041 & P5020 don't have "fsl,p4080-pcie"
compatible for their PCIe controllers as they aren't backwards compatible.

Allow the macro's to specify the PCIe compatible to use to allow SoC
uniqueness.  On P3041 & P5020 we utilize "fsl,qoriq-pcie-v2.2" for the
PCIe controllers.

Signed-off-by: Laurentiu TUDOR <Laurentiu.Tudor@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:43 -05:00
Kumar Gala
d5d2cd4331 powerpc/p3041: Add various p3041 specific information
Add P3041 SoC specific information:
* SERDES Table
* LIODN setup
* Portal configuration

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00