To sync the DT binding with Linux, the register base must be taken
from the parent syscon node.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Move U_BOOT_DRIVER() entry from the data file (clk-uniphier-mio.c)
to the core support file (clk-uniphier-core.c) because I do not want
to repeat the driver boilerplate when I add more clock data.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
pmucru is a module like cru which is a clock controller manage some PLL
and module clocks.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add a simple driver for the clocks provided by the MIPS Boston
development board. The system provides information about 2 clocks whose
rates are fixed by the bitfile flashed in the boards FPGA, and this
driver simply reads the rates of these 2 clocks.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The patch is referred to at91 clock driver of Linux, to make
the clock node descriptions in DT aligned with the Linux's.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP
(Boot and Power Management Processor). This change implements a driver
that does that. A tegra/ sub-directory is created to follow the existing
pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually
any Tegra186 build of U-Boot will need the feature.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The already available ilog2 function does exactly the same in the common
case than the log2 function the current clock-driver reimplement.
So, simply move to that one.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
MMC core will use 400KHz for card initialize first and then switch to
higher frequency like 50MHz, we need to support both 400KHz and about
50MHz for dwmmc controller.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
With the number of Rockchip clock drivers increasing, don't clutter up
the core drivers/clk directory with them and instead move them out of
the way into a separate subdirectory.
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Updated for rk3399:
Signed-off-by: Simon Glass <sjg@chromium.org>
The current code picks the first available clock. In U-Boot proper this is
the oscillator device, not the SoC clock device. As a result the HDMI display
does not work.
Fix this by calling rockchip_get_clk() instead.
Fixes: 135aa950 (clk: convert API to match reset/mailbox style)
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
According to the TRM the minimum FREF frequency is 269kHz not MHz.
Adapt the constant accordingly.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
The function is very specific to the rk3288 in its arguments
referencing the rk3288 cru and grf and every other rockchip soc
has differing cru and grf registers. So make that function naming
explicit.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
This does not have much impact on behavior, but makes code look more
more like Linux. The use of devm_ioremap() often helps to delete
.remove callbacks entirely.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Simple version of clk_get_by_index() added by:
"dm: clk: Add a simple version of clk_get_by_index()"
(sha1: a4b10c088c)
is only working for #clock-cells=<1> but not for
any other values. Fixed clocks is using #clock-cells=<0>
which requires full implementation.
Remove simplified versions of clk_get_by_index() and use full version.
Also remove empty clk_get_by_name() which is failing when it is called
which is useless.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Add support for of-platdata with rk3288. This requires decoding the
of-platdata struct and setting up the devices from that. Also the driver
needs to be renamed to match the string that of-platdata will search for.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is more correct to avoid touching the device tree in the probe() method.
Update the driver to work this way. Also add an error check on grf since if
that fails then we should not use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
clk->id is unsigned, so it can't be < 0. Remove the check for that.
FWIW, this issue was introduced when the clock API converted e.g.
clk_get_rate()'s clock ID parameter from an int to an unsigned long
(with a struct clk), without removing this check.
Fixes: 135aa95002 ("clk: convert API to match reset/mailbox style")
Reported-by: Coverity Scan
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock
provider now implements a single set of clocks. This provides a simpler
conceptual interface to clients, and better aligns with device tree
clock bindings.
* Clocks are now identified with a single "struct clk", rather than
requiring clients to store the clock provider device and clock identity
values separately. For simple clock consumers, this isolates clients
from internal details of the clock API.
* clk.h is split so it only contains the client/consumer API, whereas
clk-uclass.h contains the provider API. This aligns with the recently
added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers
can customize these operations if needed. This also aligns with the
recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and
clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.
Buildman shows no clock-related errors for any board for which buildman
can download a toolchain.
test/py passes for sandbox (which invokes the dm clk test amongst
others).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
For odroid-c2 (arch-meson) for now disable designware eth as meson
now needs to do some harder GPIO work.
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
lib/efi_loader/efi_disk.c
Modified:
configs/odroid-c2_defconfig
Setup the clocks for the gmac ethernet interface. This assumes the mac
clock is fed by an external clock which is common on RK3288 based
devices.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>
The current reset API implements a method to reset the entire system.
In the near future, I'd like to introduce code that implements the device
tree reset bindings; i.e. the equivalent of the Linux kernel's reset API.
This controls resets to individual HW blocks or external chips with reset
signals. It doesn't make sense to merge the two APIs into one since they
have different semantic purposes. Resolve the naming conflict by renaming
the existing reset API to sysreset instead, so the new reset API can be
called just reset.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add a clock driver for Exynos7420 SoC. There are about 25 clock controller
blocks in Exynos7420 out of which support for topc, top0 and peric1 blocks
are added in this initial version of the driver.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This is the initial commit for the UniPhier clock drivers.
Currently, only the Media I/O clock is supported.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers
and dividers capable of supplying clock to various controllers
on or off-chip.
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Add a feature which speeds up the CPU to full speed in SPL to minimise
boot time. This is only supported for certain boards (at present only
jerry).
Signed-off-by: Simon Glass <sjg@chromium.org>
The displays need to use NPLL and also select some new peripheral clocks.
Add support for these to the clock driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
The current method assumes that clocks are numbered from 0 and we can
determine a clock by its number. It is safer to use an ID in the clock's
platform data to avoid the situation where another clock is bound before
the one we expect.
Move the existing code into rk3036 since it still works there. Add a new
implementation for rk3288.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function adds quite a bit of code to SPL and we probably don't need
all the features in SPL. Add a simple version (for SPL only) to save space.
Signed-off-by: Simon Glass <sjg@chromium.org>
The current approach of using uclass_get_device() is error-prone. Another
clock (for example a fixed-clock) may cause it to break. Add a function that
does a proper search.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present we use the same peripheral ID for clocks and pinctrl. While this
works it is probably better to use the device tree clock binding ID for
clocks. We can use the clk_get_by_index() function to find this.
Update the clock drivers and the code that uses them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a method which can locate a clock for a device, given its index. This
uses the normal device tree bindings to return the clock device and the
first argument which is normally used as a peripheral ID in U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit intends to implement "fixed-clock" as in Linux.
(drivers/clk/clk-fixed-rate.c in Linux)
If you need a very simple clock to just provide fixed clock rate
like a crystal oscillator, you do not have to write a new driver.
This driver can support it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
The most basic thing for clock is to enable it, but it is missing
in this uclass.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add a driver for setting up and modifying the various PLLs, peripheral
clocks and mmc clocks on RK3036
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Clocks are an important feature of platforms and have become increasing
complex with time. Most modern SoCs have multiple PLLs and dozens of clock
dividers which distribute clocks to on-chip peripherals.
Some SoC implementations have a clock API which is private to that SoC family,
e.g. Tegra and Exynos. This is useful but it would be better to have a
common API that can be understood and used throughout U-Boot.
Add a simple clock API as a starting point. It supports querying and setting
the rate of a clock. Each clock is a device. To reduce memory and processing
overhead the concept of peripheral clocks is provided. These do not need to
be explicit devices - it is possible to write a driver that can adjust the
I2C clock (for example) without an explicit I2C clock device. This can
dramatically reduce the number of devices (and associated overhead) in a
complex SoC.
Clocks are referenced by a number, and it is expected that SoCs will define
that numbering themselves via an enum.
Signed-off-by: Simon Glass <sjg@chromium.org>
