Provide a default linker script for SPL binaries. Start address
and size of text section and BSS section are configurable. All
sections are arranged in a way that only relevant sections are
kept in the code section for maximum size reduction. All other
sections are kept but moved outside the code section to help
with debugging.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Both real Malta boards & emulators that mimic Malta (eg. QEMU) can
support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards,
which enables the user to make use of the whole 64 bit address space.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
If dev->iobase is 64 bits wide then writing the value of the BAR into a
pointer to iobase will not work on big endian systems, where the BAR
value will incorrectly get written to the upper 32 bits of the 64 bit
variable. Fix this by reading the BAR into a u32, matching the type
expected by pci_read_config_dword.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fix the pcnet driver to build safely on 64 bit platforms, in preparation
for allowing MIPS64 builds for Malta boards.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Now that MIPS virt_to_phys can handle kseg1 addresses on MIPS32, stop
manually converting addresses to their kseg0 equivalents in the pcnet
driver.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Use CPHYSADDR to implement the virt_to_phys function for converting from
a virtual to a physical address for MIPS32, much as is already done for
MIPS64. This allows for virt_to_phys to work regardless of whether the
address being translated is in kseg0 or kseg1, unlike the previous
subtraction based approach which only worked for addresses in kseg0.
This allows for drivers to provide an address to virt_to_phys without
needing to manually ensure that kseg1 addresses are converted to
equivalent kseg0 addresses first.
This patch is equivalent to this Linux patch currently waiting to be
reviewed & merged:
https://patchwork.linux-mips.org/patch/12564/
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
EFI is not needed on x600. So lets remove the EFI support to make it fit
into the 0x60000 image size limit again.
Signed-off-by: Stefan Roese <sr@denx.de>
As the old ethernet PHY is not available any more, the x600 board has
been redesigned with the Micrel KSZ9031 PHY. This patch adds support
to autodetect the PHY and configure the Micrel PHY correctly.
Signed-off-by: Stefan Roese <sr@denx.de>
In the big move of CONFIG_HUSH_PARSER to config files the clearfog
somehow missed out.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
So far this is hardcoded to 2, but it should really be read
from the I/O APIC register.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds basic quark platform ASL files. They are intended to be
included in dsdt.asl of any board that is based on this platform.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There is a device.h for quark on-chip devices, mainly for definitions
of internal PCI device numbers, but it's not ready to be included by
ASL files. Update to use hex numbers for PCI dev and __ASSEMBLY__.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
ASL files may include various U-Boot header files, but IASL compiler
does not understand any C language embedded in these header files.
To reuse those header files for ASL compiling, use __ASSEMBLY__ in
the header files to exclude everything that is not liked by IASL.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The irqroute.asl file is already common enough to all x86 platforms.
Platform ASL files need only provide a irqroute.h to describe how
internal PCI devices and PCIe downstream port devices' INTx pins are
routed to which PIRQ pin.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move the irqlinks.asl file currently in the BayTrail directory to
a common place to be shared among all x86 platforms. As the PIRQ
routing control programming interface is common to Intel chipsets,
leave the common part in the common file, and move the platform
specific part to the platform files.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For odroid-c2 (arch-meson) for now disable designware eth as meson
now needs to do some harder GPIO work.
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
lib/efi_loader/efi_disk.c
Modified:
configs/odroid-c2_defconfig
All the output clock parameters of a DPLL needs to be programmed before
locking the DPLL. But it is being configured after locking the DPLL which
could potentially bypass DPLL. So fixing this sequence.
Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Since f6c8f38ec6 ("tools/genboardscfg.py: improve performance more
with Kconfiglib"), this tool does not use the subprocess module.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
In order for CONFIG_IS_ENABLED(FOO) to work we need to move the changes
that CONFIG_FIT_DISABLE_SHA256 makes to be prior to the evaluation by
CONFIG_IS_ENABLED(foo)
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
[trini: Move CONFIG_FIT_DISABLE_SHA256 parts to fix build breakage]
Signed-off-by: Tom Rini <trini@konsulko.com>
Since 1e6ad55c05 ("armv8/cache: Change cache invalidate and flush
function"), this routine can be used for both cache flushing and
cache invalidation. So, it is better to not include "flush" in
this routine name.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
__asm_dcache_all can directly return to the caller of
__asm_{flush,invalidate}_dcache_all.
We do not have to waste x16 register here.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Different AM335x based platforms have different serial consoles. As serial
console is Kconfig option a separate defconfig has to be created for each
platform. So pass the serial device dynamically.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add minimal dts support for AM335x-ICEv2 board
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Populate the right dtb file and console for AM335x-ICEv2 board.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
In order to enable cpsw on AM335x ICEv2 board, the following needs to be done:
1)There are few on board jumper settings which gives a choice between
cpsw and PRUSS, that needs to be properly selected[1]. Even after selecting
this, there are few GPIOs which control these muxes that needs to be held high.
2) The clock to PHY is provided by a PLL-based clock synthesizer[2] connected
via I2C. This needs to properly programmed and locked for PHY operation.
And PHY needs to be reset before before being used, which is also held by
a GPIO.
3) RMII mode needs to be selected.
[1] http://www.ti.com/lit/zip/tidr336
[2] http://www.ti.com/lit/ds/symlink/cdce913.pdf
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The CDCE913 and CDCEL913 devices are modular PLL-based, low cost,
high performance , programmable clock synthesizers. They generate
upto 3 output clocks from a single input frequency. Each output can
be programmed for any clock-frequency.
Adding support for the same.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
AM335x ICEv2 contains a 2Gbit(128Mx16) of DDR3 SDRAM(MT41J128M16JT-125),
capable of running at 400MHz. Adding this specific DDR configuration
details running at 400MHz.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Similar to other TI's AM335x platforms, AM335x ICEv2 also has an
eeprom populated for its unique identification. Adding this info
so that AM335x ICEv2 specific initialization can be done.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Re-org env sections so that we can fall back to env is in FAT on SD
card, for broader board compatibility
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
As per mmc device tree binding documentation card detect gpio has
to be active low signal. When a hardware is designed with active
high card detect, gpio polarity has to be changed with
cd-inverted dt property.
In AM335x the card detect gpio is designed as active low gpio.
So correcting the dt card detect gpio definition.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Use a single defconfig for all AM335x platforms by enabling FIT
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Allow am335x-bone.dts to be built and enable uart and timer
for all beaglebones.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
FIT allows for a multiple dtb in a single image. SPL needs a way to
detect the right dtb to be used. Adding support for the same.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Convert usb host boot defconfig to use DM, DT. Also enable FIT
support.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Use a single defconfig for all AM43xx platforms by enabling FIT and delete
the platform specific defconfigs.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
FIT allows for a multiple dtb in a single image. SPL needs a way to
detect the right dtb to be used. Adding support for the same.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Removing:
uart3_defconfig:
Now uart3 can be selected using menuconfig, removing separate
config for uart mode. Doing uart boot is not straight forward as ROM uses
uart3 as default serial console. In order to boot to prompt, concole in both
u-boot and kernel needs to be changed.
qspiboot_defconfig:
The only advantage of enabling QSPI_BOOT is selecting env in QSPI.
Eventually env needs to be selected by menuconfig so removing
qspiboot_defconfig. qspiboot can be done using dra7xx_evm_defconfig.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Use a single defconfig for all DRA7 platforms by enabling FIT and delete
the platform specific defconfigs.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
