4 commits

Author	SHA1	Message	Date
Michal Simek	03606ff42e	ARM: zynq: Show ECC status on the same line as DRAM size ... Without this patch is DRAM size one line below DRAM: which is not nice Origin: I2C: ready DRAM: Memory: ECC disabled 1 GiB MMC: zynq_sdhci: 0 Fixed by this patch: I2C: ready DRAM: ECC disabled 1 GiB MMC: zynq_sdhci: 0 Signed-off-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>	2014-07-23 15:36:55 +02:00
Michal Simek	10fa49f428	ARM: zynq: Do not use half memory size for ECC case ... Memory size should be specified without ECC place. If you need to have half memory size, please change u-boot configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>	2014-05-14 07:43:34 +02:00
Michal Simek	ec9638659f	ARM: zynq: Fix sparse warning in ddrc.c ... Warning: arch/arm/cpu/armv7/zynq/ddrc.c:43:24: warning: Using plain integer as NULL pointer Signed-off-by: Michal Simek <michal.simek@xilinx.com>	2014-05-14 07:43:34 +02:00
Michal Simek	148ba55cc6	zynq: Add new ddrc driver for ECC support ... The first 1MB is not initialized by first stage bootloader. Check if memory is setup to 16bit mode and ECC is enabled. If it is, clear the first 1MB. Also u-boot should report only the half size of memory. Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>	2013-08-12 08:59:55 +02:00