As we have already DRAM initialization code for V3s SoC, we can
defaultly enable SPL now on Lichee Pi Zero.
Add CONFIG_SPL in Lichee Pi Zero defconfig.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This syncs all of the currently Kconfig'd symbols out of the headers and
into the defconfig files. This has two exceptions, first am335x_evm
needs to be converted to DM in SPL and then it can stop undef'ing
CONFIG_DM_USB. Leaving this as-is results in a build failure, and
without work, run time failure. The other case is am43xx_evm.h and in
turn am43xx_evm_usbhost_boot. The problem here is that we need DWC3 USB
host mode in SPL, but still desire to have gadget mode in U-Boot proper.
Signed-off-by: Tom Rini <trini@konsulko.com>
Lichee Pi Zero is a development board with a V3s SoC, which features
64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not
soldered in production batch), a 40-pin RGB LCD connector and some extra
pins available as 2.54mm pins or stamp holes.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
