This patch adds the CONFIG_PCI_4xx_PTM_OVERWRITE option and replaces
the ugly 'if defined(BOARD1) || ... || defined(BOARDn)' construct
in 4xx pci code.
When CONFIG_PCI_4xx_PTM_OVERWRITE is defined the default ptm register
setup can be overwritten through environment variables ptm1la, ptm1ms,
ptm2la and ptm2ms to do application specific pci target BAR configuration.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch fixes PMC405DE support. Patch 85d6bf0b fixed out-of-tree
building for this board but the loadpci object did not get linked
after that.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
Using a separate "u-boot" environment variable allows to easily
specify different filenames for the update procedure. This is also in
line with many other board configurations defining an "update" script.
Signed-off-by: Detlev Zundel <dzu@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Some board ports place TEXT_BASE at a location that would cause the
RESET_VECTOR_ADDRESS not to be at 0xfffffffc when we link. By default
we assume RESET_VECTOR_ADDRESS will be 0xfffffffc if the board doesn't
explicitly set it.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
There is no reason to do a run time check for e500 v1 based cores to
determine if we have the GUTs RSTCR facility. Only the first generation
of PQ3 parts (MPC8540/41/55/60) do not have it. So checking to see if
we are e500 v2 would miss future parts (like e500mc).
Just change this to be ifdef'd based on CONFIG_MPC85{40,41,55,60}.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
While in probecpu() UART is still not initialized.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fixing the number of cores in the device tree based on the actual number of
cores on the system. With this same device tree image can be used for dual
core and single core members of otherwise exactly same SOC.
For example:
* P2020RDB and P2010RDB
* P1020RDB and P1011RDB
* MPC8641D and MPC8641
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Incase the system is detected with Unknown SVR, let the system boot
with a default value and a proper message.
Now with dynamic detection of SOC properties from SVR, this is necessary
to prevent a crash.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Refactor the code into a simple bitmask lookup table that determines if
a given PCI controller is enabled and if its in host/root-complex or
agent/end-point mode.
Each processor in the PQ3/MPC86xx family specified different encodings
for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Cleaned up cpu/mpc85xx/Makefile to use CONFIG_* for those obvious cases
we have like PCI, CPM2, QE. Also reworked it to use one line per file
for everything and sorted in alphabetical order.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
After programming a new LAW, we should read-back the LAWAR register so that
we sync the writes. Otherwise, code that attempts to use the new LAW-mapped
memory might fail right away.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Its possible that we try and copy the boot page code out of flash into a
DDR location that doesn't have a TLB cover it. For example, if we have
3G of DDR we typically only map the first 2G. In the cases of 4G+ this
wasn't an issue since the reset page TLB mapping covered the last page
of memory which we wanted to copy to.
We now change the physical address of the reset page TLB to map to the
true physical location of the boot page code, copy and than set the
TLB back to its 1:1 mapping of the reset page.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Allow us to search the TLB array based on an address. This is useful
if we want to change an entry but dont know where it happens to be
located.
For example, the boot page mapping we use on MP or the flash TLB that
we change the WIMGE settings for after we've relocated.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
In future Book-E implementations IVORs will most likely go away and be
replaced with fixed offsets. The IVPR will continue to exist to allow
for relocation of the interrupt vectors.
This code adds support to setup the IVORs as their fixed offset values
per the ISA 2.06 spec when we transition from u-boot to another OS
either via 'bootm' or a cpu release.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The ddr_pd_cntl isn't defined in any reference manual and thus we wil
remove especially since we set it to 0, which would most likely be its
POR value.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The warning is bogus, so silence it by initializing the 'ret' variable.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Enable eSDHC Clock based on generic CONFIG_FSL_ESDHC define instead of a
platform define. This will enable all the 85xx platforms to use sdhc_clk
based on CONFIG_FSL_ESDHC.
Signed-off-by: Gao Guanhua <B22826@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The value of I2C_TIMEOUT in fsl_i2c.c has several problems. First, it is
defined as CONFIG_HZ/4, but it is used as a count of microseconds, so it makes
no sense to derive it from a clock rate. Second, the current value (250) is
too low for some boards, so it needs to be increased. Third, the timeout
necessary for multiple-master arbitration is larger than the timeout for basic
read/write operations, so we shouldn't have a single constant for both timeouts.
Finally, it would be nice if we could override these values on a per-board
basis.
Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Wolfgang Denk <wd@denx.de>
Tested-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
Reset any i2c devices that may have been interrupted during a system reset.
Normally this would be accomplished by clocking the line until SCL and SDA
are released and then sending a start condtiion (From an Atmel datasheet).
There is no direct access to the i2c pins so instead create start commands
through the i2c interface. Send a start command then delay for the SDA Hold
time, repeat this by disabling/enabling the bus a total of 9 times.
Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
Rather than maintain/extend the current ifeq($(ARCH)) mess that exists in
the standalone Makefile, push the setting up of LOAD_ADDR out to the arch
config.mk (and rename to STANDALONE_LOAD_ADDR in the process). This keeps
the common code clean and lets the arch do whatever crazy crap it wants in
its own area.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Removed stdio.h inclusion and moved trace macros to use printf avoiding to
write debug informations to standard error.
Signed-off-by: Giuseppe Condorelli <giuseppe.condorelli@st.com>
Some files included my old standerd file header which had a "All
Rights Reserved" part. As this has never been my intention, I remove
these lines to make the files compatible with GPL v.2 and later.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Fix warning messages:
cmd_mtdparts.c:1429: warning: format '%08lx' expects type 'long
unsigned int', but argument 6 has type 'u32'
cmd_mtdparts.c:1429: warning: format '%08lx' expects type 'long
unsigned int', but argument 7 has type 'u32'
Signed-off-by: Wolfgang Denk <wd@denx.de>
Added a arch_preboot_os() function that cpu specific code can implement to
allow for various modifications to the state of the machine right before
we boot. This can be useful to setup register state to a specific
configuration.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Now that the PCI, SATA et al compile problems have been resolved, the
cludge that was applied to avoid them can be removed
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Primary intent is to resolve build errors for this board which has been
neglected for a very long time. I do not have one of these boards, so I
cannot test functionality
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
This patch is based on a patch submitted by Jean-Christophe PLAGNIOL-VILLARD
on 18th May 2008 as part of a general i386 / sc520 fixup which was never
applied
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
