Commit graph

2977 commits

Author SHA1 Message Date
Ajay Kumar
466d40396e ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chip
This patch adds DT properties for fimd and the parade bridge chip
present on peach_pit. The panel supports 1366x768 resolution.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Ajay Kumar
a99cea0313 exynos5420: add callbacks needed for exynos_fb driver
Add initialization code for peach_pit panel, parade bridge chip,
and backlight.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Ajay Kumar
2358fc8ed9 ARM: exynos: Add missing declaration for gpio_direction_input
This patch adds missing declaration for gpio_direction_input
function, thereby helps in resolving compilation warnings.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Ajay Kumar
45c480c9f6 video: exynos_fimd: Add framework to disable FIMD sysmmu
On Exynos5420 and newer versions, the FIMD sysmmus are in
"on state" by default.
We have to disable them in order to make FIMD DMA work.
This patch adds the required framework to exynos_fimd driver,
and disables FIMD sysmmu on Exynos5420.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Ajay Kumar
496f0e47e1 arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Ajay Kumar
e6756f6a2e arm: exynos: Add RPLL for Exynos5420
RPLL is needed to drive the LCD panel on Exynos5420 based boards.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Ajay Kumar
f0017175e3 exynos_fb: Remove usage of static defines
Previously, we used to statically assign values for vl_col, vl_row and
vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.

Introducing the function exynos_lcd_early_init() would take care of this
assignment on the fly by parsing FIMD DT properties, thereby allowing us
to remove LCD_XRES and LCD_YRES from the main config file.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Przemyslaw Marczak
73eca21128 odroid: kconfig: add odroid_defconfig
This config is valid for two devices:
- Odroid X2,
- Odroid U3.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 13:58:50 +09:00
Przemyslaw Marczak
a47fa7906c odroid: add odroid U3/X2 device tree description
This is a standard description for Odroid boards.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 13:58:50 +09:00
Przemyslaw Marczak
1fb4dab2a1 arm:reset: call the reset_misc() before the cpu reset
On an Odroid U3 board, the SOC is unable to reset the eMMC card
in the DWMMC mode by the cpu software reset. Manual reset of the card
by switching proper gpio pin - fixes this issue.

Such solution needs to add a call to pre reset function.
This is done by the reset_misc() function, which is called before reset_cpu().
The function reset_misc() is a weak function.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>

Changes v4:
- arch/arm/reset: fix weak function attribute to proper style
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 13:58:49 +09:00
Przemyslaw Marczak
4fb4d55a35 arch:exynos: boot mode: add get_boot_mode(), code cleanup
This patch introduces code clean-up for exynos boot mode check.
It includes:
- removal of typedef: boot_mode
- move the boot mode enum to arch-exynos/power.h
- add bootmode for sequence: eMMC 4.4 ch4 / SD ch2
- add new function: get_boot_mode() for OM[5:1] pin check
- update spl boot code

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>

Changes v5:
- exynos: boot mode: add missing bootmode (1st:EMMC 4.4 / 2nd:SD ch2)

Changes v6:
- none

changes v7:
- change boot mode name: BOOT_MODE_MMC to BOOT_MODE_SD
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 13:58:49 +09:00
Przemyslaw Marczak
19f1b629bf exynos: pinmux: fix the gpio names for exynos4x12 mmc
This change fixes the bad gpio configuration for the exynos dwmmc.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Beomho Seo <beomho.seo@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 13:58:49 +09:00
R Sricharan
681f785f7c ARM: DRA72: DDR3: Add emif settings for 666MHz clock
On DRA72x, EMIF supports DDR3 upto 667MHz.
Adding the required settings for DDR3 at 666MHz and enabling it.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-09-04 13:12:49 -04:00
Khoronzhuk, Ivan
e6c9428a2f keystone2: use readl/writel functions instead of redefinition
There is no reason to redefine pure readl/writel functions.
So remove this redundancy.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: Vitaly Andrianov <vitalya@ti.com>
2014-09-04 13:06:00 -04:00
Khoronzhuk, Ivan
1c4044ae4a ARM: keystone: clock: use correct BWADJ field mask for PASSPLLCTL0
The mask for BWADJ field of PASSPLLCTL0 register has to be 0xff, but
by mistake, here is used shift instead of mask, so correct it.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-09-04 13:05:57 -04:00
Masahiro Yamada
a1263632bb mx6: tqma6: get board support back to Kconfig build system
The QS Systems TQMa6 board support was added by commit cb07d74e
and lost by commit e82abaeb.

Commit e82abaeb merged the IMX branch based on pre-Kconfig
and the mainline based on post-Kconfig, simply deleting
the boards.cfg file.  As a result, some boards added just before
the merge were lost.

This commit adds Kconfig, defconfig, MAINTAINERS for TQMa6 board
to work on the Kconfig infrastructure.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Stefano Babic <sbabic@denx.de>
2014-08-31 12:01:04 -04:00
Masahiro Yamada
16e16fdde2 nomadik: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Nomadik board select menu to nomadik/Kconfig.

Move also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="nomadik").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-30 21:22:00 -04:00
Masahiro Yamada
ef2b694c73 highbank: kconfig: move common settings
Move Highbank-specific settings to highbank/Kconfig.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Rob Herring <robh@kernel.org>
2014-08-30 21:22:00 -04:00
Masahiro Yamada
22f2be7a12 orion5x: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Orion5x board select menu to orion5x/Kconfig.

Move also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="orion5x").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
c338f09e96 keystone: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Keystone board select menu to keystone/Kconfig.

Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="keystone").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
6c5431ac81 omap5: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the OMAP5 board select menu to omap5/Kconfig.

Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="omap5").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
d08215a5f1 omap4: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the OMAP4 board select menu to omap4/Kconfig.

Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="omap4").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
3cfbcb58d3 omap3: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the OMAP3 board select menu to omap3/Kconfig.

Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="omap3

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
3491ba6311 davinci: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Davinci board select menu to davinci/Kconfig.

Move also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="davinci").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
72df68cc6b exynos: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Exynos board select menu to exynos/Kconfig.

Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="exynos").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
47539e2317 kirkwood: kconfig: refactor Kconfig and defconfig
Becuase the board select menu in arch/arm/Kconfig is too big,
move the KirkWood board select menu to kirkwood/Kconfig.

Consolidate also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="kirkwood").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Prafulla Wadasdkar <prafulla@marvell.com>
Cc: Luka Perkov <luka@openwrt.org>
2014-08-30 21:21:21 -04:00
Masahiro Yamada
ad17a81c06 versatile: kconfig: move common settings
Move Versatile-specific settings to versatile/Kconfig.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-30 21:19:32 -04:00
Masahiro Yamada
f40b989863 rmobile: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Rmobile board select menu to rmobile/Kconfig.

Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="rmobile").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-08-30 21:19:32 -04:00
Masahiro Yamada
ddd960e6c4 tegra: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Tegra board select menu to tegra/Kconfig.

Insert the Tegra SoC select menu between the arch select and the
board select.

 Architecture select
 |-- Tegra Platform (Tegra)
     |- Tegra SoC select (Tegra20 / 30 / 114 / 124)
        |- Board select

Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="tegra*") and always "select" CONFIG_SPL as follows:

  config TEGRA
          bool
          select SPL

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
2014-08-30 21:19:32 -04:00
Masahiro Yamada
44dcb4036b zynq: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Zynq board select menu to zynq/Kconfig.

Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="zynq").

Refactor board/xilinx/zynq/MAINTAINERS too.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
2014-08-30 21:19:32 -04:00
Benoît Thébaudeau
eeadd3fe0f arm: Add missing .vectors section to linker scripts
Commit 41623c9 'arm: move exception handling out of start.S files' missed some
linker scripts. Hence, some boards no longer had exception handling linked since
this commit. Restore the original behavior by adding the .vectors section to
these linker scripts.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-08-30 07:46:41 -04:00
Tom Rini
3f1b6bebe0 arm64: Correct passing of Linux kernel args
The Documentation/arm64/booting.txt document says that pass in x1/x2/x3
as 0 as they are reserved for future use.

Signed-off-by: Tom Rini <trini@ti.com>
2014-08-30 07:46:40 -04:00
Steve Rae
9dec5270be arm: convert Cygnus and NSP boards to Kconfig
Convert the bcm958300k and the bcm958622hr boards from "boards.cfg" to Kconfig.

Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:40 -04:00
Scott Branden
da1f5ac295 arm: add Cygnus and NSP boards
The bcm_ep board configuration is used by a number of boards
including Cygnus and NSP.
Add builds for the bcm958300k and the bcm958622hr boards.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:40 -04:00
Scott Branden
562f01a2ba arm: bcmnsp: Add bcmnsp u-architecture
Base support for the Broadcom NSP SoC.
Based on iproc-common and the SoC specific reset function.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:40 -04:00
Scott Branden
7986688075 arm: bcmcygnus: Add bcmcygnus u-architecture
Base support for the Broadcom Cygnus SoC.
Based on iproc-common and the SoC specific reset function.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:40 -04:00
Scott Branden
c4b4500910 arm: iproc: Initial commit of iproc architecture code
The iproc architecture code is present in several Broadcom
chip architectures, including Cygnus and NSP.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:40 -04:00
Stefan Agner
b0e31c7b66 arm: vf610: add NFC clock support
Add NFC (NAND Flash Controller) clock support and enable them
at board initialization time.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-08-30 07:46:40 -04:00
Stefan Agner
baa3134440 arm: vf610: add NFC pin mux
Add pin mux for NAND Flash Controller (NFC). NAND can be connected
using 8 or 16 data lines, this patch adds pin mux entries for all
16 data lines.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-08-30 07:46:39 -04:00
Marek Vasut
221a49d5bd ARM: Fix overflow in MMU setup
The patch fixes a corner case where adding size to DRAM start resulted
in a value (1 << 32), which in turn overflew the u32 computation, which
resulted in 0 and it therefore prevented correct setup of the MMU tables.

The addition of DRAM bank start and it's size can end up right at the end
of the address space in the special case of a machine with enough memory.
To prevent this overflow, shift the start and size separately and add them
only after they were shifted.

Hopefully, we only have systems in tree which have DRAM size aligned to
1MiB boundary. If not, this patch would break such systems. On the other
hand, such system would be broken by design anyway.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-08-30 07:46:39 -04:00
Jiandong Zheng
2d66a0fd58 arm: bcm281xx: Add Ethernet Clock support
Enable Ethernet clock when Broadcom StarFighter2 Ethernet block
(CONFIG_BCM_SF2_ETH) is enabled.

Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:39 -04:00
Sergey Kostanbaev
0bf62d7bc4 arm: ep9315: Add .vectors section to lds and remove obsolete lds
However ep9315 don't use
interrupt vectors during startup, but _startup symbol is used inside uboot to
calculate actual monitor size.

Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com>
Cc: albert.u.boot@aribaud.net
2014-08-30 07:46:38 -04:00
Pavel Machek
99b97106f3 socfpga: initialize designware ethernet
Enable initialization fo designware ethernet controller. With this
patch, ethernet works in my configuration, provided I set ethernet
address in the environment.

Signed-off-by: Pavel Machek <pavel@denx.de>
2014-08-30 07:46:38 -04:00
Chin Liang See
3ab019e1dc socfpga: Fix SOCFPGA build error for Altera dev kit
To fix the build error when build for Altera dev kit, not
virtual target. At same time, set the build for Altera dev
kit as default instead virtual target. With that, U-Boot
is booting well and SPL still lack of few drivers.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2014-08-29 15:50:54 -04:00
Pavel Machek
51fb455f82 socfpga: fix clock manager register definition
Structure defining clock manager hardware was wrong, leading to
wrong registers being accessed and hang in MMC init.

This fixes structure to match hardware.

Signed-off-by: Pavel Machek <pavel@denx.de>
2014-08-29 15:50:50 -04:00
Christian Riesch
db993fc8ec arm: include config.h in arch/arm/lib/vectors.S
config.h is required for CONFIG_SYS_DV_NOR_BOOT_CFG.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
2014-08-29 15:50:43 -04:00
Jeroen Hofstee
8863aa5c98 ARM:asm:io.h use static inline
When compiling u-boot with W=1 the extern inline void for
read* is likely causing the most noise. gcc / clang will
warn there is never a actual declaration for these functions.
Instead of declaring these extern make them static inline so
it is actually declared.

cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-08-29 15:50:43 -04:00
Tom Rini
6defdc0b55 Merge branch 'master' of git://git.denx.de/u-boot-ti 2014-08-29 13:47:42 -04:00
Tom Rini
7f14fb20f8 Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze 2014-08-29 11:07:35 -04:00
Tom Rini
5ddc329341 Merge branch 'master' of git://git.denx.de/u-boot-tegra 2014-08-29 11:07:10 -04:00
Tom Rini
5a1095a830 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-08-29 11:06:51 -04:00
Tom Rini
6af857c50d Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2014-08-29 11:06:26 -04:00
Tom Rini
3e1b36bd58 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-08-28 13:03:25 -04:00
Lokesh Vutla
7b92252370 ARM: DRA: Enable VTT regulator
DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination
and this is controlled by gpio7_11. Configuring gpio7_11.
The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards,
and left unused on previous boards, so it is safe enough to enable gpio
on all DRA7 boards.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-25 10:48:13 -04:00
Sricharan R
f2a1b93b5c ARM: DRA7: Enable software leveling for dra7
Currently hw leveling is enabled by default on DRA7/72.
But the hardware team suggested to use sw leveling as hw leveling
is not characterized and seen some test case failures.
So enabling sw leveling on all DRA7 platforms.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-25 10:48:13 -04:00
Vitaly Andrianov
61f66fd5a8 keystone2: use EFUSE_BOOTROM information to configure PLLs
This patch reads EFUSE_BOOTROM register to see the maximum supported
clock for CORE and TETRIS PLLs and configure them accordingly.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-08-25 10:48:12 -04:00
pekon gupta
9352697aa0 board/ti/dra7xx: add support for parallel NOR
This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM.
The Flash device is connected to GPMC controller on chip-select[0] and accessed
as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and
is CFI compatible.

As multiple devices are share GPMC pins on this board, so following board
settings are required to detect NOR device:
     SW5.1 (NAND_BOOTn) = OFF (logic-1)
     SW5.2 (NOR_BOOTn)  = ON  (logic-0) /* Active-low */
     SW5.3 (eMMC_BOOTn) = OFF (logic-1)
     SW5.4 (QSPI_BOOTn) = OFF (logic-1)

And also set appropriate SYSBOOT configurations:
     SW3.1 (SYSBOOT[ 8])= ON  (logic-1) /* selects SYS_CLK1 speed */
     SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */
     SW3.3 (SYSBOOT[10])= ON  (logic-1) /* wait-pin monitoring = enabled */
     SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */
     SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */
     SW3.6 (SYSBOOT[13])= ON  (logic-1) /* device bus-width: 1(x16) */
     SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */
     SW3.8 (SYSBOOT[15])= ON  (logic-1) /* reserved */

Also, following changes are required to enable NOR Flash support in
dra7xx_evm board profile:
2014-08-25 10:48:12 -04:00
Masahiro Yamada
62d636aa2a omap: remove omap5912osk board support
Emails to the board maintainer
"Rishi Bhattacharya <rishi@ti.com>"
have been bouncing.

Tom suggested to remove this board.

Remove also omap1510_udc.c because this is the last board
to enable it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suggested-by: Tom Rini <trini@ti.com>
2014-08-21 12:01:12 -04:00
Fabio Estevam
d145878d59 mx6sxsabresd: Add Ethernet support
mx6sxsabresd board has 2 FEC ports, each one connected to a AR8031.

Add support for one FEC port initially.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20 13:15:23 +02:00
Fabio Estevam
5c045cddaa mx6sx: Adjust enable_fec_anatop_clock() for mx6solox
Configure and enable the ethernet clock for mx6solox.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20 13:14:09 +02:00
Fabio Estevam
080d72f233 mx6sxsabresd: Convert to the new Kconfig style
mx6sxsabresd was not in the master branch when the conversion to the new Kconfig
style happened, so convert it now so that it can build again.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20 13:11:12 +02:00
Marek Vasut
b299ab7435 ARM: mx6: Handle the MMDCx_MDCTL COL field caprices
The COL field value cannot be easily calculated from the desired
column number. Instead, there are special cases for that, see the
datasheet, MMDCx_MDCTL field description, field COL . Cater for
those special cases.

Signed-off-by: Marek Vasut <marex@denx.de>
2014-08-20 12:22:52 +02:00
Marek Vasut
fcfdfdd58c ARM: mx6: Prevent overflow in DRAM size detection
The MX6 DRAM controller can be configured to handle 4GiB of DRAM, but
only 3840 MiB of that can be really used. In case the controller is
configured to operate a 4GiB module, the imx_ddr_size() function will
correctly compute that there is 4GiB of DRAM in the system. Firstly,
the return value is 32-bit, so the function will effectively return
zero. Secondly, the MX6 cannot address the full 4GiB, but only 3840MiB
of all that. Thus, clamp the returned size to 3840MiB in such case.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20 12:21:57 +02:00
Marek Vasut
68968901e7 ARM: mx5: Fix CHSCCDR name
Fix the name of the CCM CHSCCDR register.

Signed-off-by: Marek Vasut <marex@denx.de>
2014-08-20 12:19:20 +02:00
Gabriel Huau
a76df70908 mx6: add support of multi-processor command
This allows u-boot to load different OS or Bare Metal application on
different cores of the i.MX6 SoC.
For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1.

Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-08-20 11:52:54 +02:00
Michal Simek
ae2ee77f98 ARM: zynq: Remove spl.h
Do not specify own zynq specific SPL macros
because there is no need for that.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-19 08:48:18 +02:00
Michal Simek
dbc31f6a20 ARM: zynq: Move ps7_init() out of spl.h
Prepare for spl.h removal.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-19 08:48:00 +02:00
Stefan Agner
24d4d422c1 ARM: tegra: add Colibri T30 board support
This adds board support for the Toradex Colibri T30 module.

Working functions:
- SD card boot
- eMMC environment and boot
- USB host/USB client (on the dual role port)
- Network (via ASIX USB)

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-08-18 16:59:04 -07:00
Stephen Warren
aeb3fcb359 ARM: tegra: Use mem size from MC rather than ODMDATA
In at least Tegra124, the Tegra memory controller (MC) has a register
that controls the memory size. Read this to determine the memory size
rather than requiring this to be redundantly encoded into the ODMDATA.
This way, changes to the BCT (i.e. MC configuration) automatically
updated SW's view of the memory size, without requiring manual changes
to the ODMDATA.

Future work potentially required:
* Clip the memory size to architectural limits; U-Boot probably doesn't
  and won't support either LPAE or Tegra's "swiss cheese" memory layout,
  at least one of which would be required for >2GB RAM.
* Subtract out any carveout required by firmware on future SoCs.

Based-on-work-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-08-18 16:57:03 -07:00
Bryan Wu
df3443dfa4 ARM: tegra: Disable VPR
On Tegra114 and Tegra124 platforms, certain display-related registers cannot
be accessed unless the VPR registers are programmed.  For bootloader, we
probably don't care about VPR, so we disable it (which counts as programming
it, and allows those display-related registers to be accessed).

This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c
in Chromium OS U-Boot project.

Signed-off-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Signed-off-by: Bryan Wu <pengw@nvidia.com>
[acourbot: ensure write went through, vpr.c style changes]
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <TWarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-08-18 16:57:02 -07:00
Stefano Babic
7e9291720d Update aristainetos board to Kconfig
aristainetos board was merged in u-boot-imx before
Kconfig was integrated, but it is not yet
mainline.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
2014-08-13 09:30:41 +02:00
Siarhei Siamashka
bf4ca384ad sunxi: dram: Autodetect DDR3 bus width and density
In the case if the 'dram_para' struct does not specify the exact bus
width or chip density, just use a trial and error method to find a
usable configuration.

Because all the major bugs in the DRAM initialization sequence are
now hopefully fixed, it should be safe to re-initialize the DRAM
controller multiple times until we get it configured right. The
original Allwinner's boot0 bootloader also used a similar
autodetection trick.

The DDR3 spec contains the package pinout and addressing table for
different possible chip densities. It appears to be impossible to
distinguish between a single chip with 16 I/O data lines and a pair
of chips with 8 I/O data lines in the case if they provide the same
storage capacity. Because a single 16-bit chip has a higher density
than a pair of equivalent 8-bit chips, it has stricter refresh timings.
So in the case of doubt, we assume that 16-bit chips are used.
Additionally, only Allwinner A20 has all A0-A15 address lines and
can support densities up to 8192. The older Allwinner A10 and
Allwinner A13 can only support densities up to 4096.

We deliberately leave out DDR2, dual-rank configurations and the
special case of a 8-bit chip with density 8192. None of these
configurations seem to have been ever used in real devices. And no
new devices are likely to use these exotic configurations (because
only up to 2GB of RAM can be populated in any case).

This DRAM autodetection feature potentially allows to have a single
low performance fail-safe DDR3 initialiazation for a universal single
bootloader binary, which can be compatible with all Allwinner
A10/A13/A20 based devices (if the ifdefs are replaced with a runtime
SoC type detection).

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:34 +02:00
Siarhei Siamashka
935758b1d5 sunxi: dram: Derive write recovery delay from DRAM clock speed
The write recovery time is 15ns for all JEDEC DDR3 speed bins. And
instead of hardcoding it to 10 cycles, it is possible to set tighter
timings based on accurate calculations. For example, DRAM clock
frequencies up to 533MHz need only 8 cycles for write recovery.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
b5c71f5f9c sunxi: dram: Drop DDR2 support and assume only single rank DDR3 memory
All the known Allwinner A10/A13/A20 devices are using just single rank
DDR3 memory. So don't pretend that we support DDR2 or more than one
rank, because nobody could ever test these configurations for real and
they are likely broken. Support for these features can be added back
in the case if such hardware actually exists.

As part of this code cleanup, also replace division by 1024 with
division by 1000 for the refresh timing calculations. This allows
to use the original non-skewed tRFC timing table from the DRR3 spec
and make code less confusing.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
d755a5fb20 sunxi: dram: Configurable DQS gating window mode and delay
The hardware DQS gate training is a bit unreliable and does not
always find the best delay settings.

So we introduce a 32-bit 'dqs_gating_delay' variable, where each
byte encodes the DQS gating delay for each byte lane. The delay
granularity is 1/4 cycle.

Also we allow to enable the active DQS gating window mode, which
works better than the passive mode in practice. The DDR3 spec
says that there is a 0.9 cycles preamble and 0.3 cycle postamble.
The DQS window has to be opened during preamble and closed during
postamble. In the passive window mode, the gating window is opened
and closed by just using the gating delay settings. And because
of the 1/4 cycle delay granularity, accurately hitting the 0.3
cycle long postamble is a bit tough. In the active window mode,
the gating window is auto-closing with the help of monitoring
the DQS line, which relaxes the gating delay accuracy requirements.

But the hardware DQS gate training is still performed in the passive
window mode. It is a more strict test, which is reducing the results
variance compared to the training with active window mode.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
e044daa33e sunxi: dram: Add a helper function 'mctl_get_number_of_lanes'
It is going to be useful in more than one place.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
b8f7cb6ae3 sunxi: dram: Improve DQS gate data training error handling
The stale error status should be cleared for all sun4i/sun5i/sun7i
hardware and not just for sun7i. Also there are two types of DQS
gate training errors ("found no result" and "found more than one
possible result"). Both are handled now.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
013f2d7469 sunxi: dram: Use divisor P=1 for PLL5
This configures the PLL5P clock frequency to something in the ballpark
of 1GHz and allows more choices for MBUS and G2D clock frequency
selection (using their own divisors). In particular, it enables the use
of 2/3 clock speed ratio between MBUS and DRAM.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
1a9717cbb3 sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6)
The sun5i hardware (Allwinner A13) introduced configurable MBUS clock
speed. Allwinner A13 uses only 16-bit data bus width to connect the
external DRAM, which is halved compared to the 32-bit data bus of sun4i
(Allwinner A10), so it does not make much sense to clock a wider
internal bus at a very high speed. The Allwinner A13 manual specifies
300 MHz MBUS clock speed limit and 533 MHz DRAM clock speed limit. Newer
sun7i hardware (Allwinner A20) has a full width 32-bit external memory
interface again, but still keeps the MBUS clock speed configurable.
Clocking MBUS too low inhibits memory performance and one has to find
the optimal MBUS/DRAM clock speed ratio, which may depend on many
factors:
    http://linux-sunxi.org/A10_DRAM_Controller_Performance

This patch introduces a new 'mbus_clock' parameter for the 'dram_para'
struct and uses it as a desired MBUS clock speed target. If 'mbus_clock'
is not set, 300 MHz is used by default to match the older hardcoded
settings.

PLL5P and PLL6 are both evaluated as possible clock sources. Preferring
the one, which can provide higher clock frequency that is lower or
equal to the 'mbus_clock' target. In the case of a tie, PLL5P has
higher priority.

Attempting to set the MBUS clock speed has no effect on sun4i, but does
no harm either.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
5c18384dea sunxi: dram: Re-introduce the impedance calibration ond ODT
The DRAM controller allows to configure impedance either by using the
calibration against an external high precision 240 ohm resistor, or
by skipping the calibration and loading pre-defined data. The DRAM
controller register guide is available here:

    http://linux-sunxi.org/A10_DRAM_Controller_Register_Guide#SDR_ZQCR0

The new code supports both of the impedance configuration modes:
   - If the higher bits of the 'zq' parameter in the 'dram_para' struct
     are zero, then the lowest 8 bits are used as the ZPROG value, where
     two divisors encoded in lower and higher 4 bits. One divisor is
     used for calibrating the termination impedance, and another is used
     for the output impedance.
   - If bits 27:8 in the 'zq' parameters are non-zero, then they are
     used as the pre-defined ZDATA value instead of performing the ZQ
     calibration.

Two lowest bits in the 'odt_en' parameter enable ODT for the DQ and DQS
lines individually. Enabling ODT for both DQ and DQS means that the
'odt_en' parameter needs to be set to 3.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
94cd301988 sunxi: dram: Add 'await_bits_clear'/'await_bits_set' helper functions
The old 'await_completion' function is not sufficient, because
in some cases we want to wait for bits to be cleared, and in the
other cases we want to wait for bits to be set. So split the
'await_completion' into two new 'await_bits_clear' and
'await_bits_set' functions.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
cfc89b003b sunxi: dram: Do DDR3 reset in the same way on sun4i/sun5i/sun7i
The older differences were likely justified by the need to mitigate
the CKE delay timing violations on sun4i/sun5i. The CKE problem is
already resolved, so now we can use the sun7i variant of this code
everywhere.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:32 +02:00
Siarhei Siamashka
7e40e1926a sunxi: dram: Remove broken impedance and ODT configuration code
We can safely remove it, because none of the currently supported
boards uses these features.

The existing implementation had multiple problems:
   - unnecessary code duplication between sun4i/sun5i/sun7i
   - ZQ calibration was never initiated explicitly, and could be
     only triggered by setting the highest bit in the 'zq' parameter
     in the 'dram_para' struct (this was never actually done for
     any of the known Allwinner devices).
   - even if the ZQ calibration could be started, no attempts were
     made to wait for its completion, or checking whether the
     default automatically initiated ZQ calibration is still
     in progress
   - ODT was only ever enabled on sun4i, but not on sun5i/sun7i

Additionally, SDR_IOCR was set to 0x00cc0000 only on sun4i. There
are some hints in the Rockchip Linux kernel sources, indicating
that these bits are related to the automatic I/O power down
feature, which is poorly understood on sunxi hardware at the
moment. Avoiding to set these bits on sun4i too does not seem to
have any measurable/visible impact.

The impedance and ODT configuration code will be re-introdeced in
one of the next comits.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:32 +02:00
Siarhei Siamashka
f8e88b6837 sunxi: dram: Fix CKE delay handling for sun4i/sun5i
Before driving the CKE pin (Clock Enable) high, the DDR3 spec requires
to wait for additional 500 us after the RESET pin is de-asserted.

The DRAM controller takes care of this delay by itself, using a
configurable counter in the SDR_IDCR register. This works in the same
way on sun4i/sun5i/sun7i hardware (even the default register value
0x00c80064 is identical). Except that the counter is ticking a bit
slower on sun7i (3 DRAM clock cycles instead of 2), resulting in
longer actual delays for the same settings.

This patch configures the SDR_IDCR register for all sun4i/sun5i/sun7i
SoC variants and not just for sun7i alone. Also an explicit udelay(500)
is added immediately after DDR3 reset for extra safety. This is a
duplicated functionality. But since we don't have perfect documentation,
it may be reasonable to play safe. Half a millisecond boot time increase
is not that significant. Boot time can be always optimized later.
Preferebly by the people, who have the hardware equipment to check the
actual signals on the RESET and CKE lines and verify all the timings.

The old code did not configure the SDR_IDCR register for sun4i/sun5i,
but performed the DDR3 reset very early for sun4i/sun5i. This resulted
in a larger time gap between the DDR3 reset and the DDR3 initialization
steps and reduced the chances of CKE delay timing violation to cause
real troubles.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:32 +02:00
Siarhei Siamashka
e626d2d446 sunxi: dram: Respect the DDR3 reset timing requirements
The RESET pin needs to be kept low for at least 200 us according
to the DDR3 spec. So just do it the right way.

This issue did not cause any visible major problems earlier, because
the DRAM RESET pin is usually already low after the board reset. And
the time gap before reaching the sunxi u-boot DRAM initialization
code appeared to be sufficient.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:32 +02:00
Siarhei Siamashka
f257796773 sunxi: dram: Remove broken super-standby remnants
If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1,
this means that DRAM is currently in self-refresh mode and retaining the
old data. Since we have no idea what to do in this situation yet, just
set this register to 0 and initialize DRAM in the same way as on any
normal reboot (discarding whatever was stored there).

This part of code was apparently used by the Allwinner boot0 bootloader
to handle resume from the so-called super-standby mode. But this
particular code got somehow mangled on the way from the boot0 bootloader
to the u-boot-sunxi bootloader and has no chance of doing anything even
remotely sane. For example:
1. in the original boot0 code we had "mctl_write_w(SDR_DPCR,
   0x16510000)" (write to the register) and in the u-boot it now looks
   like "setbits_le32(&dram->ppwrsctl, 0x16510000)" (set bits in the
   register)
2. in the original boot0 code it was issuing three commands "0x12, 0x17,
   0x13" (Self-Refresh entry, Self-Refresh exit, Refresh), but in the
   u-boot they have become "0x12, 0x12, 0x13" (Self-Refresh entry,
   Self-Refresh entry, Refresh)

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:32 +02:00
Siarhei Siamashka
34759d74a3 sunxi: dram: Remove useless 'dramc_scan_dll_para()' function
The attempt to do DRAM parameters calibration in 'dramc_scan_dll_para()'
function by trying different DLL adjustments and using the hardware
DQS gate training result as a feedback is a great source of inspiration,
but it just can't work properly the way it is implemented now. The fatal
problem of this implementation is that the DQS gating window can be
successfully found for almost every DLL delay adjustment setup that
gets tried. Thus making it unable to see any real difference between
'good' and 'bad' settings.

Also this code was supposed to be only activated by setting the highest
bit in the 'dram_tpr3' variable of the 'dram_para' struct (per-board
dram configuration). But none of the linux-sunxi devices has ever used
it for real. Basically, this code is just a dead weight.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:32 +02:00
Stefano Babic
e82abaeb7f Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
	boards.cfg

Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-08-11 10:21:03 +02:00
maxin.john@enea.com
194c1ed400 emif.h: remove duplicated argument to |
Remove the duplicated argument to | in two places. Reported
by Coccinelle (http://coccinelle.lip6.fr/).

Signed-off-by: Maxin B. John <maxin.john@enea.com>
2014-08-09 11:17:03 -04:00
Albert ARIBAUD
1899fac925 Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master' 2014-08-09 16:48:34 +02:00
Peter Crosthwaite
fb8d876698 zynq: spl: Add vectors section to linker script
The vectors section contains the _start symbol which is used as the
program entry point. Add it to the linker script in same fashion as done
for regular u-boot. This allows for correct generation of an spl elf
with a non-zero entry point.

A similar change was applied to sunxi platform in
"sunxi: Fix u-boot-spl.lds to refer to .vectors"
(sha1: 9e5f80d823)

This also allows for placement of the vector table at the hivecs
location by setting the TEXT_BASE to 0xffff0000.

Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-08-08 11:27:29 +02:00
Fabio Estevam
9cd744ff11 mx6: crm_regs: Fix MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED
According to the Reference Manual the 'mask_periph2_clk_sel_loaded' field of
register CCM_CIMR corresponds to bit 19 so fix its definition accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-08 10:29:40 +02:00
Fabio Estevam
326454a88d mx6: crm_regs: Fix MXC_CCM_CLPCR_WB_PER_AT_LPM definition
According to the Reference Manual the 'wb_per_at_lpm' field of register
CCM_CLPCR corresponds to bit 16 so fix its definition accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-08 10:29:40 +02:00
Fabio Estevam
338c9da605 mx6: crm_regs: Fix CDCDR_SPDIF0_CLK_PODF mask and offset
According to the Reference Manual the 'spdif0_clk_podf' field of register
CCM_CDCDR corresponds to bits 22, 23 and 24, so fix the mask and offset
definitions accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-08 10:29:40 +02:00
Fabio Estevam
2834490245 mx6: imx-regs: Remove unused 'omux' field from iomux struct
'omux' field is not used anywhere and such layout is not valid for mx6solox.

Instead of adding more ifdef's into the structure, let's simply remove this
unused 'omux' field.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-08-08 10:29:39 +02:00
Stefano Babic
c23154aab5 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-08-08 10:18:40 +02:00
Tom Rini
aa159e681e Merge http://git.denx.de/u-boot-dm 2014-08-04 10:16:27 -04:00
Simon Glass
76a1e584e1 arm: Support pre-relocation malloc()
Add support for re-relocation malloc() in arm's start-up code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-04 05:24:35 -06:00
Simon Glass
aae2aef9c8 arm: Set up global data before board_init_f()
At present arm defines CONFIG_SYS_GENERIC_GLOBAL_DATA, meaning that
the global_data pointer is set up in board_init_f(). However it is
actually set up before this, it just isn't zeroed.

If we zero the global data before calling board_init_f() then we
don't need to define CONFIG_SYS_GENERIC_GLOBAL_DATA.

Make this change (on arm32 only) to simplify the init process. I
don't have the ability to test aarch64 yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Tom Rini <trini@ti.com>
2014-08-04 05:23:59 -06:00
Marek Vasut
dae0f5c644 mmc: s3c: Add SD driver
Implement SD driver for the S3C24xx family. This implementation
is currently only capable of using the PIO transfers, DMA is not
supported.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-08-01 19:24:34 +03:00