Commit graph

622 commits

Author SHA1 Message Date
Tom Rini
17059f972f Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-04-15 07:46:11 -04:00
Albert ARIBAUD
1812201997 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	drivers/video/exynos_fb.c
2013-04-12 22:07:57 +02:00
Stefan Roese
e303be2d28 Revert "mtd: cfi_flash: Fix CFI flash driver for 8-bit bus support"
This reverts commit 239cb9d904.

Signed-off-by: Stefan Roese <sr@denx.de>
2013-04-12 19:04:54 +02:00
Stefan Roese
b9589ec1a3 Revert "cfi_flash: Use uintptr_t for casts from u32 to void *"
This reverts commit 81a4f7098b.

Signed-off-by: Stefan Roese <sr@denx.de>
2013-04-12 19:04:37 +02:00
Gerlando Falauto
7070b550be kirkwood_nand: allow usage of NAND_ECC_SOFT_BCH
If CONFIG_NAND_ECC_BCH is set use 4-bit error correction code instead of
the 1-bit error correction code on the NAND device.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Scott Wood <scottwood@freescale.com>
2013-04-12 21:42:01 +05:30
Benoît Thébaudeau
e53232250b arm: Remove support for unused s3c64xx
Following the removal of the smdk6400 board, the s3c64xx SoC becomes unused, so
remove associated code. It will still be possible to restore it later from the
Git history if necessary.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:08 +02:00
Benoît Thébaudeau
da962b7175 nand: mxc: Switch NAND SPL to generic SPL
This also fixes support for mx31pdk and tx25, which had been broken by commit
e05e5de7fa.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-12 07:55:07 +02:00
Benoît Thébaudeau
3ec9d6eb09 nand: mxc: Use appropriate page number in syndrome functions
The syndrome functions should use the page number passed as argument instead of
the page number saved upon NAND_CMD_READ0.

This does not make any difference if the NAND_NO_AUTOINCR option is set, but
otherwise this fixes accesses to the wrong pages.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Scott Wood <scottwood@freescale.com>
2013-04-12 07:55:05 +02:00
Benoît Thébaudeau
78ee7b1729 nand: mxc: Fix debug trace in mxc_nand_read_oob_syndrome()
The page number indicated in the debug trace of mxc_nand_read_oob_syndrome() did
not match the page being worked on.

By the way, replace the GCC-specific __FUNCTION__ with __func__.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Scott Wood <scottwood@freescale.com>
2013-04-12 07:55:04 +02:00
Benoît Thébaudeau
35537bc773 nand: mxc: Add support for i.MX5
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-12 07:55:04 +02:00
Benoît Thébaudeau
2dc0aa0227 nand: mxc: Prepare to add support for i.MX5
Add some abstraction to NFC definitions so that some parts of the current code
can also be used for future i.MX5 code.

Clean up a few things by the way.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-12 07:55:04 +02:00
Fabio Estevam
a430e91643 mtd: nand: mxc_nand: Fix is_16bit_nand()
Currently is_16bit_nand() is a per SoC function and it decides the bus nand
width by reading some boot related registers.

This method works when NAND is the boot medium, but does not work if another
boot medium is used. For example: booting from a SD card and then using NAND
to store the environment variables, would lead to the following error:

NAND bus width 16 instead 8 bit
No NAND device found!!!
0 MiB

Use CONFIG_SYS_NAND_BUSWIDTH_16BIT symbol to decide the bus width.

If it is defined in the board file, then consider 16-bit NAND bus-width,
otherwise assume 8-bit NAND is used.

This also aligns with Documentation/devicetree/bindings/mtd/nand.txt, which
states:

nand-bus-width : 8 or 16 bus width if not present 8

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:03 +02:00
Fabio Estevam
66bd1846ef mtd: nand: Introduce CONFIG_SYS_NAND_BUSWIDTH_16BIT
Introduce CONFIG_SYS_NAND_BUSWIDTH_16BIT option so that other NAND controller
drivers could use it when a 16-bit NAND is deployed.

drivers/mtd/nand/ndfc has CONFIG_SYS_NDFC_16BIT, so just rename it, so that
other NAND drivers could reuse the same symbol.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:03 +02:00
Joe Hershberger
147162dac6 ubi: ubifs: Turn off verbose prints
The prints are out of control.  SILENCE!

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2013-04-11 15:52:54 -04:00
Joe Hershberger
76c1637e95 ubi: Fix broken cleanup code in attach_by_scanning
The unwind code was not reversing operations correctly and was causing
a hang on any error condition.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2013-04-11 15:52:54 -04:00
Tom Rini
c39d6a0ea5 nand: Extend nand_(read|write)_skip_bad with *actual and limit parameters
We make these two functions take a size_t pointer to how much space
was used on NAND to read or write the buffer (when reads/writes happen)
so that bad blocks can be accounted for.  We also make them take an
loff_t limit on how much data can be read or written.  This means that
we can now catch the case of when writing to a partition would exceed
the partition size due to bad blocks.  To do this we also need to make
check_skip_len count not just complete blocks used but partial ones as
well.  All callers of nand_(read|write)_skip_bad are adjusted to call
these with the most sensible limits available.

The changes were started by Pantelis and finished by Tom.

Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Tom Rini <trini@ti.com>
2013-04-10 15:22:22 +02:00
Andreas Bießmann
4a0930069b omap_gpmc: add support for hw assisted BCH8
The kernel states:

---8<---
The OMAP3 GPMC hardware BCH engine computes remainder polynomials, it does not
provide automatic error location and correction: this step is implemented using
the BCH library.
--->8---

And we do so in u-boot.

This implementation uses the same layout for BCH8 but it is fix. The current
provided layout does only work with 64 Byte OOB.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Ilya Yanok <ilya.yanok@cogentembedded.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Mansoor Ahamed <mansoor.ahamed@ti.com>
Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
2013-04-08 11:29:05 -04:00
Andreas Bießmann
da634ae356 omap_gpmc: change nandecc command
With uppcoming BCH support on OMAP devices we need to decide between differnt
algorithms when switching the ECC engine.  Currently we support 1-bit hammign
and 8-bit BCH on HW backend.

In order to switch between differnet ECC algorithms we need to change the
interface of omap_nand_switch_ecc() also.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
2013-04-08 11:29:05 -04:00
Andreas Bießmann
5bf299bc4f asm/omap_gpmc.h: consolidate common defines
arch/arm/include/asm/arch-am33xx/omap_gpmc.h and
arch/arm/include/asm/arch-omap3/omap_gpmc.h are almost the same, consolidate
the common parts into a new header.

Introduce a new asm/omap_gpmc.h which defines the command part and pulls in
the architecture specific one.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-08 11:29:05 -04:00
Tom Rini
bc5fd908d9 Merge branch 'master' of git://www.denx.de/git/u-boot-cfi-flash 2013-04-04 12:01:27 -04:00
Stefan Roese
81a4f7098b cfi_flash: Use uintptr_t for casts from u32 to void *
This fixes this build warning:

Configuring for qemu_mips64 - Board: qemu-mips64, Options: SYS_BIG_ENDIAN
   text    data     bss     dec     hex filename
 215344   13082  218720  447146   6d2aa qemu_mips64/u-boot
cfi_flash.c: In function 'flash_map':
cfi_flash.c:217:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
2013-04-04 07:07:30 +02:00
Jagannadha Sutradharudu Teki
c502321c4a mtd: cfi_flash: Write buffer size adjustment for M29EW Numonyx devices
This patch addjusted the write buffer size for M29EW devices those
are operated in 8-bit mode.

The M29EW devices seem to report the CFI information wrong when
it's in 8 bit mode.

There's an app note from Numonyx on this issue and there's a patch
in the open source as well for Linux, but it doesn't seem to be in mainline.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-04-02 14:27:54 +02:00
aaron.williams@caviumnetworks.com
239cb9d904 mtd: cfi_flash: Fix CFI flash driver for 8-bit bus support
This commit is based on that patch from aaron.williams@caviumnetworks.com
with same commit title. pulled the same code changes into current u-boot tree.

http://patchwork.ozlabs.org/patch/140863/
http://lists.denx.de/pipermail/u-boot/2011-April/089606.html

This patch corrects the addresses used when working with Spansion/AMD FLASH chips.
Addressing for 8 and 16 bits is almost identical except in the 16-bit case the
LSB of the address is always 0.  The confusion arose because the addresses
in the datasheet for 16-bit mode are word addresses but this code assumed it was
byte addresses.

I have only been able to test this on our Octeon boards which use either an 8-bit
or 16-bit bus.  I have not tested the case where there's an 8-bit part on a 16-bit
bus.

This patch also adds some delays as suggested by Spansion.

If a part can be both 8 and 16-bits, it forces it to work in 8-bit mode if an
8-bit bus is detected.

Apart from the pulled changes, fixed few minor code cleanups and tested
on 256M29EW, 512M29EW flashes.

Before this fix:
---------------
Bank # 1: CFI conformant flash (8 x 8)  Size: 64 MB in 512 Sectors
  AMD Standard command set, Manufacturer ID: 0xFF, Device ID: 0xFF
  Erase timeout: 4096 ms, write timeout: 2 ms
  Buffer write timeout: 5 ms, buffer size: 1024 bytes

After this fix:
--------------
Bank # 1: CFI conformant flash (8 x 8)  Size: 64 MB in 512 Sectors
  AMD Standard command set, Manufacturer ID: 0x89, Device ID: 0x7E2301
  Erase timeout: 4096 ms, write timeout: 2 ms
  Buffer write timeout: 5 ms, buffer size: 1024 bytes

Signed-off-by: Aaron Williams <aaron.williams@caviumnetworks.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-04-02 14:27:45 +02:00
York Sun
472d546054 Consolidate bool type
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.

All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.

Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-04-01 16:33:52 -04:00
Albert ARIBAUD
009d75ccc1 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	drivers/spi/tegra20_sflash.c
	include/fdtdec.h
	lib/fdtdec.c
2013-03-28 18:50:01 +01:00
Allen Martin
772ba15474 sf: winbond: add W25Q32DW
Add support for Winbond W25Q32DW 32Mbit part

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:06 -07:00
Tom Rini
98f92001b3 am33xx: Add required includes to some omap/am33xx code
- In arch/arm/cpu/armv7/omap-common/timer.c,
  drivers/mtd/nand/omap_gpmc.c and drivers/net/cpsw.c add #include files
  that the driver needs but had been relying on <config.h> to bring in.
- In arch/arm/cpu/armv7/omap-common/lowlevel_init.S add <config.h>
- In am335x_evm.h and pcm051.h don't globally include
  <asm/arch/hardware.h> and <asm/arch/cpu.h> but just <asm/arch/omap.h>
  as that is the only include which defines things the config uses.

Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Tom Rini <trini@ti.com>
2013-03-24 12:49:11 -04:00
Simon Glass
bb8215f437 sf: Enable FDT-based configuration and memory mapping
Enable device tree control of SPI flash, and use this to implement
memory-mapped SPI flash, which is supported on Intel chips.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19 08:45:37 -07:00
Simon Glass
1e566bc6db sf: Respect maximum SPI write size
Some SPI flash controllers (e.g. Intel ICH) have a limit on the number of
bytes that can be in a write transaction. Support this by breaking the
writes into multiple transactions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19 08:45:37 -07:00
Simon Glass
c0f87dd4ff sf: Use spi_flash_alloc() in each SPI flash driver
Rather than each device having its own way to allocate a SPI flash
structure, use the new allocation function everywhere. This will make it
easier to extend the interface without breaking devices.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19 08:45:36 -07:00
Simon Glass
b5aec1424d sf: Add spi_flash_alloc() to create a new SPI flash struct
At present it is difficult to extend the SPI flash structure since
all devices allocate it themselves, and few of them zero all fields.
Add a new function spi_flash_alloc() which can be used by SPI devices
to perform this allocation, and thus ensure that all devices can
better cope with SPI structure changes.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19 08:45:36 -07:00
Tom Rini
76b40ab41e Merge u-boot/master into u-boot-ti/master
In master we had already taken a patch to fix the davinci GPIO code for
CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support
DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850).  Resolve these
conflicts manually and comment the #else/#endif lines for clarity.

Conflicts:
	arch/arm/include/asm/arch-davinci/gpio.h
	drivers/gpio/da8xx_gpio.c

Signed-off-by: Tom Rini <trini@ti.com>
2013-03-11 12:16:13 -04:00
Enric Balletbo i Serra
f99613782a SPL: ONENAND: Fix onenand_spl_load_image implementation.
Tested with an IGEPv2 board seems that current onenand_spl_load_image implementation
doesn't work. This patch fixes this function changing the read loop and reading the
onenand blocks from page to page.

Tested with various IGEP based boards with a OneNAND from Numonyx.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
2013-03-08 16:41:14 -05:00
Joe Hershberger
fcecb4a52c mtd: nand: Check if NAND is locked tight before lock cmds
If the NAND is locked tight, commands such as lock and unlock will not
work, but the NAND chip may not report an error.  Check the lock tight
status before attempting such operations so that an error status can be
reported if we know the operation will not succeed.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2013-02-22 19:06:34 -06:00
Holger Brunck
938187329a kmeter1_nand: allow uasge of NAND_ECC_SOFT_BCH
If CONFIG_NAND_ECC_BCH is set we use 4-bit error corretion code
instead of the 1-bit error correction code on the NAND device
within this driver.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Scott Wood <scottwood@freescale.com>
2013-02-15 17:47:20 -06:00
Jagannadha Sutradharudu Teki
d62ef5619c sf: stmicro: Add support for N25Q256A
Add support for Numonyx N25Q256A SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-06 10:10:00 -05:00
Jagannadha Sutradharudu Teki
b1431dac32 sf: stmicro: Add support for N25Q32A
Add support for Numonyx N25Q32A SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-06 10:10:00 -05:00
Jagannadha Sutradharudu Teki
c75c92122f sf: stmicro: Add support for N25Q32
Add support for Numonyx N25Q32 SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-06 10:10:00 -05:00
Jagannadha Sutradharudu Teki
f785fcb631 sf: stmicro: Add support for N25Q64A
Add support for Numonyx N25Q64A SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-06 10:10:00 -05:00
Jagannadha Sutradharudu Teki
5818a09d70 sf: winbond: Add W25Q64W
Add support for Winbond's W25Q64W SPI flash.
This device is used on xilinx zynq emulation platform.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-06 10:10:00 -05:00
Jagannadha Sutradharudu Teki
4e994c168f sf: spansion: Correct the first byte of idcode1 for S25FL256S part
This patch corrected the first byte of idcode1 for S25FL256S SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-06 10:10:00 -05:00
Jagannadha Sutradharudu Teki
3981d02e0b sf: stmicro: add support for N25Q064
Add support for Numonyx N25Q064 SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-02-04 09:14:21 -05:00
Stefan Roese
d2af028db3 cfi_flash: Report Advanced Sector Protection (PPB) with flinfo cmd
Report the usage of the Advanced Sector Protection (PPB) to the user
upon 'flinfo' command. E.g:

Bank # 1: CFI conformant flash (16 x 16)  Size: 64 MB in 512 Sectors
  AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E2301
  Advanced Sector Protection (PPB) enabled
  Erase timeout: 16384 ms, write timeout: 2 ms
  Buffer write timeout: 5 ms, buffer size: 32 bytes

  Sector Start Addresses:
  FC000000 E      FC020000 E RO   FC040000 E      FC060000 E      FC080000 E
  ...

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Holger Brunck <holger.brunck@keymile.com>
Tested-by: Holger Brunck <holger.brunck@keymile.com>
2013-01-10 14:40:00 +01:00
Stefan Roese
ac6b911514 cfi_flash: Enable PPB protection for all AMD cmdset flash chips
Not only Spansion supports the Persistent Protection Bits (PPB) locking.
Other devices like the Micron JS28F512M29EWx also support this type
of locking/unlocking. Detection of support is done in the same way as
done for the Spansion chips - via the 0x49 CFI word.

This patch enables this PPB protection mechanism for all AMD type
(AMD commandset) chips.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Holger Brunck <holger.brunck@keymile.com>
Tested-by: Holger Brunck <holger.brunck@keymile.com>
2013-01-10 14:39:54 +01:00
Stefan Roese
03deff433e cfi_flash: Read PPB sector protection from device for AMD/Spansion chips
Patch 66863b05 [cfi_flash: add support for Spansion flash PPB sector
protection] introduced the PPB (Persistent Protection Bit) locking for
Spansion chips. But right now the sector protection status (locked vs
unlocked) is set to unlocked for all sectors upon bootup. The real
sector protection status is ignored.

This patch now reads the current sector protection status and uses
it for these AMD/Spansion flash chips.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Holger Brunck <holger.brunck@keymile.com>
Tested-by: Holger Brunck <holger.brunck@keymile.com>
2013-01-10 14:39:48 +01:00
Stefan Roese
20043a4c3c cfi_flash: Add manufact_match helper function
Consolidate manufacturer matching into the function manufact_match()
and use it.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Holger Brunck <holger.brunck@keymile.com>
2013-01-10 14:39:30 +01:00
Angelo Dureghello
07b2c5c0e5 mtd/cfi: add support for SST 4KB sector granularity
Add support for SST 4KB sector granularity.

Many recent SST flashes, i.e. SST39VF3201B and similar of this family
are declared CFI-conformant from SST. They support CFI query, but implement
2 different sector sizes in the same memory: a 64KB sector (they call it
"block", std AMD erase cmd=0x30), and a 4KB sector (they call it "sector",
erase cmd=0x50). Also, CFI query on these chips, reading from address 0x2dh
of cfi query struct, detects a number of secotrs for the 4KB granularity
(flinfo shows it).

For all other aspects, they are CFI compliant, so, as Linux do, i think
it's a good idea to handle these chips in the CFI driver, with a fixup
to allow 4KB granularity, as should be expected, instead of 64KB.

Signed-off-by: Angelo Dureghello <sysamfw@gmail.com>
Signed-off-by: Stefan Rose <sr@denx.de>
2013-01-10 14:39:13 +01:00
Albert ARIBAUD
449485948e Fix SPL build for non-ARM targets
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-01-09 06:34:40 -07:00
Tom Rini
91c038f087 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-01-08 14:26:42 -07:00
Albert ARIBAUD
79f3877794 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
This required manual merging drivers/mtd/nand/Makefile
and adding am335x_evm support for CONFIG_SPL_NAND_DRIVERS
2013-01-08 13:15:45 +01:00