Commit graph

1436 commits

Author SHA1 Message Date
Simon Glass
67c4e9f815 common: Move board_get_usable_ram_top() out of common.h
Move this function into init.h which seems to be designed for this sort
of thing. Also update the header to declare struct global_data so that it
can be included without global_data.h being needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:04 -05:00
Simon Glass
36bf446b64 common: Move enable/disable_interrupts out of common.h
Move these two functions into the irq_funcs.h header file. Also move
interrupt_handler_t as this is used by the irq_install_handler() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:01 -05:00
Simon Glass
c30b7adbca common: Move interrupt functions into a new header
These functions do not use driver model but are fairly widely used in
U-Boot. But it is not clear that they will use driver model anytime soon,
so we don't want to label them as 'legacy'.

Move them to a new irq_func.h header file. Avoid the name 'irq.h' since it
is widely used in U-Boot already.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:00 -05:00
Simon Glass
1eb69ae498 common: Move ARM cache operations out of common.h
These functions are CPU-related and do not use driver model. Move them to
cpu_func.h

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:24:58 -05:00
Simon Glass
9edefc2776 common: Move some cache and MMU functions out of common.h
These functions belong in cpu_func.h. Another option would be cache.h
but that code uses driver model and we have not moved these cache
functions to use driver model. Since they are CPU-related it seems
reasonable to put them here.

Move them over.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:55 -05:00
Simon Glass
30c7c43473 common: Move checkcpu() out of common.h
This function belongs in cpu_func.h so move it over.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:14 -05:00
Simon Glass
73c6cd6c0b x86: Quieten TPL's jump_to_image_no_args()
We already a message indicating that U-Boot is about to jump to SPL, so
make this one a debug() to reduce code size.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03 07:20:29 +08:00
Simon Glass
09455d3a8f x86: Don't print CPU info in TPL
We don't need to do this and it is done (in more detail) in U-Boot proper.
Drop this to save code space.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03 07:20:28 +08:00
Simon Glass
0e72ac7150 x86: Move CPU init to before spl_init()
At present we call spl_init() before identifying the CPU. This is not a
good idea - e.g. if bootstage is enabled then it will try to set up the
timer which works better if the CPU is identified.

Put explicit code at each entry pointer to identify the CPU.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03 07:20:28 +08:00
Simon Glass
ece3a46070 x86: Add a CPU init function for TPL
For TPL we only need to set up the features and identify the CPU to a
basic level. Add a function to handle that.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03 07:20:28 +08:00
Simon Glass
0ced70a0bb x86: tpl: Add a fake PCI bus
In TPL we try to minimise code size so do not include the PCI subsystem.
We can use fixed BARs and drivers can directly program the devices that
they need.

However we do need to bind the devices on the PCI bus and without PCI this
does not ordinarily happen. As a work-around, define a fake PCI bus which
does this binding, but no other PCI operations. This is a convenient way
to ensure that we can use the same device tree for TPL, SPL and U-Boot
proper:

   TPL    - CONFIG_TPL_PCI is not set (no auto-config, fake PCI bus)
   SPL    - CONFIG_SPL_PCI is set (no auto-config but with real PCI bus)
   U-Boot - CONFIG_PCI is set (full auto-config after relocation)

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03 07:20:28 +08:00
Simon Glass
c0e2c81d8e x86: spl: Support init of a PUNIT
The x86 power unit handles power management. Support initing this device
which is modelled as a new type of system controller since there are no
operations needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03 07:20:27 +08:00
Simon Glass
a478a26cd0 x86: timer: Use a separate flag for whether timer is inited
At present the value of the timer base is used to determine whether the
timer has been set up or not. It is true that the timer is essentially
never exactly 0 when it is read. However 'time 0' may indicate the time
that the machine was reset so it is useful to be able to denote that.

Update the code to use a separate flag instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03 07:20:27 +08:00
Simon Glass
5e239183f6 binman: x86: Separate out 16-bit reset and init code
At present these two sections of code are linked together into a single
2KB chunk in a single file. Some Intel SoCs like to have a FIT (Firmware
Interface Table) in the ROM and the pointer for this needs to go at
0xffffffc0 which is in the middle of these two sections.

Make use of the new 'reset' entry and change the existing 16-bit entry to
include just the 16-bit data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:02 -06:00
Simon Glass
d362a08817 x86: Reduce resetvec size
At present this produces a 16-byte file. It is intended to start 16 bytes
before the end of ROM and pads with zeroes to readh the end.

But binman sometimes wants to add an image-header at the very end of ROM.
Furthermore binman automatically pads the data if it is finishes early.

Drop the padding in resetvec and let binman handle it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-11 17:37:38 +08:00
Simon Glass
b9e7c3370e x86: Drop RESET_SEG_SIZE
This is not used anywhere now, so drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-11 17:37:34 +08:00
Simon Glass
fd0ef895b6 x86: Drop RESET_BASE
Since x86 users binman now, we don't need this compile-time define.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-11 17:37:29 +08:00
Simon Glass
530bec93d6 x86: Update Kconfig options for FSP1
Many of the Kconfig options do not apply to FSP2. Update them to use the
FSP_VERSION1 condition instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-11 17:37:19 +08:00
Simon Glass
ca4e40887e x86: Add a function to find the size of an mrccache record
Move the code to determine the size of a cache record into a function so
we can use it elsewhere in this file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-11 17:37:19 +08:00
Simon Glass
3d95688c85 x86: Panic when SPL or TPL fail
At present when these fail to boot there is no message, just a hang. Add a
panic so it is obvious that something when wrong.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-11 16:45:05 +08:00
Simon Glass
cc2d27dcdc x86: Use mtrr_commit() with FSP2
With FSP2 we use MTRRs in U-Boot proper even though the 32-bit init
happens in TPL. Enable this, using a variable to try to make the
conditions more palatable.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:49 +08:00
Simon Glass
b377ebbd5b x86: cpu: Don't include the cpu driver in TPL
We don't need this driver very early in boot and it adds code size. Drop
it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:49 +08:00
Simon Glass
add3f4c918 x86: Add a function to set variable MTRRs
Normally U-Boot handles MTRRs through an add/commit process which
overwrites all MTRRs. But in very early boot it is not desirable to clear
the existing MTRRs since they may be in use and it can cause a hang.

Add a new mtrr_set_next_var() function which sets up the next available
MTRR to the required region.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: pass 'type' to set_var_mtrr() in mtrr_set_next_var()]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:48 +08:00
Simon Glass
6ccb2f890b x86: Refactor mtrr_commit() to allow for shared code
Move the code that actually sets up the MTRR into another function so it
can be used elsewhere in the file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:48 +08:00
Simon Glass
12e927b0a8 x86: Allow the PCH and LPC uclasses to work with of-platdata
At present these uclasses assumes that they are used with a device tree.
Update them to support of-platdata as well.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:48 +08:00
Simon Glass
a27520904f x86: Add new common CPU functions for turbo/burst mode
Add a few more CPU functions that are common on Intel CPUs. Also add
attribution for the code source.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add missing MSR_IA32_MISC_ENABLE write back in cpu_set_eist();
        fix 2 typos in cpu_get_burst_mode_state() comments]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:47 +08:00
Simon Glass
f6d00da459 x86: Tidy up some duplicate MSR defines
Some MSR registers are defined twice in different parts of the file. Move
them together and remove the duplicates. Also drop some thermal defines
which are not used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:47 +08:00
Simon Glass
2f0c2f03e7 x86: Add common functions for TDP and perf control
These functions are the same on modern Intel CPUs, so use common code to
set them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: return false instead of 0 in cpu_ivybridge_config_tdp_levels();
        fix 'muiltiplier' and 'desgn' typos]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:47 +08:00
Simon Glass
55a6b13a75 x86: Use a common bus clock for Intel CPUs
Modern Intel CPUs use a standard bus clock value of 100MHz, so put this in
a common file and tidy up the copies.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:47 +08:00
Simon Glass
246ac08b03 x86: Add a common function to set CPU thermal target
This code appears in a few places, so move it to a common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:46 +08:00
Simon Glass
e2493a7f5a x86: Use a common definition of MSR_IA32_PERF_CTL
Remove the duplicate definition as it is not needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:46 +08:00
Simon Glass
a827ba910c x86: pci: Drop the first parameter in pci_x86_r/w_config()
This parameter is needed by the PCI driver-mode interface but is always
NULL on x86. There are a number of calls to this function so it makes
sense to minimise the parameters.

Adjust the x86 function to omit the first parameter, and introduce stub
functions to handle the conversion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:46 +08:00
Simon Glass
49a0f8cc96 x86: Move acpi_s3.h to a common location
At present this hedaer is only available on x86. To allow sandbox to use
it for testing, move it to a common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:46 +08:00
Simon Glass
bdeb2bccbf x86: Rename turbo ratio MSR to MSR_TURBO_RATIO_LIMIT
This MSR number is used on most modern Intel processors, so drop the
confusing NHM prefix (which might mean Nehalem).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: drop MSR_IVT_TURBO_RATIO_LIMIT as no code uses it]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:37 +08:00
Simon Glass
ebe002cd18 x86: Add various MTRR indexes and values
Add some new MTRRs used by Apollolake as well as a mask for the MTRR
type.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:37 +08:00
Simon Glass
08deb6d36f x86: Add more comments to the start-up code
The full start-up sequence (TPL->SPL->U-Boot) can be a bit confusing since
each phase has its own 'start' file. Add comments to explain this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:36 +08:00
Simon Glass
6172e94c3c x86: Change condition for using CAR
At present we assume that CAR (Cache-as-RAM) is used if HOBs (Hand-off
blocks) are not, since HOBs typically indicate that an FSP is in use, and
FSPs handle the CAR init.

However this is a bit indirect, and for FSP2 machines which use their own
CAR implementation (such as apollolake) but use the FSP for other
functions, the logic is wrong.

To fix this, add a dedicated Kconfig option to indicate when CAR is used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fix a typo in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:36 +08:00
Simon Glass
c3863eadbc x86: fsp: Save usable RAM and hob_list in the handoff area
The useable RAM is calculated when the RAM is inited. Save this value so
that it can be easily used in U-Boot proper.

Also save a pointer to the hob list so that it is accessible (before
relocation only) in U-Boot proper. This avoids having to scan it in SPL,
for everything U-Boot proper might need later.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: guard handoff_arch_save() with IS_ENABLED(CONFIG_USE_HOB)]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:36 +08:00
Simon Glass
12c81b2f41 x86: spl: Move broadwell-specific code out of generic x86 spl
When TPL is running, broadwell needs to do different init from SPL. There
is no need for this code to be in the generic x86 SPL file, so move it to
arch_cpu_init().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:36 +08:00
Simon Glass
daade119aa x86: spl: Reduce priority of the basic SPL image loader
This image loader works on systems where the flash is directly mapped to
the last part of the 32-bit address space. On recent Intel systems (such
as apollolake) this is not the case.

Reduce the priority of this loader so that another one can override it.

While we are here, rename the loader to BOOT_DEVICE_SPI_MMAP since
BOOT_DEVICE_BOARD is not very descriptive.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:35 +08:00
Simon Glass
14dd93beb7 x86: spl: Use hang() instead of a while() loop
Use the standard hang() function when booting fails since this implements
the defined U-Boot behaviour for this situation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:35 +08:00
Simon Glass
e46d00c77c x86: pci: Add a function to clear and set PCI config regs
At present the x86 pre-DM equivalent of pci_bus_clrset_config32() does not
exist. Add it to simplify PCI init code on x86.

Also add the missing functions to this header.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:35 +08:00
Simon Glass
1eeb55755f x86: Add binman symbols to the image
It is useful in SPL and TPL to access symbols from binman, such as the
position and size of an entry in the ROM. Collect these symbols together
in the SPL binaries.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:35 +08:00
Simon Glass
d3abc5d1ee x86: Move common Intel CPU info code into a function
Add cpu_intel_get_info() to find out the CPU info on modern Intel CPUs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add parameter and return value descriptions]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:35 +08:00
Simon Glass
46dd41fa5a x86: fsp: Add access to variable MRC data
With FSP2 the non-volatile storage used by the FSP to init memory can be
split into a fixed piece (determined at compile time) and a variable piece
(determined at run time). Add support for reading the latter.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:31 +08:00
Simon Glass
ceec18491c x86: fsp: Add a few more definitions for FSP2
Add definitions for the FSP signature and the FSP init phase.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:16 +08:00
Simon Glass
62888d840f x86: fsp: Move common support functions into a common file
Some of this file can be shared between FSP1 and FSP2. Move it into a
shared file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:54:07 +08:00
Simon Glass
b2d544a15d x86: Move common fsp functions into a common file
Some of this file can be shared between FSP1 and FSP2. Move it into a
shared file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:54:01 +08:00
Simon Glass
e9de4a7cd3 x86: fsp: Move common dram functions into a common file
Most of the DRAM functionality can be shared between FSP1 and FSP2. Move
it into a shared file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:53:57 +08:00
Simon Glass
12cf65a4d1 x86: fsp: Tidy up comment style a little
The comments in the FSP code use a different style from the rest of the
x86 code. I am not sure it this is intentional.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fix 2 comment style issues]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:53:54 +08:00