2 commits

Author	SHA1	Message	Date
Dinh Nguyen	a45526aaa0	arm: socfpga: set the mpuclk divider in the Altera group register ... The mpuclk register in the Altera group of the clock manager divides the mpu_clk that is generated from the C0 output of the main pll. Without this patch, the default value of the register is 1, so the mpuclk will always get divided by 2 if the correct value is not set. For example, on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be 1.05 GHz. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>	2017-02-08 02:19:11 +01:00
Marek Vasut	ca62d2e1fc	arm: socfpga: Move wrappers into platform directory ... Move the wrappers for QTS-generated files into platform directory out of the board directory. The trick here is to add -I to CFLAGS such that it points to the board directory in source tree and thus the qts/ directory there is still reachable. Signed-off-by: Marek Vasut <marex@denx.de>	2015-08-23 11:56:19 +02:00

Renamed from board/altera/socfpga/wrap_pll_config.c (Browse further)