Commit graph

7 commits

Author SHA1 Message Date
Keerthy
769c94263f arm: dts: k3-j721e-mcu-wakeup: Add assigned-clocks/rates properties for ospi1/qspi
Add assigned-clocks/rates properties for ospi1/qspi.
This is the expected rate as per ROM configuration.

Signed-off-by: Keerthy <j-keerthy@ti.com>
2020-03-06 12:53:00 +05:30
Vignesh Raghavendra
224d7fe263 ARM: dts: k3-j721e: Add OSPI DT nodes
Add OSPI DT nodes to enable OSPI at U-Boot prompt and also to support
OSPI boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-03-03 13:08:13 +05:30
Vignesh Raghavendra
01ec6a5ae1 arm: dts: k3-j721e: Add I2C nodes
J721e SoC has 2 I2C instances in MCU domain and 7 I2C instances in main
domain. Add DT nodes for the same

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04 09:07:24 +05:30
Keerthy
0f63ceaf54 arm: dts: k3-j721e-r5-common: Add tps65941 node and dependent wkup_i2c0 node
Add tps65941 node and dependent wkup_i2c0 node needed for AVS class 0 support

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:17 -05:00
Vignesh Raghavendra
358032f9a5 arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node
Add DT node for HyperBus Memory Controller in the FSS. On J721e, its not
possible to use OSPI0 and HBMC simultaneously as they are muxed within
the Flash Subsystem hence disable HBMC by default as keep OSPI enabled.
Bootloader will fixup DT when it detects HyperFlash instead of OSPI.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2019-10-24 09:49:16 +02:00
Lokesh Vutla
b9f035e9c8 arm: dts: k3-j721e-mcu: Add MCU domain R5F cluster node
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
the MCU domain, and the remaining two clusters are present in the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a LockStep mode or in
an Asymmetric Multi Processing (AMP) fashion in Split-mode. These
subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.

Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5 cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11 10:07:34 -04:00
Lokesh Vutla
eeb2e8b6eb arm: dts: ti: Add Support for J721E SoC
Add initial SoC definition for J721E SoC.
Kernel dts posted here:
https://lore.kernel.org/lkml/20190522161921.20750-1-nm@ti.com/

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:28 -04:00