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54 commits

Author SHA1 Message Date
Dave Liu
1b5291dddf 85xx: Fix the clock adjust of mpc8569mds board 
Currently the clk_adj is 6 (3/4 cycle), The settings will cause
the DDR controller hang at the data init. Change the clk_adj
from 6 to 4 (1/2 cycle), make the memory system stable.

Signed-off-by: Dave Liu <daveliu@freescale.com>
 2009-06-09 22:58:05 +02:00
Kumar Gala
32049b4048 fsl_pci: Move prototypes into fsl_pci.h and remove explicit externs 
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
 2009-04-04 10:21:30 -05:00
Kumar Gala
c8514622e2 fsl_pci: Renamed immap_fsl_pci.h to fsl_pci.h 
Rename the pci header for FSL HW so we can move some prototypes
in there and stop doing explicit externs

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
 2009-04-04 10:21:29 -05:00
Haiying Wang
765547dc5e MPC85xx: Add MPC8569MDS board support 
This patch adds MPC8569MDS board support. The UART, QE UEC1 and UEC2, BRD
EEPROM on I2C2 bus, PCI express and DDR3 SPD are supported in this patch.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Hillel Avni <Hillel.Avni@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
 2009-03-30 13:33:51 -05:00