Commit graph

3 commits

Author SHA1 Message Date
Yen Lin
60acde43d7 spi: tegra: clear RDY bit prior to every transfer
The RDY bit indicates that a transfer is complete. This needs to be
cleared by SW before every single HW transaction, rather than only
at the start of each SW transaction (those being made up of n HW
transactions).

It seems that earlier HW may have cleared this bit autonomously when
starting a new transfer, and hence this code was not needed in practice.
However, this is generally a good idea in all cases. In Tegra124, the
HW behaviour appears to have changed, and SW must explicitly clear this
bit. Otherwise, SW will believe that transfers have completed when they
have not, and may e.g. read stale data from the RX FIFO.

Signed-off-by: Yen Lin <yelin@nvidia.com>
[swarren, rewrote commit description, unified duplicate RDY clearing code
and moved it right before the start of the HW transaction, unconditionally
exit loop after reading RX data, rather than checking if TX FIFO is empty,
since it is guaranteed to be]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-12-19 00:00:51 +05:30
Axel Lin
d6f64d4a11 spi: tegra114_spi: Convert to use spi_alloc_slave()
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-06-13 22:55:24 +05:30
Allen Martin
77c42e80b9 tegra114: add SPI driver
Add driver for tegra114 SPI controller.  This controller is not
compatible with either the tegra20 or tegra30 controllers, so it
requires a new driver.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:07 -07:00