Set default configuration to have SDHC controller enabled,
AUDIO enabled(codec clock sources is 12MHz) and disable TDM.
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
For soc which have pin multiplex relation, some of them can't enable
simultaneously. This patch add environment var 'hwconfig' content
defination for them. you can enable some one function by setting
environment var 'hwconfig' content and reset board. Detail setting
please refer doc/README.p1022ds
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Make the support for ATI graphics cards mutually exclusive with DIU.
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove the SERDES8 erratum work-around code that only applied to P4080
rev1, which is not supported by this version of U-Boot.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add documentation for the "serdes" hwconfig option, which is used to
specify the status of SerDes banks two and three for the SERDES8 erratum
work-around.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We don't really ever use Video cards on corenet_ds style boards and its
bloating our image which is close the its max size. Drop support and
also kill some defines for non-PNP PCI which we never use.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Flash might be in unknown state when u-boot is started with jtag.
And got wrong env data. So reset it in board early init.
We cannot use generic cfi flash routines, because flash_init() is
not run yet.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
renaming 85xx define CONFIG_NAND_OR_PRELIM to CONFIG_SYS_NAND_OR_PRELIM
and CONFIG_NAND_BR_PRELIM to CONFIG_SYS_NAND_BR_PRELIM to use the more
appropriate CONFIG_SYS prefix as well as be consistent with 83xx.
Signed-off-by: Matthew McClintock <msm@freescale.com>
cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit cfbe861506 removed the definition of
monitor_flash_len from the eNET which was not picked up due to extensive
use of the SRAM configuration target for testing
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
U-Boot itself takes up more than 0x40000 bytes, so we can't use that
sector for the environment. Move it down a page.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The bfin_reset_or_hang function unnecessarily duplicates the panic()
logic based on CONFIG_PANIC_HANG.
This patch deletes 20 lines of code and just calls panic() instead.
This also makes the following generic-restart conversion patch simpler.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Don't forget to count full data size for the multiblock operation request.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The timer register is 32bits, not 16bit, so 0xFFFF won't fill it.
Write out -1 to make sure to fill the whole thing.
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Some parts lack Bank B in L1 data, so have the linker script fall back to
Bank A when that happens. This way we can still leverage L1 data.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
When bootstrapping ourselves on the fly at runtime (via "go"), we need to
turn off the caches to avoid taking software exceptions. Since caches
need CPLBs and CPLBs need exception handlers, but we're about to rewrite
the code in memory where those exception handlers live, we need to turn
off caches first.
This new code also encourages a slight code optimization by storing the
MMR bases in dedicated registers so we don't have to fully load up the
pointer regs multiple times.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
If the part has no external memory configured, then there will be no os
log for us to check, and any attempt to access that memory will trigger
hardware errors.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Common code already takes care of setting up these defines when a port
hasn't specified them, so punt the duplicate values.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The recent global data changes (making the size autogenerated) broke the
board info handling on Blackfin ports as we were lying and lumping the
bd_t size in with the gd_t size. So use the new dedicated bd_t size to
setup its own address in memory.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Have CONFIG_ENV_ADDR be based on CONFIG_ENV_OFFSET rather than the other
way around so that we can use CONFIG_ENV_OFFSET during build. It also
avoids a little address duplication.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The __BFIN_DEF_ADSP_BF537_proc__ define isn't setup anymore, so use
the one coming from the compiler.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Info about the hardware can be found here:
http://www.dilnetpc.com/dnp0086.htm
Signed-off-by: Andreas Schallenberg <Andreas.Schallenberg@3alitydigital.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
We don't want/use this value for Blackfin boards, so punt it and have the
common code error out when people try to use it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Only the first run of boards had a ksz switch on it, so if building for a
newer silicon rev or SPI is disabled, don't bother checking for the ksz.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
collect code which protects default sectors in a function, called
flash_protect_default. So boardspecific code can call it too.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
* Added SDHCDCR register to GUR struct
* Added SDHCDCR_CD_INV define related to SDHCDCR
* Added Pin Muxing define related to TDM on P102x
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P1021 has some QE pins which need to be set in pmuxcr register before
using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and
UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to
be released after MII access because QE12 pin is muxed with LBCTL signal.
Also added relevant QE support defines unique to P1021.
The P1021 QE is shared on P1012, P1016, and P1025.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
