This is required by Chrome OS so that the audio and other unibuild
features work correctly. Add it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These settings are included twice. The second lot are correct, so drop the
others.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The bloblist guarantees that blobs are zeroed so there is no need to do
an additional memset(). Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present we create the ACPI context but then drop it after generation of
tables is complete. This is annoying because we have to then search for
tables later.
To fix this, allocate the context and store it in global_data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present write_tables() can fail but does not report this problem to its
caller. Fix this by changing the return type.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some boards need to include binary data into the image for use during the
boot process. Add a node for these.
An example is the audio-codec configuration used by some audio drivers on
Intel platforms. If no private files are provided, they will be omitted.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add definitions for part of the vboot context used with verified boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Set up MSRs required for Apollo Lake. This enables Linux to use the
timers correctly. Also write the fixed MSRs for this platform.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present there are a lot of dtoc warnings reported when building
chromebook_coral, of the form:
WARNING: the driver intel_apl_lpc was not found in the driver list
Correct these by using driver names that matches their compatible string.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
CONFIG_NEEDS_MANUAL_RELOC macro was out of Kconfig. Move it there to be
able to use compile-time checks to reduce the number of build paths.
Fixes: f9a882438966 ("dm: core: Convert #ifdef to if() in root.c") for Microblaze
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Merge tag 'u-boot-atmel-fixes-2021.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
First set of u-boot-atmel fixes for 2021.01 cycle:
This specific feature set includes the patches for DT required to fix
the warnings for newer DTC version (1.6.0+), i2c and spi bus unit
address.
w+arch/arm/dts/.at91sam9260ek.dtb.pre.tmp:119.21-123.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
w+arch/arm/dts/.at91sam9260ek.dtb.pre.tmp:119.21-123.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
w+arch/arm/dts/sama5d3xmb.dtsi:64.25-83.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f0018000/camera@0x30: I2C bus unit address format error, expected "30"
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
w+arch/arm/dts/.at91sam9g45-gurnard.dtb.pre.tmp:118.21-122.7: Warning (spi_bus_reg): /ahb/apb/spi@fffa4000/mtd_dataflash@0: SPI bus unit address format error, expected "1"
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
w+arch/arm/dts/.at91sam9g25ek.dtb.pre.tmp:28.25-47.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f8010000/camera@0x30: I2C bus unit address format error, expected "30"
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
w+arch/arm/dts/at91sam9g20ek_common.dtsi:100.21-104.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
w+arch/arm/dts/.at91sam9g20-taurus.dtb.pre.tmp:79.18-83.4: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
w+arch/arm/dts/.at91sam9261ek.dtb.pre.tmp:124.15-144.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/tsc2046@0: SPI bus unit address format error, expected "2"
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
w+arch/arm/dts/.at91-vinco.dtb.pre.tmp:131.18-134.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f8024000/rtc@64: I2C bus unit address format error, expected "32"
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
- New PX30 board: Engicam PX30.Core;
- Fix USB HID support for rock960;
- Remove host endianness dependency for rockchip mkimage;
- dts update for rk3288-tinker;
- Enable console MUX for some ROCKPi boards;
- Add config-based ddr selection for px30;
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.
PX30.Core needs to mount on top of this Carrier board for creating
complete PX30.Core C.TOUCH 2.0 board.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose
carrier board with capacitive touch interface.
Genaral features:
- TFT 10.1" industrial, 1280x800 LVDS display
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector
SOM's like PX30.Core needs to mount on top of this Carrier board
for creating complete PX30.Core C.TOUCH 2.0 board.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board from Engicam.
PX30.Core needs to mount on top of this Evaluation board for
creating complete PX30.Core EDIMM2.2 Starter Kit.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
TARGET_EVB_PX30 can be possible to use other px30 boards.
Add the help text for existing EVB, so-that the new boards
which are resuing this config option can mention their board
help text.
This would help to track which boards are using EVB_PX30 config.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
General features:
- Rockchip PX30
- Up to 2GB DDR4
- eMMC 4 GB expandible
- rest of PX30 features
PX30.Core needs to mount on top of Engicam baseboards for creating
complete platform boards.
Possible baseboards are,
- EDIMM2.2
- C.TOUCH 2.0
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.
Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out
SOM's like PX30.Core needs to mount on top of this Evaluation board
for creating complete PX30.Core EDIMM2.2 Starter Kit.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add chosen node in -u-boot.dtsi for ROCK-Pi N8 board.
This will help to get serial out messages.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
The property reg-shift with the same value is present in the base
device tree already. Remove unnecessary node from rk3288-tinker.dts.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The I2C EEPROM is present on Tinker Board S as well. Move the i2c node
to the shared, U-Boot specific rk3288-tinker-u-boot.dtsi device tree.
Cc: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This feature is incompatble with of-platdata since it uses the
U_BOOT_DEVICE() macro. With of-platdata the only devices permitted are
those created by dtoc.
The driver is not used in SPL anyway, so exclude it from that build.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Now that parent devices are supported with of-platadata, we don't need the
messy code to fix up the parent pointers and allocations on Apollo Lake.
Put the code behind a condition.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present, enabling CONFIG_APL_SPI_FLASH_BOOT does not build since SPI
and SPI flash are not enabled for TPL. Add a condition to fix this and
tidy up a build warning in the SPI-flash driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a simple test that we can obtain the correct parent for an I2C
device. This requires updating the driver names to match the compatible
strings, adding them to the devicetree and enabling a few options.
Signed-off-by: Simon Glass <sjg@chromium.org>
We have a test in dtoc for this feature, but not one in U-Boot itself.
Add a simple test that checks that the information comes through
correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a -u flag for U-Boot SPL which requests that unit tests be run. To
make this work, export dm_test_main() and update it to skip test features
that are not used with of-platdata.
To run the tests:
$ spl/u-boot-spl -u
U-Boot SPL 2020.10-rc5 (Oct 01 2020 - 07:35:39 -0600)
Running 0 driver model tests
Failures: 0
At present there are no SPL unit tests.
Note that there is one wrinkle with these tests. SPL has limited memory
available for allocation. Also malloc_simple does not free memory
(free() is a nop) and running tests repeatedly causes driver-model to
reinit multiple times and allocate memory. Therefore it is not possible
to run more than a few tests at a time. One solution is to increase the
amount of malloc space in sandbox_spl. This is not a problem for pytest,
since it runs each test individually, so for now this is left as is.
Signed-off-by: Simon Glass <sjg@chromium.org>
Without resizing the SDL window showed by
./u-boot -D -l
is not legible on a high resolution screen.
Allow resizing the window
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
- Armada 8k: Add NAND support via PXA3xx NAND driver (Baruch)
- Armada 8k: Use ATF serdes init instead of the "old" U-Boot version
(Baruch)
- Minor update to Octeon TX/TX2 defconfig (Stefan)
common:
- Add support for 64bit loadables from SPL
xilinx:
- Update documentation and record ownership
- Enable eeprom board detection based legacy and fru formats
- Add support for FRU format
microblaze:
- Optimize low level ASM code
- Enable SPI/I2C
- Enable distro boot
zynq:
- Add support for Zturn V5
zynqmp:
- Improve silicon detection code
- Enable several kconfig options
- Align DT with the latest state
- Enabling security commands
- Enable and support FPGA loading from SPL
- Optimize xilinx_pm_request() calling
versal:
- Some DTs/Kconfig/defconfig alignments
- Add binding header for clock and power
zynq-sdhci:
- Add support for tap delay programming
zynq-spi/zynq-qspi:
- Use clock framework for getting clocks
xilinx-spi:
- Fix some code issues (unused variables)
serial:
- Check return value from clock functions in pl01x
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Merge tag 'xilinx-for-v2021.01-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.01-v2
common:
- Add support for 64bit loadables from SPL
xilinx:
- Update documentation and record ownership
- Enable eeprom board detection based legacy and fru formats
- Add support for FRU format
microblaze:
- Optimize low level ASM code
- Enable SPI/I2C
- Enable distro boot
zynq:
- Add support for Zturn V5
zynqmp:
- Improve silicon detection code
- Enable several kconfig options
- Align DT with the latest state
- Enabling security commands
- Enable and support FPGA loading from SPL
- Optimize xilinx_pm_request() calling
versal:
- Some DTs/Kconfig/defconfig alignments
- Add binding header for clock and power
zynq-sdhci:
- Add support for tap delay programming
zynq-spi/zynq-qspi:
- Use clock framework for getting clocks
xilinx-spi:
- Fix some code issues (unused variables)
serial:
- Check return value from clock functions in pl01x
Move board_fit_config_name_match() from Zynq/ZynqMP to common location.
This change will open a way to use it also by Microblaze and Versal.
Through this function there is a way to handle images with multiple DTBs.
For now match it with DEVICE_TREE as is done for Zynq.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Align node properties to kernel dts node.
The change of compatible property does not affect any currently
supported board.
Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility
with the current driver.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Align node properties to kernel dts node.
Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility
with the current driver.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Provide tests to check the behavior of the multiplexer framework.
Two sets of tests are added. One is using an emulated multiplexer driver
that can be used to test basic functionality like select, deselect, etc.
The other is using the mmio mux which adds tests specific to it.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For zynqmp qspi, frequencies up to 40MHz will work irrespective
of feedback clock enabled or disabled. If we want higher than
40Mhz the feedback clock should be enabled.
With spi-max-frequency 108MHz it is not working when the feedback
clock is disabled. Change it to 40MHz so that it works irrespective
of feedback clock enabled or disabled.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
