Commit graph

2577 commits

Author SHA1 Message Date
Jimmy Zhang
b9dd6215ce ARM: tegra: don't exceed AVP limits when configuring PLLP
Based on the Tegra TRM, the system clock (which is the AVP clock) can
run up to 275MHz. On power on, the default sytem clock source is set to
PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to
408MHz which is beyond system clock's upper limit.

The fix is to set the system clock to CLK_M before initializing PLLP,
and then switch back to PLLP_OUT4, which has an appropriate divider
configured, after PLLP has been configured

Implement this logic in new function tegra30_set_up_pllp(),
which sets up PLLP and all PLLP_OUT* dividers, and handles the AVP
clock switching. Remove the duplicate PLLP setup from pllx_set_rate()
and adjust_pllp_out_freqs().

Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
[swarren, significantly refactored the change]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03 09:46:45 -07:00
Stephen Warren
9399e540ca ARM: tegra: amend pmc.h for Tegra114+
Tegra114 and later's PMC module removes the pwrgate_timer_on register
and replaces it with a clamp_status register. Adjust pmc.h to reflect
this, and update any code affected by the change.

The cpu.c change in this patch was extracted from a much larger patch
by Jimmy Zhang. The pmc.h change was written from scratch, but inspired
by related changes made by Tom Warren.

There could well be other differences in the PMC register set for chips
after Tegra20/30. However, they don't affect the code in U-Boot at
present, so I haven't attempted an exhaustive update of pmc.h.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03 09:46:45 -07:00
Tom Warren
c82014daf5 ARM: tegra: implement MASK_BITS_31_29
Some clock sources have 3-bit muxes in bits 31:29. Implement core
support for this mux field.

Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, extracted from a larger patch by Tom]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03 09:46:45 -07:00
Stephen Warren
04b8e8e745 ARM: tegra: MASK_BITS_ no longer needs specific values
Since all code that sets or interprets MASK_BITS_* now uses the enums
to define/compare the values, there is no need for MASK_BITS_* to have
a specific integer value. In fact, having a specific integer value may
encourage people to hard-code those values, or interpret the values in
incorrect ways.

As such, remove the logic that assigns a specific value to the enum
values in order to make it completely clear that it's just an enum, not
something that directly represents some integer value.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03 09:46:45 -07:00
Stephen Warren
54d2e18292 ARM: tegra: use MASK_BITS_* macros everywhere
Not all code that set or interpreted "mux_bits" was using the named
macros, but rather some was simply using hard-coded integer constants.
This makes it hard to determine which pieces of code are affected by
changes to those constants.

Replace the integer constants with the equivalent macro definitions so
that everything is nicely tied together.

Note that I'm not convinced all the code was using the correct integer
constants, and hence I'm not convinced that all the code is now using
the desired macros. However, this change is a purely mechanical
replacement and should have no functional change. Fixing any bugs will
come later, separately.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03 09:46:45 -07:00
Stephen Warren
9cb0c6dc69 ARM: tegra: rename OUT_CLK_SOURCE_*
OUT_CLK_SOURCE_ are currently named after the number of bits the mask
they represent includes. However, bit count is not the only possible
variable; bit position may also vary. Rename OUT_CLK_SOURCE_ to
OUT_CLK_SOURCE_31_30_ and OUT_CLK_SOURCE4_ to OUT_CLK_SOURCE_31_28 to
more completely describe exactly what they represent, without having to
go look up the definitions.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03 09:46:45 -07:00
Stephen Warren
5916a36ee9 ARM: tegra: rename MASK_BITS_29_28 to MASK_BITS_31_28
The only place where the MASK_BITS_* values are used is in
adjust_periph_pll(), which interprets the value 4 (old MASK_BITS_29_28,
new MASK_BITS_31_28) as being associated with mask OUT_CLK_SOURCE4_MASK,
i.e. bits 31:28. Rename the MASK_BITS_ macro to reflect how it's actually
implemented.

Note that no Tegra clock register actually uses all of bits 31:28 as
the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
those cases, nothing is stored in the bits above the mux field, so it's
safe to pretend that the mux field extends all the way to the end of the
register. As such, the U-Boot clock driver is currently a bit lazy, and
doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps
them all together and pretends they're all 31:28. This patch doesn't
cause this issue; it was pre-existing. Hopefully, future patches will
clean this up.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03 09:46:45 -07:00
Tom Warren
0b01b53aa5 ARM: tegra: deduplicate MASK_BITS_xxx clock mux enum
The enum used to define the set of register bits used to represent a
clock's input mux, MUX_BITS_*, is defined separately for each SoC at
present. Move this definition to a common location to ease fixing up
some issues with the definition, and the code that uses it.

Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, extracted from a larger patch by Tom]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03 09:46:44 -07:00
Stephen Warren
86b657878b ARM: tegra: accept any SKU ID for most chips
For Tegra20, the SKU ID actually impacts how U-Boot programs the chip,
and hence we need to explicitly know about each and every SKU ID in order
to operate correctly.

However, for Tegra30/114, this isn't the case. Rather than forcing each
new user with a different SKU to manually add their SKU ID into the code,
simply accept any SKU ID.

If U-Boot ever starts e.g. programming maximal CPU clocks etc., we'll
need to undo this, or make the default case map to conservative defaults,
but for now it's likely the path to least support cost.

Reported-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03 09:46:44 -07:00
Przemyslaw Marczak
8475c869c3 s5p: gpio: change gpio coding method for s5p gpio.
Old s5p gpio coding method was not clean and was not working properly
for all parts and banks. New method is clean and easy to extend.

Gpio coding mask:
0x000000ff - pin number
0x00ffff00 - bank offset
0xff000000 - part number

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-02-03 15:36:14 +09:00
Albert ARIBAUD
e97f9d817e Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2014-01-29 14:07:50 +01:00
Marek Vasut
e9be4292e4 ARM: mx6: Add PCI express driver
Add PCIe driver for the Freescale i.MX6 SoC . This driver operates the
PCIe block in RC mode only, the EP mode is NOT supported. The driver is
tested with the Intel e1000 NIC driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2014-01-26 12:41:20 +01:00
Marek Vasut
7981449280 ARM: mx6: Add PCI express clock configuration
Split the SATA clock enabling function and add PCI express clock
enabling function. The SATA clock enabling function starts up the
100MHz SATA reference PLL in ENET_PLL register, but the code can
be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull
this code into separate function. Moreover, add the PCIe clock
enabling code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-01-26 12:41:20 +01:00
Marek Vasut
7cbe638e41 ARM: armv7: Make indirect vector addresses globl
Make indirect vectors addresses global, so they can be replaced by
various code that needs to do so. For example the MX6 PCI express
driver needs to temporarily replace data abort handler when reading
the config space.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2014-01-26 12:41:20 +01:00
Stefano Babic
707acd01de Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-01-26 12:11:54 +01:00
Dan Murphy
8cffe5bd0d spl: common: Support for USB MSD FAT image loading
Add SPL support to be able to detect a USB Mass Storage device
connected to a USB host.  Once a USB Mass storage device is detected
the SPL will load the u-boot.img from a FAT partition to target address.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
2014-01-24 16:59:22 -05:00
Masahiro Yamada
bf1af3d872 ARM: merge commonly-defined PLATFORM_RELFLAGS
Before this commit, all arch/arm/cpu/${CPU}/config.mk except ARMv8
had the same option:
$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

This commit moves it into arch/arm/config.mk.

If the compiler does not support the option,
it is ignored by $(call cc-option,...).
So this commit gives no harm to ARMv8.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:08 -05:00
Darwin Rambo
de351d6be6 lib: time: add weak timer_init() function
If timer_init() is made a weak stub function, then it allows us to
remove several empty timer_init functions for those boards that
already have a timer initialized when u-boot starts. Architectures
that use the timer framework may also remove the need for timer.c.

Signed-off-by: Darwin Rambo <drambo@broadcom.com>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
2014-01-24 16:59:06 -05:00
Nishanth Menon
194dd74ad9 DRA7: add ABB setup for MPU voltage domain
Patch adds modification to shared omap5 abb_setup() function, and
proper registers definitions needed for ABB setup sequence. ABB is
initialized for MPU voltage domain at OPP_NOM.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-01-24 11:41:17 -05:00
Nishanth Menon
3ac8c0bf65 DRA7: Add support for ES1.1 silicon ID code
ES1.1 silicon is a very minor variant of ES1.0. Add priliminary support
for ES1.1 IDCODE change.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-01-24 11:41:17 -05:00
Satyanarayana, Sandhya
e9b13ce0b6 ARM: AM335x: Enable DDR dynamic IO power down
This patch enables dynamically powering down the
IO receiver when not performing a read on boards using DDR3.
This optimizes both active and standby power consumption.
This bit is not set on EVM SK and EVM 1.5 and later boards.
Setting the same.

This has been tested on PG2.0 EVM1.5, EVM1.2, EVM-SK, BBB.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
2014-01-24 11:38:39 -05:00
Enric Balletbò i Serra
ac02aa9763 ARM: OMAP3: Rename OMAP3_PUBLIC_SRAM_* to NON_SECURE_SRAM_*
Other TI processors like am33xx, omap4 and omap5 have called these variables
as NON_SECURE_SRAM_*, shouldn't be a big problem rename these variables to
be coherent.

One reason more to rename these variables is to have the possibility of any
OMAP3 board to use the ti_armv7_common.h include as the NON_SECURE_SRAM_END
is used to define the CONFIG_SYS_INIT_SP_ADDR variable.

Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
2014-01-24 11:38:39 -05:00
Jassi Brar
e81f63f0d2 ARM: OMAP4/5: Remove dead code against CONFIG_SYS_ENABLE_PADS_ALL
The commit
f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls"
removed the config option aimed towards moving that stuff into kernel, which
renders some code unreachable. Remove that code.

Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2014-01-24 09:38:39 -05:00
Jassi Brar
02c41535b6 ARM: OMAP4/5: Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL
The commit
 f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls"
removed the config option aimed towards moving that stuff into kernel, which
renders some code unreachable. Remove that code.

Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2014-01-24 09:34:22 -05:00
Stephen Warren
004c10598b ARM: bcm2835: fix mailbox timeout
My original intention was to have a 100ms timeout. However, the timer
operations used return values in ms not us, so we ended up with a 100s
timeout instead. Fixing this exposes that some operations need longer
to operate than 100ms, so bump the timeout up to a whole second.

Reported-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Andre Heider <a.heider@gmail.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2014-01-20 17:11:39 -05:00
Stephen Warren
f66f2aa265 ARM: rpi_b: power on SDHCI and USB HW modules
Send RPC commands to the VideoCore to turn on the SDHCI and USB modules.
For SDHCI this isn't needed in practice, since the firmware already
turned on the power in order to load U-Boot. However, it's best to be
explicit. For USB, this is necessary, since the module isn't powered
otherwise. This will allow the kernel USB driver to work.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2014-01-20 17:11:39 -05:00
Tom Rini
4641c211f6 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-01-20 07:33:42 -05:00
Fabio Estevam
be2a3bb39a mx6: Revert "mx6: soc: Disable VDDPU regulator"
Commit 022298278 (mx6: soc: Disable VDDPU regulator) is causing kernel hang
for people using FSL kernel 3.0.35 and 3.10, so revert it for now.

Reported-by: Otavio Salvador <otavio@ossystems.com.br>
Reported-by: Pierre Aubert <p.aubert@staubli.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-17 10:16:48 +01:00
Tom Rini
4913fc23f0 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-01-16 13:50:16 -05:00
Nobuhiro Iwamatsu
82852762ce arm: rmobile: Add SH QSPI base register address
This adds base register address of SH QSPI.
Currently, SH QSPI is used only from R8A7790 and R8A7791.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-01-16 08:07:20 +09:00
Albert ARIBAUD
bf46e7d8d1 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2014-01-15 15:18:04 +01:00
Fabio Estevam
3a21773129 mx6: Add initial support for the Hummingboard solo
SolidRun has designed the Hummingboard board based on mx6q/dl/solo.

Add the initial support for the mx6 solo variant.

More information about this hardware can be found at:
http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware

(Carrier-One was the previous name of Hummingboard).

Based on the work from Jon Nettleton <jon.nettleton@gmail.com>.

Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-15 10:33:25 +01:00
Fabio Estevam
5f98d0b5d3 mx6: clock: Pass the frequency as argument of enable_fec_anatop_clock()
Provide an argument to enable_fec_anatop_clock() to specify the clock frequency
that will be generated.

No changes are made to mx6slevk, which uses the default 50MHz fec clock.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-01-15 10:33:25 +01:00
Tom Rini
b5c068f3f8 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-01-14 14:48:42 -05:00
Andreas Bießmann
6ba2bc8fa9 arm: use canonical sub mnemonic
Building some arm boards with older binutils may produce errors like this:

---8<---
crt0.S: Assembler messages:
crt0.S:70: Error: register expected, not '#(184)' -- `sub sp,#(184)'
--->8---

Use canonical version of the subtract mnemonic to avoid those issues.

Reported-by: Alexey Smishlayev <alexey@xtech2.lv>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-01-14 12:38:47 +01:00
Albert ARIBAUD
e6fe4bd989 Merge 'u-boot-imx/master' into 'u-boot-arm/master' 2014-01-14 11:50:54 +01:00
Albert ARIBAUD
b02bfc4dfc arm: put .hash, .got.plt and .machine_param back in binaries
Some targets will build fine but not boot if sections .hash and
.got.plt are not present in the binary. Add them back.

Also, Exynos machines require .machine_param section in SPL.
Add it.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
2014-01-14 11:43:10 +01:00
Tom Rini
0effc5e567 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-01-13 13:50:25 -05:00
Marek Vasut
67decc71ed ARM: pxa: Fix OneNAND SPL builds
The OneNAND SPL used on PXA is slightly obscure. Due to the OneNAND limitation,
where we have only the first 1KiB of the OneNAND available upon power-up as a
memory-mapped area, from which the CPU starts executing, we place only the most
essential code into this first 1KiB . This code copies the rest of the SPL into
SRAM and jumps to it. This code is stored in section .text.0 .

The rest of the SPL is stored in section .text.1 . When running the OBJCOPY on
the SPL, it will preserve only .text section, but the .text.0 and .text.1 are
stripped away from the result, thus making the SPL binary empty. The patch adds
additional -j parameters to the OBJCOPY for PXA during the SPL build, which will
preserve the .text.0 and .text.1 sections.

Moreover, this patch also adds missing functions into the .text.0 section, since
otherwise the PXA270 with 1KiB-window OneNAND won't be able to boot.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
2014-01-13 12:39:10 +01:00
Inderpal Singh
16f9480dfc usb: ehci: exynos: set/reset hsic phys
The controller has 3 ports. The port0 is for USB 2.0 Phy, port1 and port2
are for HSIC phys. The usb 2.0 phy is already being setup. This patch
sets up the hsic phys.

Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
2014-01-13 12:23:28 +01:00
Christian Gmeiner
5a66016987 imx6: make use of lldiv(..)
Commit 762a88ccf8 introduces
a 64-bit division without using the lldiv() function,
which pulls in previously unused libgcc stuff.

Signed-off-by: Måns Rullgård <mans@mansr.com>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-01-13 11:52:28 +01:00
Tom Rini
7f673c99c2 Merge branch 'master' of git://git.denx.de/u-boot-arm
Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be
added to include/configs/exynos5-dt.h now.

Conflicts:
	include/configs/exynos5250-dt.h

Signed-off-by: Tom Rini <trini@ti.com>
2014-01-10 10:56:00 -05:00
Jagannadha Sutradharudu Teki
84515165da gpio: zynq: Add dummy gpio routines
GPIO dummy routines are required for fdt build, may be removed
these dependencies once the u-boot fdt is fully optimized.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-10 15:18:33 +01:00
Jagannadha Sutradharudu Teki
f8f36c5dda dts: zynq: Add basic fdt support
This patch provides a basic fdt support for zynq u-boot.

zynq-7000.dtsi-> initial arch dts file
zynq-zed.dts -> initial zed board dts file
more devices should be added in subsequent patches.

u-boot build: once configuring of a board done
for building dtb with zynq-zed.dts as an input
zynq-uboot> make DEVICE_TREE=zynq-zed

Enabled CONFIG_OF_SEPARATE for building dtb separately.
There is a new binary called u-boot-dtb.bin which is a u-boot
with devicetree supported.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-10 15:18:33 +01:00
Jagannadha Sutradharudu Teki
b3de92495f zynq: Add support to find bootmode
Added support to find the bootmodes by reading
slcr bootmode register. this can be helpful to
autoboot the configurations w.r.t a specified bootmode.

Added this functionality on board_late_init as it's not
needed for normal initializtion part.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-10 15:18:33 +01:00
Tom Rini
795611e6ff armv8: Use __aarch64__ rather than CONFIG_ARM64 in some cases
The toolchain sets __aarch64__ for both LE and BE.  In the case of
posix_types.h we cannot reliably use config.h as that will lead to
problems.  In the case of byteorder.h it's clearer to check the EB flag
being set in either case instead.

Cc: David Feng <fenghua@phytium.com.cn>
Signed-off-by: Tom Rini <trini@ti.com>

Amended by Albert ARIBAUD <albert.u.boot@aribaud.net> to
actually remove the config.h include from the posix_types.h
files, with permission from Tom Rini.
2014-01-10 10:10:23 +01:00
David Feng
0ae7653128 arm64: core support
Relocation code based on a patch by Scott Wood, which is:
Signed-off-by: Scott Wood <scottwood@freescale.com>

Signed-off-by: David Feng <fenghua@phytium.com.cn>
2014-01-09 16:08:44 +01:00
Chin Liang See
c5c1af2176 socfpga/dwmmc: Adding DesignWare MMC driver support for SOCFPGA
To add the DesignWare MMC driver support for Altera SOCFPGA. It
required information such as clocks and bus width from platform
specific files (SOCFPGA handoff files)

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-01-09 11:53:55 +02:00
Albert ARIBAUD
4b0561d841 Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2014-01-06 09:32:42 +01:00
Albert ARIBAUD
a891601ce5 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts:
	include/micrel.h

The conflict above was trivial, caused by four lines being
added in both branches with different whitepace.
2014-01-06 08:49:58 +01:00
Sergey Alyoshin
4611d5bab2 arm: mx5: Add fuse supply enable in fsl_iim
Enable fuse supply before fuse programming and disable after.

Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2014-01-03 15:44:06 +01:00
Otavio Salvador
c655b816e5 ARM: mx6: Allow enablement of FEC Anatop based clock for all MX6
The enable_fec_anatop_clock method should be available for all MX6
variant as it is not MX6 SoloLite specific. This moves the code out of
the #ifdef/#endif and we make it conditional to CONFIG_FEC_MXC
instead.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-01-03 15:44:05 +01:00
Otavio Salvador
7773fd1969 imx: Easy enabling of SION per-pin using MUX_MODE_SION helper macro
The macro allows easy setting in per-pin, as for example:

,----
| imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION);
`----

The IOMUX_CONFIG_SION allows for reading PAD value from PSR register.

The following quote from the datasheet:

,----
| ...
| 28.4.2.2 GPIO Write Mode
| The programming sequence for driving output signals should be as follows:
| 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need
| to read loopback pad value through PSR
| 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b).
| 3. Write value to data register (GPIO_DR).
| ...
`----

This fixes the gpio_get_value to properly work when a GPIO is set for
output and has no conflicts.

Thanks for Benoît Thébaudeau <benoit.thebaudeau@advansee.com>, Fabio
Estevam <fabio.estevam@freescale.com> and Eric Bénard
<eric@eukrea.com> for helping to properly trace this down.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-01-03 15:44:05 +01:00
Fabio Estevam
0222982780 mx6: soc: Disable VDDPU regulator
As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator
in order to save power.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02 17:16:51 +01:00
Fabio Estevam
39f0ac9347 mx6: soc: Add the required LDO ramp up delay
When changing LDO voltages we need to wait for the required amount of time
for the voltage to settle.

Also, as the timer is still not available when arch_cpu_init() is called, we
need to call it later at board_postclk_init() phase.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02 17:16:51 +01:00
Fabio Estevam
3d622b78bd mx6: soc: Introduce set_ldo_voltage()
Introduce set_ldo_voltage() so that all three LDO regulators can be configured.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02 17:16:51 +01:00
Fabio Estevam
7e5e8c94a9 mx6: soc: Set the VDDSOC at 1.175 V
mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V.
Add a 25 mV margin and set it to 1.175V.

This also matches the VDDSOC voltages for 792MHz operation that the kernel configures:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02 17:16:50 +01:00
Fabio Estevam
e113fd1972 mx6: soc: Clear the LDO ramp values up prior to setting the LDO voltages
Since ROM may modify the LDO ramp up time according to fuse setting,
it is safer to reset the ramp up field to its default value of 00:

00: 64 cycles of 24MHz clock;
01: 128 cycles of 24MHz clock;
02: 256 cycles of 24MHz clock;
03: 512 cycles of 24MHz clock;

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02 17:16:50 +01:00
Fabio Estevam
fc740648bd mx6: soc: Staticize set_vddsoc()
set_vddsoc() is not used anywhere else, so make it static.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02 17:16:50 +01:00
Rajeshwari Birje
e2be3369c8 DTS: Add dts support for SMDK5420
This patch adds dts support for SMDK5420.
exynos5.dtsi created is a common file which has the nodes common
to both 5420 and 5250.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:35 +09:00
Rajeshwari Birje
5af4a4f74a Exynos5420: Add support for 5420 in pinmux and gpio
Adds code in pinmux and gpio framework to support Exynos5420.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Rajeshwari Birje
f3d7c2fe9d Exynos5420: Add DDR3 initialization for 5420
This patch intends to add DDR3 initialization code for Exynos5420.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Rajeshwari Birje
060c227a28 Exynos5420: Add clock initialization for 5420
This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Rajeshwari Birje
e89278c933 EXYNOS5420: Add dmc and phy_control register structure
Add dmc and phy_control register structure for 5420.

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Rajeshwari Birje
3e97635764 EXYNOS5420: Add power register structure.
Add structure for power register for Exynos5420

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Rajeshwari Birje
e69847ab8d Exynos5420: Add base addresses for 5420
Adds base addresses of various IPs and controllers required for
Exynos5420.

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Rajeshwari Birje
71ebb33559 EXYNOS5: Create a common board file
Create a common board.c file for all functions which are common across
all EXYNOS5 platforms.

exynos_init function is provided for platform specific code.

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Stefano Babic
f5514e47c4 MX6: fix sata compilation for i.MX6
Commit 164d984661 breaks
board with SATA support, because sata is not compiled.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-12-19 11:04:33 +01:00
Lokesh Vutla
b5e01eecc8 ARM: AM43xx: GP_EVM: Add support for DDR3
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:45 -05:00
Lokesh Vutla
d3daba10f1 ARM: AM43xx: EPOS_EVM: Add support for LPDDR2
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
-> Wait till initialization is complete and the configure MR registers.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:44 -05:00
Lokesh Vutla
965de8b91b ARM: AM33xx+: Update ioregs to pass different values
Currently same value is programmed for all ioregs. This is not
the case for all SoC's like AM4372. So adding a structure for ioregs
and updating in all board files. And also return from config_cmd_ctrl()
and config_ddr_data() functions if data is not passed.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Fixup dxr2, cm_t335, adapt pcm051 rev3]
Signed-off-by: Tom Rini <trini@ti.com>
2013-12-18 21:14:18 -05:00
Lokesh Vutla
cf04d0326b ARM: AM43xx: clocks: Update DPLL details
Updating the Multiplier and Dividers value for all DPLLs.
Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
returned the MPU DPLL is locked.
At different OPPs follwoing are the MPU locked frequencies.
OPP50	300MHz
OPP100	600MHz
OPP120	720MHz
OPPTB	800MHz
OPPNT	1000MHz
According to the latest DM following is the OPP table dependencies:
	VDD_CORE 	VDD_MPU
	OPP50		OPP50
	OPP50 		OPP100
	OPP100		OPP50
	OPP100		OPP100
	OPP100		OPP120
So at different OPPs of MPU it is safest to lock CORE at OPP_NOM.
Following are the DPLL locking frequencies at OPP NOM:
Core locks at 1000MHz
Per locks at 960MHz
LPDDR2 locks at 266MHz
DDR3 locks at 400MHz

Touching AM33xx files also to get DPLL values specific to board but no
functionality difference.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:01 -05:00
Lokesh Vutla
4892495e36 ARM: AM43xx: mux: Update mux data
Updating the mux data for UART, adding data for i2c0 and mmc.
And also updating pad_signals structure.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:01 -05:00
Lokesh Vutla
1fb68b842e ARM: AM43xx: Update Current Booting devices list
Current Booting devices list is different from that of AM33xx.
Updating the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:01 -05:00
Lokesh Vutla
0d54cb924e ARM: AM43xx: Select clk source for Timer2
Selecting the Master osc clk as Timer2 clock source.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:01 -05:00
Sekhar Nori
9f1a8cd33f ARM: AM43XX: board: add support for reading onboard EEPROM
Add support for reading onboard EEPROM to enable
board detection.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:00 -05:00
Lokesh Vutla
369cbe1e1e ARM: AM43xx: Adapt to ti_armv7_common.h config file
Use ti_armv7_common.h config file to inclde the common
configs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:00 -05:00
Lokesh Vutla
7ca1b2a210 ARM: AM43xx: Update the base addresses of modules
PRCM, timer base addresses and offsets are different from
AM33xx. Updating the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:13:59 -05:00
Albert ARIBAUD
d627eefcd5 Merge remote-tracking branch 'u-boot-pxa/master' into 'u-boot-arm/master' 2013-12-18 22:19:02 +01:00
Alban Bedel
766afc3dff arm: tegra: Fix the CPU complex reset masks
The CPU complex reset masks are not matching with the datasheet for
the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20
and T30 the register consist of groups of 4 bits, with one bit for
each CPU core. On T20 the 2 high bits of each group are always stubbed
as there is only 2 cores.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swrren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-12-18 10:19:49 -07:00
Alban Bedel
3346cbb8e8 ARM: tegra: support SKU b1 of Tegra30
Add the Tegra30 SKU b1 and treat it like other Tegra30 chips.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Reviewed-by: Julian Scheel <julian.scheel@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-12-18 10:19:48 -07:00
Thierry Reding
4475c7752d Tegra114: Do not program CPCON field for PLLX
PLLX no longer has the CPCON field on Tegra114, so do not attempt to
program it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-12-18 10:19:48 -07:00
Jimmy Zhang
44de8e22ec Tegra114: Fix PLLX M, N, P init settings
The M, N and P width have been changed from Tegra30. The maximum value
for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should
be set accordingly.

Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-12-18 10:19:48 -07:00
Sergei Ianovich
23f00caf6e ARM: pxa: prevent PXA270 occasional reboot freezes
Erratum 71 of PXA270M Processor Family Specification Update
(April 19, 2010) explains that watchdog reset time is just
8us insead of 10ms in EMTS.

If SDRAM is not reset, it causes memory bus congestion and
the device hangs.

We put SDRAM in selfresh mode before watchdog reset, removing
potential freezes.

Signed-off-by: Sergei Ianovich <ynvich@gmail.com>
CC: Marek Vasut <marex@denx.de>
2013-12-18 16:00:37 +01:00
Frank Li
ebaf6b26bc imx6: fix random hang when download by usb
ROM did not invalidate L1 cache when download by usb
Need invalidate L1 cache before enable cache

Signed-off-by: Huang yongcai <b20788@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
2013-12-17 18:48:45 +01:00
Fabio Estevam
89cfd0f575 mx6: clock: Fix the calculation of PLL_ENET frequency
According to the mx6 quad reference manual, the DIV_SELECT field of register
CCM_ANALOG_PLL_ENETn has the following meaning:

"Controls the frequency of the ethernet reference clock.
- 00 - 25MHz
- 01 - 50MHz
- 10 - 100MHz
- 11 - 125MHz"

Current logic does not handle the 25MHz case correctly, so fix it.

Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-12-17 18:38:42 +01:00
Giuseppe Pagano
164d984661 nitrogen6x: Move setup_sata to common part
Move setup_sata function definition from platform file nitrogen6x.c
to arch/arm/imx-common/sata.c to avoid code duplication.

Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Eric Nelson <eric.nelson@boundarydevices.com>
2013-12-17 18:12:14 +01:00
Eric Nelson
b47abc36aa i.MX6 (DQ/DLS): use macros for mux and pad declarations
This allows the use of either or both declarations from
the files mx6q_pins.h and mx6dl_pins.h.

All board files should include <asm/arch/mx6-pins.h>
with one of the following defined in boards.cfg
    MX6Q   - for boards targeting i.MX6Q or i.MX6D
    MX6DL  - for boards targeting i.MX6DL
    MX6S   - for boards targeting i.MX6S
    MX6QDL - for boards that support any of the above with
             run-time detection

Pad declarations will be MX6_PAD_x for single-variant boards
and MX6Q_PAD_x and MX6DL_PAD_x for boards supporting both
processor classes.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-12-17 17:12:34 +01:00
Miao Yan
871a57bb81 common/cmd_bootm: extend do_bootm_vxworks to support the new VxWorks boot interface.
The next version VxWorks adopts device tree (for PowerPC and ARM) as its hardware
description mechanism. For PowerPC, the boot interface conforms to
the ePAPR standard, which is:

   void (*kernel_entry)(ulong fdt_addr,
          ulong r4 /* 0 */,
          ulong r5 /* 0 */,
          ulong r6 /* EPAPR_MAGIC */, ulong r7 /* IMA size */,
          ulong r8 /* 0 */, ulong r9 /* 0 */)

For ARM, the boot interface is:

   void (*kernel_entry)(void *fdt_addr)

Signed-off-by: Miao Yan <miao.yan@windriver.com>
[trini: Fix build error when !CONFIG_OF_FDT is set, typo on PowerPC,
missing extern ft_fixup_num_cores]
Signed-off-by: Tom Rini <trini@ti.com>
2013-12-16 08:59:05 -05:00
Tom Rini
49a90e2975 ARM:PXA: Correct tick_to_time / us_to_tick to use lldiv
Cc: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-12-13 09:16:20 -05:00
Tom Rini
e83bab8403 ARM:zynq: Correct __udelay to use lldiv
Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: Tom Rini <trini@ti.com>
2013-12-13 09:16:20 -05:00
Lokesh Vutla
d2c7074b95 ARM: OMAP5: clocks: Update MPU settings for OPP_NOM
As per the latest 0.6 version of DM for OMAP5430 ES2.0,
MPU_GCLK is given as 1000MHz. In order to achieve this DPLL_MPU
should be locked at 2000MHz. Fixing the same and cleaning the
previously used dpll values.

Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-12 17:43:39 -05:00
Lokesh Vutla
5298f21ab3 ARM: DRA7xx: Change clk divider setting
Commit "armv7: hw_data: change clock divider setting"
updates the setting for m6 divider for 20MHz sys_clk frequency.
But missed to update for other sys_clk frequencies. Doing the same.

Reported-by: Rajendran, Vinothkumar <vinothr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-12 17:43:39 -05:00
Nikita Kiryanov
47b4bcf785 arm: omap: abb: add missing include
ABB code uses LDELAY but does not include the header that provides its
definition.

Include the header.

Cc: Tom Rini <trini@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Nishanth Menon <nm@ti.com>
2013-12-12 14:54:22 -05:00
Dan Murphy
052fb19603 arm: am437: Fix offset for USB registers
Fix the offset for the USB clock registers

Signed-off-by: Dan Murphy <dmurphy@ti.com>
2013-12-12 14:54:22 -05:00
Lokesh Vutla
dcc2357638 ARM: OMAP4: Move TEXT_BASE down to non-HS limit
With the current scenario SPL size is being overlapped with the public
stack and not allowing any OMAP4 device to boot. So the suggestion came
up was to move the TEXT_BASE down to non-HS limit. Fixing the same and
also moving the SRAM_SCRATCH_SPACE_ADDR up to the end of image
downloadable area.
Discussion on this can be seen here:
https://www.mail-archive.com/u-boot@lists.denx.de/msg127147.html

Tested on OMAP4460 PANDA.

Reported-by: Chao Xu <caesarxuchao@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-12 14:54:20 -05:00
Tom Rini
12115c6ad3 am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF
Test on Beaglebone white over cpsw, usb ether and SD card (read and
write), performance increased, crc32 of data matches.

Signed-off-by: Tom Rini <trini@ti.com>
2013-12-12 14:54:12 -05:00
Albert ARIBAUD
bd851c7a26 Revert "ARM: move interrupt_init to before relocation"
Revert commit 0f5141e9 which causes boards starting in
FLASH to try and write to a FLASH location.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-12-11 21:28:06 +01:00
Albert ARIBAUD
f15ea6e1d6 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	arch/arm/cpu/armv7/rmobile/Makefile
	doc/README.scrapyard

Needed manual fix:
	arch/arm/cpu/armv7/omap-common/Makefile
	board/compulab/cm_t335/u-boot.lds
2013-12-10 22:23:59 +01:00
Andreas Bießmann
bcf9fe37f5 at91: switch coloured LED to gpio API
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-12-09 13:21:47 +01:00
Andreas Bießmann
934e3b5240 at91: redefine legacy GPIO PIN_BASE
In order to get the very same value for legacy pin definitions and new gpio
definitions set the legacy PIN_BASE to 0.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-12-09 13:21:39 +01:00
Andreas Bießmann
9ecc922e75 at91: add new gpio pin definitions
This patch define new names for GPIO pins on at91 devices. Follow up patches
will convert the whole infrastructure to use these new definitions.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Tested-by: Bo Shen <voice.shen@atmel.com>
2013-12-09 13:21:26 +01:00
Albert ARIBAUD
47ed5dd031 arm: keep all sections in ELF file
Current LDS files /DISCARD/ a lot of sections when linking ELF
files, causing diagnostic tools such as readelf or objdump to
produce partial output. Keep all section at link stage, filter
only at objcopy time so that .bin remains minimal.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-12-07 06:53:58 +01:00
Masahiro Yamada
3064d599af ARM: align MVBAR on 32 byte boundary
The lower 5 bit of MVBAR is UNK/SBZP.
So, Monitor Vector Base Address must be 32-byte aligned.
On the other hand, the secure monitor handler does not need
32-byte alignment.

This commit moves ".algin 5" directive to the correct place.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Andre Przywara <andre.przywara@linaro.org>
Acked-by: Andre Przywara <andre.przywara@linaro.org>
2013-12-06 21:03:35 +01:00
Albert ARIBAUD
375a4496ff Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2013-12-06 16:54:42 +01:00
Albert ARIBAUD
c35cf8dc9f Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-12-06 14:26:51 +01:00
Michael Trimarchi
f33b9bd398 arm: omap3: Enable clocks for peripherals only if they are used
This patch change the per_clocks_enable() function used in OMAP3
code to enable peripherals clocks. Only required clock should be
activated. So if the board use the uart(x) as a console we need
to activate it. The Board's config should include define to enable
every subsystem that the board use. For a complete list
of affected peripherals, registers CM_FCLKEN_PER and CM_ICLKEN_PER
should be checked.
Right now the bootloader can enable and disable clocks for:
uart(x) using CONFIG_SYS_NS16550
gpio bank (x) using CONFIG_OMAP3_GPIO_X with X = { 2, 3, 4, 5, 6 }
i2c bus using CONFIG_DRIVER_OMAP34XX_I2C.

Not required gptimer(x) and mcbsp(x) for booting are disabled by default and
are not supported by any define.
Their activation need to included in the per_clocks_enable if the
peripheral is included. Not booting board should enable the peripheral
clock connected to their driver

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2013-12-06 07:02:32 -05:00
Minkyu Kang
d8fa31a71f arm: exynos: adds ifdef for spi boot
This patch fix following errors and warnings

spl_boot.c: In function 'exynos_spi_copy':
spl_boot.c:111:49: error: 'CONFIG_ENV_SPI_BASE' undeclared (first use in this function)
spl_boot.c:111:49: note: each undeclared identifier is reported only once for each function it appears in
spl_boot.c:142:2: error: 'SPI_FLASH_UBOOT_POS' undeclared (first use in this function)
spl_boot.c: In function 'copy_uboot_to_ram':
spl_boot.c:189:28: warning: unused variable 'param' [-Wunused-variable]
spl_boot.c: At top level:
spl_boot.c:107:13: warning: 'exynos_spi_copy' defined but not used [-Wunused-function]

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-12-06 19:07:47 +09:00
Albert ARIBAUD
7988bd4ed6 Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master' 2013-12-06 10:41:49 +01:00
Jaehoon Chung
01322004ec arm: exynos: remove the unused define.
These defines didn't use anywhere.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-05 10:42:04 +09:00
Jaehoon Chung
4bee78f502 arm: exynos/goni: fix the return type for s5p_mmc_init
The "int" type is right.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-05 10:42:04 +09:00
Hardik Patel
675cc77a3a pandaboard: 1/1] ARM:OMAP4+: panda-es: Support Rev B3 Elpida DDR2 RAM
Signed-off-by: Hardik Patel <hardik.patel@volansystech.com>
2013-12-04 11:41:13 -05:00
Viktar Palstsiuk
3558243b6f davinci: fix Master Priority Registers location
MSTPRI0 (Master Priority 0 Register) sits at 0x01C14110 not at
0x01C14114

Signed-off-by: Viktar Palstsiuk <viktar.palstsiuk@promwad.com>
2013-12-04 11:41:13 -05:00
Michael Trimarchi
bcec95bdb4 arm: omap3: Add uart4 omap3 adddress
This patch add the OMAP34XX_UART4 memory address

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2013-12-04 11:41:13 -05:00
Lokesh Vutla
642cdc13f6 ARM: OMAP5+: Remove unnecessary EFUSE settings
Certain EFUSE settings were recommended for the first
four lots of OMAP5 ES1.0 silicon. These are not applicable
for OMAP5 ES2.0 and DRA7 silicon. So removing these EFUSE settings.

Reported-by: Griffis, Brad <bgriffis@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-04 08:12:38 -05:00
Roger Quadros
5afded6a4c ARM: DRA7xx: Add PRCM and Control information for SATA
Adds the necessary PRCM and Control register information for
SATA on DRA7xx.

Signed-off-by: Roger Quadros <rogerq@ti.com>
2013-12-04 08:12:09 -05:00
Roger Quadros
a087a7fb92 ARM: OMAP5: Add SATA platform glue
Add platform glue logic for the SATA controller.

Signed-off-by: Roger Quadros <rogerq@ti.com>
2013-12-04 08:12:09 -05:00
Roger Quadros
8ffcf74bb0 ARM: OMAP5: Add PRCM and Control information for SATA
Adds the necessary PRCM and Control register information for
SATA on OMAP5.

Signed-off-by: Roger Quadros <rogerq@ti.com>
2013-12-04 08:12:09 -05:00
Roger Quadros
9c4b64fb61 ARM: OMAP5: Add Pipe3 PHY driver
Pipe3 PHY is used by SATA, USB3 and PCIe modules. This is
a driver for the Pipe3 PHY.

Signed-off-by: Roger Quadros <rogerq@ti.com>
2013-12-04 08:12:08 -05:00
SRICHARAN R
54d022e76c ARM: DRA7/OMAP5: EMIF: Add workaround for bug 0039
When core power domain hits oswr, then DDR3 memories does not come back
while resuming. This is because when EMIF registers are lost, then the
controller takes care of copying the values from the shadow registers.
If the shadow registers are not updated with the right values, then this
results in incorrect settings while resuming. So updating the shadow registers
with the corresponding status registers here during the boot.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-12-04 08:12:08 -05:00
SRICHARAN R
6c70935d75 ARM: DRA: EMIF: Change DDR3 settings to use hw leveling
Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using
software leveling. This was done since hardware leveling was not
working. Now that the right sequence to do hw leveling is identified,
use it. This is required for EMIF clockdomain to idle and come back
during lowpower usecases.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-12-04 08:12:08 -05:00
SRICHARAN R
39302dcd30 ARM: DRA7: Add is_dra7xx cpu check definition
A generic is_dra7xx cpu check is useful for grouping
all the revisions under that. This is used in the
subsequent patches.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-12-04 08:12:07 -05:00
Tom Rini
39245c8699 am33xx: Stop modifying certain EMIF4D registers
Based on the definitive guide to EMIF configuration[1] certain registers
that we have been modifying (and are documented registers) should be
left in their reset values rather than modified.  This has been tested
on AM335x GP EVM and Beaglebone White.

[1]: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Cc: Javier Martinez Canillas <javier@dowhile0.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Tom Rini <trini@ti.com>
Tested-by: Matt Porter <matt.porter@linaro.org>
2013-12-04 08:11:45 -05:00
Lubomir Popov
87b94a43d6 ARM: OMAP4: Fix bug in omap4470_volts struct
The struct incorrectly referenced SMPS1 for all three power
domains. Fixed this by using SMPS2 and SMPS5 as appropriate.

Add some comments and choose voltage values that correspond
to voltage selection codes.

Signed-off-by: Lubomir Popov <l-popov@ti.com>
2013-12-04 08:11:28 -05:00
Ilya Ledvich
54e7445de9 cm_t335: add cm_t335 board support
Add cm_t335 board directory, config file. Enable build.

Signed-off-by: Ilya Ledvich <ilya@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
[trini: Adapt Makefile]
Signed-off-by: Tom Rini <trini@ti.com>
2013-12-04 08:10:41 -05:00
Chin Liang See
4c54419737 socfpga: Adding Freeze Controller driver
Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during the configuration from propagating to external devices.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2013-12-03 14:38:56 +01:00
Rajeshwari Shinde
347e45d745 exynos: spl: Add a custom spi copy function
This patch implements a custom spi_copy funtion to copy u-boot from SF
to RAM. This is faster then iROM spi_copy funtion as this runs spi at
50Mhz and also in WORD mode of operation.

Changed a printf in pinmux.c to debug just to avoid the compilation
error in SPL.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-03 15:26:33 +09:00
Nobuhiro Iwamatsu
cae83ce515 arm: rmobile: Remove config.mk
Renesas ARM SoCs (R-Mobile, R-Car) are armv7 only.
This drops armv5 supprt from PLATFORM_CPPFLAGS and remove config.mk of
rmobile.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2013-12-03 09:47:15 +09:00
Nobuhiro Iwamatsu
7579751c14 arm: kzm9g: Fix undefined reference to `__aeabi_uldivmod' error
The kzm9g board fails in building with -march=armv7-a.
This fixs this problem by converting to do_div().

-----
USE_PRIVATE_LIBGCC=yes ./MAKEALL kzm9g
...
arch/arm/cpu/armv7/rmobile/librmobile.o: In function `get_time_us':
arch/arm/cpu/armv7/rmobile/timer.c:41: undefined reference to `__aeabi_uldivmod'
arch/arm/cpu/armv7/rmobile/librmobile.o: In function `get_time_ms':
arch/arm/cpu/armv7/rmobile/timer.c:47: undefined reference to `__aeabi_uldivmod'
-----

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
2013-12-03 09:47:08 +09:00
Nobuhiro Iwamatsu
1251e49030 arm: rmobile: Add support koelsch board
The koelsch board has R8A7791, 2GB DDR3-SDRAM, USB,
Quad SPI, Ethernet, and more.

This patch supports the following functions:
 - DDR3-SDRAM
 - SCIF

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
2013-12-03 09:47:04 +09:00
Nobuhiro Iwamatsu
bd0550fc5f arm: rmobile: Add support R8A7791
Renesas R8A7791 is CPU with Cortex-A15.
This supports the basic register definition and GPIO and
framework of PFC.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
2013-12-03 09:46:45 +09:00
Nobuhiro Iwamatsu
1d0e92782f arm: rmobile: Add support R8A7790
Renesas R8A7790 is CPU with Cortex-A7 and A15.
This supports the basic register definition and GPIO and
framework of PFC.

Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com>
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
2013-12-03 09:45:20 +09:00
Nobuhiro Iwamatsu
941b5a40a5 arm: rmobile: Move lowlevel_init.o to taget of each CPU
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2013-12-03 09:42:28 +09:00
Minkyu Kang
771b3ba34c arm: exynos: fix the align for exynos4_power structure
res3 should be 4bytes

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dominik Klein <dominik.klein@gmx.com>
2013-12-03 09:40:24 +09:00
Jaehoon Chung
a85ca22f62 arm: exynos: fix set_mmc_clk for exynos4x12
Fix the set_mmc_clk() for exnos4x12.
If board is exynos4x12, mmc clock should be set to wrong value.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-03 09:39:46 +09:00
Albert ARIBAUD
77524d2c9d Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master' 2013-12-02 16:00:10 +01:00
Heiko Schocher
4535a24c0c arm926ejs, at91: add common phy_reset function
add common phy reset code into a common function.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Jens Scharsig <esw@bus-elektronik.de>
Cc: Sergey Lapin <slapin@ossfans.org>
Cc: Stelian Pop <stelian@popies.net>
Cc: Albin Tonnerre <albin.tonnerre@free-electrons.com>
Cc: Eric Benard <eric@eukrea.com>
Cc: Markus Hubig <mhubig@imko.de>
Acked-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Tested-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Tested-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-12-01 22:38:52 +01:00
Bo Shen
c5e8885aab arm: atmel: sama5d3: spl boot from fat fs SD card
Enable Atmel sama5d3xek boart spl boot support, which can load u-boot
from SD card with FAT file system.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-12-01 22:38:51 +01:00
Bo Shen
9d9289cb31 arm: atmel: add ddr2 initialization function
The MPDDRC supports different type of SDRAM
This patch add ddr2 initialization function

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-12-01 22:38:47 +01:00
Bo Shen
ebfde6db3c arm: atmel: sama5d3: the offset of MULA is 18
The offset of MULA field in PLLA register in sama5d3 is 18,
and the length only 7 bits.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-12-01 22:38:44 +01:00
Bo Shen
e82265701f arm: atmel: sama5d3: correct the error define of DIV
Correct the error define of DIV.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-12-01 22:38:42 +01:00
Bo Shen
184c551b85 arm: atmel: sama5d3: correct the ID for DBGU and PIT
As the DBGU and PIT has its own ID on sama5d3 SoC, while not share
with SYS ID. So, correct them.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-12-01 22:38:39 +01:00
Eric Nelson
3e9cbbbb2b imx-common: remove extraneous semicolon from macro
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-11-27 09:39:21 +01:00
Tom Rini
faca8ff55f Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2013-11-25 10:42:13 -05:00
Albert ARIBAUD
d44a5f5128 Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master' 2013-11-22 10:19:35 +01:00
pekon gupta
2c17e6d1d9 am335x: fix GPMC config for NAND and NOR SPL boot
GPMC controller is common IP to interface with both NAND and NOR flash devices.
Also, it supports max 8 chip-selects, which can be independently connected to
any of the devices.
But ROM code expects the boot-device to be connected to only chip-select[0].
Thus to resolve conflict between NOR and NAND boot. This patch:
- combines NOR and NAND configs spread in board files to common gpmc_init()
- configures GPMC based on boot-mode selected for SPL boot.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2013-11-21 13:33:41 -06:00
pekon gupta
d016dc42ce mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform
BCH8_ECC scheme implemented in omap_gpmc.c driver has following favours
+-----------------------------------+-----------------+-----------------+
|ECC Scheme                         | ECC Calculation | Error Detection |
+-----------------------------------+-----------------+-----------------+
|OMAP_ECC_BCH8_CODE_HW              |GPMC             |ELM H/W engine   |
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |GPMC             |S/W BCH library  |
+-----------------------------------+-----------------+-----------------+

Current implementation limits the BCH8_CODE_HW only for AM33xx device family.
(using CONFIG_AM33XX). However, other SoC families (like TI81xx) also have
ELM hardware module, and can support ECC error detection using ELM.

This patch
- removes CONFIG_AM33xx
	Thus this driver can be reused by all devices having ELM h/w engine.
- adds omap_select_ecc_scheme()
	A common function to handle ecc-scheme related configurations. This
	can be used both during device-probe and via user-space u-boot commads
	to change ecc-scheme. During device probe ecc-scheme is selected based
	on CONFIG_NAND_OMAP_ELM or CONFIG_NAND_OMAP_BCH8
- enables CONFIG_BCH
	S/W library (lib/bch.c) required by OMAP_ECC_BCHx_CODE_HW_DETECTION_SW
  	is enabled by CONFIG_BCH.
- enables CONFIG_SYS_NAND_ONFI_DETECTION
	for auto-detection of ONFI compliant NAND devices
- updates following README doc
	doc/README.nand
	board/ti/am335x/README
	doc/README.omap3

Signed-off-by: Pekon Gupta <pekon@ti.com>
[scottwood@freescale.com: fixed unused variable warning]
Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-11-21 13:33:41 -06:00
pekon gupta
beba5f04f2 mtd: nand: omap: make am33xx/elm.c as common driver for all OMAPx and AMxxxx platforms
ELM hardware engine which is used for ECC error detection, is present on all
latest OMAP SoC (like OMAP4xxx, OMAP5xxx, DRA7xxx, AM33xx, AM43xx). Thus ELM
driver should be moved to common drivers/mtd/nand/ folder so that all SoC
having on-chip ELM hardware engine can re-use it.
This patch has following changes:
- mv arch/arm/include/asm/arch-am33xx/elm.h arch/arm/include/asm/omap_elm.h
- mv arch/arm/cpu/armv7/am33xx/elm.c drivers/mtd/nand/omap_elm.c
- update Makefiles
- update #include <asm/elm.h>
- add CONFIG_NAND_OMAP_ELM to compile driver/mtd/nand/omap_elm.c
	and include in all board configs using AM33xx SoC platform.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2013-11-21 13:33:41 -06:00
Masahiro Yamada
a52f90f074 arm: rmobile: Do not create a symbolic link to sh timer
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2013-11-17 14:11:33 -05:00
Tom Rini
5e995c00f6 TI:omap: Update u-boot-spl.lds for i2c multibus/multiadapter update
In 6789e84 we update u-boot-spl.lds for OMAP to ensure we include
adapter information, as we use i2c during SPL.  However, the regex used
also means we included commands that may have been built.  On omap5_uevm
this leads to a failure as we include the command from the do_tca642x
command, and fail to link.  The fix is to restrict our regex to only the
i2c list parts.

Signed-off-by: Tom Rini <trini@ti.com>
2013-11-15 12:20:33 -05:00
Wu, Josh
618bbbb2e9 ARM: at91: sama5d3: add support for sama5d36 chip
The SAMA5D36 chip is the superset product of SAMA5D3x family.

For detail information please refer to:
  http://www.atmel.com/Microsite/sama5d3/default.aspx

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-11-13 22:18:18 +01:00
Andreas Bießmann
58fd563ffb at91: remove all occourances of CONFIG_AT91_LEGACY
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-11-13 22:17:57 +01:00
Eric Nelson
a31d3efae1 i.MX6DQ/DLS: whitespace: Align IOMUX_PAD column in declarations
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-11-13 10:19:51 +01:00
Eric Nelson
38d8219801 i.MX6DQ/DLS: remove unused pad declarations
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-11-13 10:19:51 +01:00
Eric Nelson
6001c11abc i.MX6DQ: Add Pinmux settings that are present in mainline and Dual-Lite/Solo
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-11-13 10:19:51 +01:00
Eric Nelson
066b2d68a0 i.MX6DQ/DLS: remove useless mux/pad declarations
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-11-13 10:19:50 +01:00
Eric Nelson
10fda48779 i.MX6DQ/DLS: replace pad names with their Linux kernel equivalents
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-11-13 10:19:50 +01:00
Heiko Schocher
6789e84eca i2c, omap24xx: convert driver to new mutlibus/mutliadapter framework
- add omap24xx driver to new multibus/multiadpater support
- adapted all config files, which uses this driver

Tested on the am335x based siemens boards rut, dxr2 and pxm2
posted here:
http://patchwork.ozlabs.org/patch/263211/

Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Tom Rini <trini@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Thomas Weber <weber@corscience.de>
Cc: Tom Rix <Tom.Rix@windriver.com>
Cc: Grazvydas Ignotas <notasas@gmail.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Cc: Luca Ceresoli <luca.ceresoli@comelit.it>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Ilya Yanok <yanok@emcraft.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Nishanth Menon <nm@ti.com>
Cc: Pali Rohár <pali.rohar@gmail.com>
Cc: Peter Barada <peter.barada@logicpd.com>
Cc: Nagendra T S  <nagendra@mistralsolutions.com>
Cc: Michael Jones <michael.jones@matrix-vision.de>
Cc: Raphael Assenat <raph@8d.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-11-13 06:18:17 +01:00
Nikita Kiryanov
f109a6e73e omap3_dss: define DSS_ONOFF
Add DSS_ONOFF to polarity defines

Cc: Tom Rini <trini@ti.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Anatolij Gustschin <agust@denx.de>
2013-11-12 10:11:03 +01:00
Andre Heider
e2788afe67 ARM: bcm2835: add missing mbox overscan response field
Add the missing "right" field to struct bcm2835_mbox_tag_overscan.

Signed-off-by: Andre Heider <a.heider@gmail.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-11-12 09:28:48 +01:00
Heiko Schocher
16678eb40f arm, am33x: make RTC32K OSC enable configurable
As
http://www.denx.de/wiki/view/U-Boot/DesignPrinciples#2_Keep_it_Fast
states:
"Initialize devices only when they are needed within U-Boot"

enable the RTC32K OSC only, if CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is
enabled. Enable this in ti_am335x_common.h, so all boards in mainline
should work as before.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
2013-11-11 12:16:30 -05:00
Albert ARIBAUD
85b8c5c4bf Merge branch 'iu-boot/master' into 'u-boot-arm/master'
Conflicts:
	arch/arm/cpu/arm926ejs/mxs/Makefile
	board/compulab/cm_t35/Makefile
	board/corscience/tricorder/Makefile
	board/ppcag/bg0900/Makefile
	drivers/bootcount/Makefile
	include/configs/omap4_common.h
	include/configs/pdnb3.h

Makefile conflicts are due to additions/removals of
object files on the ARM branch vs KBuild introduction
on the main branch. Resolution consists in adjusting
the list of object files in the main branch version.
This also applies to two files which are not listed
as conflicting but had to be modified:

	board/compulab/common/Makefile
	board/udoo/Makefile

include/configs/omap4_common.h conflicts are due to
the OMAP4 conversion to ti_armv7_common.h on the ARM
side, and CONFIG_SYS_HZ removal on the main side.
Resolution is to convert as this icludes removal of
CONFIG_SYS_HZ.

include/configs/pdnb3.h is due to a removal on ARM side.
Trivial resolution is to remove the file.

Note: 'git show' will also list two files just because
they are new:

	include/configs/am335x_igep0033.h
	include/configs/omap3_igep00x0.h
2013-11-09 22:59:47 +01:00
Masahiro Yamada
643aae1406 include: delete include/linux/config.h
Linux Kernel abolished include/linux/config.h long time ago.
(around version v2.6.18..v2.6.19)

We don't need to provide Linux copatibility any more.

This commit deletes include/linux/config.h
and fixes source files not to include this.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-08 15:25:13 -05:00
Masahiro Yamada
0f0f75774e cosmetic: remove empty lines at the top of file
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-08 09:41:37 -05:00
Albert ARIBAUD
3285d4ca19 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-11-07 09:32:16 +01:00
Radhey Shyam Pandey
b5f05b0634 arm: zynq : Revert TZ_DDR_RAM to secure.
TZ_DDR_RAM on reset is in secure mode.
Since uboot and linux runs in full
TZ privilege secure mode, no need
to set DDR trustzone to non-secure.

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-11-06 09:24:06 +01:00
Michal Simek
c1824ea268 arm: zynq: Do not remap OCM to high address
In case where ps-ddr is not used, do not remap
OCM to high address and keep it from 0x0.
Linux SMP requires to have memory at 0x0.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-11-06 09:23:58 +01:00
Albert ARIBAUD
c0e5dd88c4 Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master' 2013-11-05 20:50:39 +01:00
Roger Meier
c12f941bec at91: add defines for reset type
Signed-off-by: Roger Meier <r.meier@siemens.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-11-04 20:32:39 +01:00
Bo Shen
d9bef0ad2d arm: atmel: at91sam9n12ek: add usb host support
Add usb host support for at91sam9n12ek board.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-11-04 20:32:35 +01:00
Rob Herring
5b6da28352 ARM: versatile: convert to common timer code
Convert versatile to use the commmon timer code.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-11-04 11:24:22 -05:00
Rob Herring
31df9893b9 ARM: tegra: convert to common timer code
Convert tegra to use the commmon timer code.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-11-04 11:24:22 -05:00
Rob Herring
23ab7ee0ff ARM: socfpga: convert to common timer code
Convert socfpga to use the commmon timer code.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-11-04 11:23:45 -05:00
Rob Herring
3dae5b510e ARM: mx25: convert to common timer code
Convert mx25 to use the commmon timer code.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-11-04 11:09:34 -05:00
Rob Herring
9df1bd416d ARM: highbank: convert to common timer code
Convert highbank to use the commmon timer code.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-11-04 11:08:10 -05:00
Rob Herring
f232950f82 config: remove platform CONFIG_SYS_HZ definition part 2/2
Remove platform CONFIG_SYS_HZ definition for configs a-z*.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-11-04 11:06:16 -05:00
SRICHARAN R
42d4f37b79 ARM: OMAP5: DDR3: Change io settings
The change from 0x64656465 to 0x64646464 is to remove the weak pull
enabled on DQS, nDQS lines. This pulls the differential signals in the
same direction which is not intended. So disabling the weak pulls improves
signal integrity.

On the uEVM there are 4 DDR3 devices.  The VREF for 2 of the devices is powered by
the OMAP's VREF_CA_OUT pins.  The VREF on the other 2 devices is powered by the OMAP's
VREF_DQ_OUT pins.  So the net effect here is that only half of the DDR3 devices were being
supplied a VREF!  This was clearly a mistake.  The second change improves the robustness of
the interface and was specifically seen to cure corruption observed at high temperatures
on some boards.

With the above two changes better memory stability was observed with extended
temperature ranges around 100C.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-11-01 15:56:00 -04:00
Minal Shah
a13cbf5f20 dra7xx_evm: Enabled UART-boot mode and add dra7xx_evm_uart3 build
UART booting is supported on this SoC, but via UART3 rather than UART1.
Because of this we must change the board to use UART3 for all console
access (only one UART is exposed on this board and a slight HW mod is
required to switch UARTs).

Signed-off-by: Minal Shah <minal.shah@ti.com>
[trini: Make apply to mainline, reword commit]
Signed-off-by: Tom Rini <trini@ti.com>
2013-11-01 15:56:00 -04:00
Tom Rini
6843918e00 am335x: Enable CONFIG_OMAP_WATCHDOG support
There is a board-specific portion for calling watchdog enable itself, in
main U-Boot.

Signed-off-by: Tom Rini <trini@ti.com>
2013-11-01 15:55:59 -04:00
Tom Rini
155d424a9a am33xx, davinci: Create and use <asm/davinci_rtc.h>
Create a common header file for the RTC IP block that is shared between
davinci and am33xx.

Signed-off-by: Tom Rini <trini@ti.com>
2013-11-01 15:30:22 -04:00
Masahiro Yamada
09ab61c660 ARM: s5pc, exynos: move Samsung ARM SoC specific code under arch/arm/
This patch moves S5PC, EXYNOS specific directory entries
from the toplevel Makefile to arch/arm/cpu/armv7/Makefile
using Kbuild descending feature.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
2013-10-31 13:26:44 -04:00
Masahiro Yamada
3c5edd8ca5 ARM: omap: move OMAP specific code under arch/arm/
This patch moves OMAP specific directory entries
from the toplevel Makefile and spl/Makefile
to arch/arm/cpu/armv7/Makefile using Kbuild descending feature.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
2013-10-31 13:26:44 -04:00
Masahiro Yamada
37d82beb57 ARM: tegra: move Tegra specific code under arch/arm/
This patch moves Tegra specific directory entries
from the toplevel Makefile and spl/Makefile
to arch/arm/cpu/*/Makefile using Kbuild descending feature.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Warren <TWarren@nvidia.com>
2013-10-31 13:26:44 -04:00
Masahiro Yamada
71f84ef073 ARM: imx-common: convert makefiles to Kbuild style
Multiple targets are included in arch/arm/imx-common/Makefile
In order to refactor it,
we need to tweak Makefile and spl/Makefile.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 13:20:39 -04:00
Marek Vasut
a0f9761075 ARM: mxs: Enable DCDC converter for battery boot
In case the board detected sufficient voltage for battery boot,
make sure the DCDC converter is ON and the board is not running
only from linregs, otherwise an instability will be observed.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-10-31 17:54:23 +01:00
Otavio Salvador
0029bc47ad mx6: Remove PAD_CTL_DSE_120ohm from i.MX6DL's IPU1_DI0_PIN4 pin
This removes the PAD_CTL_DSE_120ohm as done for i.MX6Q's IPU1_DI0_PIN4
pin definition and makes it aligned with 3.0.35-4.1.0 and 3.12
mainline kernel.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-10-31 17:54:23 +01:00
Fabio Estevam
357efe69e9 mx5: lowlevel_init: Remove unused macro
setup_wdog macro is not used anywhere, so just remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-10-31 17:54:03 +01:00
Fabio Estevam
4867b634b7 ARM: mx5: Enable L2 cache
Enable L2 cache for improving the system performance.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-10-31 17:54:03 +01:00
Masahiro Yamada
fa8f95084d ARM: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 12:53:39 -04:00
Masahiro Yamada
3d9c84737b arm720t: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 12:53:39 -04:00
Masahiro Yamada
833db7405a arm920t: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 12:53:39 -04:00
Masahiro Yamada
d8769c62c1 arm926ejs: convert makefiles to Kbuild style
Note1:
In arch/arm/cpu/arm926ejs/spear/Makefile
START := start.o
was changed
extra-$(CONFIG_SPL_BUILD) := start.o
because spear/start.o is only used for SPL.

Note2:
START := start.o
was missing from arch/arm/cpu/arm926ejs/mxs/Makefile.
This commit simply adds
extra-$(CONFIG_SPL_BUILD) := start.o

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 12:53:39 -04:00
Masahiro Yamada
4e1aa8437a armv7: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 12:53:39 -04:00
Rajeshwari Shinde
6f0b7caa67 DWMMC: SMDK5420: Disable SMU for eMMC
SMDK5420 has a new Security Management Unit added
for dwmmc driver, hence, configuring the control
registers to support booting via eMMC.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2013-10-31 09:55:33 +02:00
Tom Rini
748bde608a Merge branch 'master' of git://git.denx.de/u-boot-usb 2013-10-21 08:10:36 -04:00
Dan Murphy
3d799c7f5e usb: am437x: Add support for am437x xhci USB host
Add the support for the am437x xhci usb host.

The xHCI host on AM437 is connected to a usb2 phy so need to
add support to enable those clocks.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
2013-10-20 23:42:41 +02:00
Dan Murphy
834e91af43 usb: dra7xx: Add support for dra7xx xhci USB host
Add the support for the dra7xx xhci usb host.
dra7xx does not contain an EHCI controller so the headers
can be removed from the board file.

The xHCI host on dra7xx is connected to a usb2 phy so need to
add support to enable those clocks.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
2013-10-20 23:42:41 +02:00
Dan Murphy
41b667b834 usb: omap: Move the xhci-omap header file to common location
Moving the xhci-omap header to a more global location so that
other code can reference this code.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
2013-10-20 23:42:41 +02:00
Mateusz Zalega
16297cfb2a usb: new board-specific USB init interface
This commit unifies board-specific USB initialization implementations
under one symbol (usb_board_init), declaration of which is available in
usb.h.

New API allows selective initialization of USB controllers whenever needed.

Signed-off-by: Mateusz Zalega <m.zalega@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Lukasz Majewski <l.majewski@samsung.com>
2013-10-20 23:42:40 +02:00
Troy Kisky
7132869d4c mx6: iomux: add GPR1 defines for use with nitrogen6x
Select GPIO1 as the USB OTG ID pin for Nitrogen6x

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-10-20 23:42:40 +02:00
Dan Murphy
2d2358ac15 OMAP5: USB: Add OMAP xHCI file and header
Add the OMAP file for the xHCI Host controller
This code will initilialize the proper components within the
OMAP5 to enable the xHCI host controller.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
2013-10-20 23:42:39 +02:00
Dan Murphy
d861a333da ARM: OMAP5: Add registers and defines for USBOTG SS
Add the prcm registers and the bit definitions to enable the
USB SS port of the OMAP5 device.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
2013-10-20 23:42:39 +02:00
Vivek Gautam
28cfef5f41 exynos5: dts: Add device node for XHCI
Adding device node for xhci host controller to enable
usb 3.0 on exynos5250.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dan Murphy <dmurphy@ti.com>
Cc: Marek Vasut <marex@denx.de>
2013-10-20 23:42:38 +02:00
Vivek Gautam
80c4c5964f arm: exynos: Add methods to control power to USB 3.0 PHY
Adding methods to turn on/off power to USB3.0 type PHY
as and when required by the controller.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dan Murphy <dmurphy@ti.com>
Cc: Marek Vasut <marex@denx.de>
2013-10-20 23:42:38 +02:00
Vivek Gautam
13194f3b5f USB: XHCI: Add xHCI host controller support for Exynos5
This adds driver layer for xHCI controller in Samsung's
exynos5 soc. This interacts with xHCI host controller stack.

Signed-off-by: Vikas C Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dan Murphy <dmurphy@ti.com>
Cc: Marek Vasut <marex@denx.de>
2013-10-20 23:42:38 +02:00
Marek Vasut
77b0e2239a ARM: mxs: Setup stack in JTAG mode
In case the MX23/MX28 is switched into JTAG mode via the BootMode select
switches, the BootROM bypasses the CPU core registers initialization.
This in turn means that the Stack Pointer (SP) register is not set as
it is in every other mode of operation, but instead is only zeroed out.

To prevent U-Boot SPL from crashing in this obscure JTAG mode, configure
the SP to point at the CONFIG_SYS_INIT_SP_ADDR if the SP is zeroed out.

Note that in case the SP is already configured, we must preserve that exact
SP value and must not modify it. This is important since in every other mode
but the JTAG mode, the SPL returns into the BootROM and BootROM in turn loads
U-Boot itself. If the SP were to be corrupted, the BootROM won't be able to
continue it's operation after returned from SPL and the system would crash.

Finally, add the JTAG mode switch identifier, so it's not recognised as
Unknown mode.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
2013-10-17 09:44:20 +02:00
Marek Vasut
6654f33c9b ARM: mxs: tools: Use mkimage for BootStream generation
Now that mkimage can generate an BootStream for i.MX23 and i.MX28,
use the mkimage as a default tool to generate the BootStreams instead
of the elftosb tool. This cuts out another obscure dependency.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-10-17 09:44:20 +02:00
Pierre Aubert
762a88ccf8 mx6: compute PLL PFD frequencies rather than using defines
Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
CC: Stefano Babic <sbabic@denx.de>
2013-10-17 09:44:20 +02:00
Michal Simek
262f08d6ea zynq: Use arch_cpu_init() instead of lowlevel_init()
Zynq lowlevel_init() was implemented in C but stack
pointer is setup after function call in _main().
Move architecture setup to arch_cpu_init() which is call
as the first function in board_init_f() which
already have correct stack pointer.

Reported-by: Sven Schwermer <sven.schwermer@tuhh.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-10-17 08:34:45 +02:00
trem
fac9640895 i2c: mxc: move to new subsystem
Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
2013-10-17 07:20:24 +02:00
Wolfgang Denk
16641d52fc Coding Style cleanup: drop some excessive empty lines
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:54 -04:00
Wolfgang Denk
d4c8aa9cb4 Coding Style cleanup: remove trailing empty lines
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:54 -04:00
Wolfgang Denk
93e1459641 Coding Style cleanup: replace leading SPACEs by TABs
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Drop changes for PEP 4 following python tools]
Signed-off-by: Tom Rini <trini@ti.com>
2013-10-14 16:06:54 -04:00
Wolfgang Denk
3765b3e7bd Coding Style cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:53 -04:00
Dan Murphy
e84b8f6ce0 ARM: omap4-panda: Add MAC address creation for panda
Add a MAC address create based on the OMAP die ID registers.
Then poplulate the ethaddr enviroment variable so that the device
tree alias can be updated prior to boot.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
2013-10-14 16:06:53 -04:00
Dan Murphy
47a4bea6af ARM: omap4: Update sdram setting for panda rev A6
OMAP4 panda rev A6 is a 4430 es2.3 IC with an updated memory
part.

The panda rev A6 uses Elpida 2x4Gb memory and no longer uses Micron
so the timings needs to be updated

Signed-off-by: Dan Murphy <dmurphy@ti.com>
2013-10-14 16:06:52 -04:00
Tom Rini
9f3fe6da27 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-10-08 09:51:48 -04:00
Tom Rini
968294bd7b Merge branch 'master' of git://git.denx.de/u-boot-spi 2013-10-08 09:03:15 -04:00
Rajeshwari Shinde
c4a796329d spi: exynos: Support word transfers
Since SPI register access is so expensive, it is worth transferring data
a word at a time if we can. This complicates the driver unfortunately.

Use the byte-swapping feature to avoid having to convert to/from big
endian in software.

This change increases speed from about 2MB/s to about 4.5MB/s.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-10-08 18:18:12 +05:30
Chin Liang See
5d649d2b08 socfpga: Adding System Manager driver
Adding System Manager driver which will configure the
pin mux for real hardware Cyclone V development kit
(not Virtual Platform)

Signed-off-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Acked-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2013-10-07 19:32:21 +02:00
Albert ARIBAUD
0610a16cf2 omap1510inn: arm925t: remove support
omap1510inn is orphan and has been for years now.
Reove it and, as it was the only arm925t target,
also remove arm925t support.
Update doc/README.scrapyard accordingly.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-10-07 19:25:19 +02:00
Poddar, Sourav
62d206dc31 armv7: hw_data: change clock divider setting.
Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,

f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)

fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-10-07 17:55:51 +05:30
Matt Porter
c97a9b3275 omap5: add qspi support
Add QSPI definitions and clock configuration support.

Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-10-07 17:55:50 +05:30
Andre Przywara
f833e790b4 ARM: virtualization: replace verbose license with SPDX identifier
The original creation of arch/arm/cpu/armv7/{virt-v7.c,nonsec_virt.S}
predates the SPDX conversion, so the original elaborate license
statements sneaked in.
Fix this by replacing them with the proper abbreviation.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-07 08:21:13 -04:00
Enric Balletbo i Serra
94b32f60fe ARM: IGEP0033: Update timing to run DDR at 400MHz.
We can run the DDR at 400MHz, so update the timings for that purpose.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
2013-10-07 07:43:46 -04:00
Tom Rini
f835c77fb7 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-10-04 13:17:48 -04:00
Andre Przywara
d429688754 ARM: extend non-secure switch to also go into HYP mode
For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already are in non-secure state,
HYP mode switching is within short reach.

While doing the non-secure switch, we have to enable the HVC
instruction and setup the HYP mode HVBAR (while still secure).

The actual switch is done by dropping back from a HYP mode handler
without actually leaving HYP mode, so we introduce a new handler
routine in our new secure exception vector table.

In the assembly switching routine we save and restore the banked LR
and SP registers around the hypercall to do the actual HYP mode
switch.

The C routine first checks whether we are in HYP mode already and
also whether the virtualization extensions are available. It also
checks whether the HYP mode switch was finally successful.
The bootm command part only calls the new function after the
non-secure switch.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03 21:28:55 +02:00
Andre Przywara
ba6a169811 ARM: add SMP support for non-secure switch
Currently the non-secure switch is only done for the boot processor.
To enable full SMP support, we have to switch all secondary cores
into non-secure state also.

So we add an entry point for secondary CPUs coming out of low-power
state and make sure we put them into WFI again after having switched
to non-secure state.
For this we acknowledge and EOI the wake-up IPI, then go into WFI.
Once being kicked out of it later, we sanity check that the start
address has actually been changed (since another attempt to switch
to non-secure would block the core) and jump to the new address.

The actual CPU kick is done by sending an inter-processor interrupt
via the GIC to all CPU interfaces except the requesting processor.
The secondary cores will then setup their respective GIC CPU
interface.
While this approach is pretty universal across several ARMv7 boards,
we make this function weak in case someone needs to tweak this for
a specific board.

The way of setting the secondary's start address is board specific,
but mostly different only in the actual SMP pen address, so we also
provide a weak default implementation and just depend on the proper
address to be set in the config file.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03 21:28:51 +02:00
Andre Przywara
bb97545565 ARM: trigger non-secure state switch during bootm execution
To actually trigger the non-secure switch we just implemented, call
the switching routine from within the bootm command implementation.
This way we automatically enable this feature without further user
intervention.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03 21:28:46 +02:00
Andre Przywara
1ef923851a ARM: add C function to switch to non-secure state
The core specific part of the work is done in the assembly routine
in nonsec_virt.S, introduced with the previous patch, but for the full
glory we need to setup the GIC distributor interface once for the
whole system, which is done in C here.
The routine is placed in arch/arm/cpu/armv7 to allow easy access from
other ARMv7 boards.

We check the availability of the security extensions first.

Since we need a safe way to access the GIC, we use the PERIPHBASE
registers on Cortex-A15 and A7 CPUs and do some sanity checks.
Boards not implementing the CBAR can override this value via a
configuration file variable.

Then we actually do the GIC enablement:
a) enable the GIC distributor, both for non-secure and secure state
   (GICD_CTLR[1:0] = 11b)
b) allow all interrupts to be handled from non-secure state
   (GICD_IGROUPRn = 0xFFFFFFFF)

The core specific GIC setup is then done in the assembly routine.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03 21:28:43 +02:00
Andre Przywara
16212b594f ARM: add assembly routine to switch to non-secure state
While actually switching to non-secure state is one thing, another
part of this process is to make sure that we still have full access
to the interrupt controller (GIC).
The GIC is fully aware of secure vs. non-secure state, some
registers are banked, others may be configured to be accessible from
secure state only.
To be as generic as possible, we get the GIC memory mapped address
based on the PERIPHBASE value in the CBAR register. Since this
register is not architecturally defined, we check the MIDR before to
be from an A15 or A7.
For CPUs not having the CBAR or boards with wrong information herein
we allow providing the base address as a configuration variable.

Now that we know the GIC address, we:
a) allow private interrupts to be delivered to the core
   (GICD_IGROUPR0 = 0xFFFFFFFF)
b) enable the CPU interface (GICC_CTLR[0] = 1)
c) set the priority filter to allow non-secure interrupts
   (GICC_PMR = 0xFF)

Also we allow access to all coprocessor interfaces from non-secure
state by writing the appropriate bits in the NSACR register.

The generic timer base frequency register is only accessible from
secure state, so we have to program it now. Actually this should be
done from primary firmware before, but some boards seems to omit
this, so if needed we do this here with a board specific value.
The Versatile Express board does not need this, so we remove the
frequency from the configuration file here.

After having switched to non-secure state, we also enable the
non-secure GIC CPU interface, since this register is banked.

Since we need to call this routine also directly from the smp_pen
later (where we don't have any stack), we can only use caller saved
registers r0-r3 and r12 to not mess with the compiler.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03 21:28:25 +02:00
Andre Przywara
45b940d6f9 ARM: add secure monitor handler to switch to non-secure state
A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state first.
Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine
which switches the CPU to non-secure state by setting the NS and
associated bits.
According to the ARM architecture reference manual this should not be
done in SVC mode, so we have to setup a SMC handler for this.
We create a new vector table to avoid interference with other boards.
The MVBAR register will be programmed later just before the smc call.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03 21:27:11 +02:00
Andre Przywara
d75ba503a9 ARM: prepare armv7.h to be included from assembly source
armv7.h contains some useful constants, but also C prototypes.
To include it also in assembly files, protect the non-assembly
part appropriately.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-10-03 08:25:58 +02:00
Tom Rini
6297872cd5 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-10-02 11:45:22 -04:00
Albert ARIBAUD
f04c537629 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-10-02 14:53:27 +02:00
Albert ARIBAUD
5c8d5b6fc1 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-10-02 08:10:36 +02:00
Eric Nelson
ce7a7f5e6b i.MX6DQ/DLS: Add pad MX6_PAD_GPIO_1__USB_OTG_ID
This patch adds the pad to i.MX6DQ and changes the i.MX6DLS
declaration to match the Linux kernel declaration.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-09-27 13:53:35 +02:00
Pierre Aubert
a0a0dacfe8 mx6: Fix use of improper value in enable_ipu_clock
The value MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET that was used to initialize
the CCGR3 register caused an undefined value for CG0.

Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
CC: Stefano Babic <sbabic@denx.de>
Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-09-27 13:53:35 +02:00
Bo Shen
3668ce3c80 ARM: atmel: add RNDIS gadget support
Add RNDIS gadget support to test atmel usba udc driver

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2013-09-24 17:51:35 +02:00
Bo Shen
ee7e9a3e72 ARM: atmel: correct UDPHS name
Correct the UDPHS name from UDHPS

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-09-24 17:51:35 +02:00
Bo Shen
9e40493fd8 USB: gadget: add atmel usba udc driver
Add atmel usba udc driver support, porting from Linux kernel

The original code in Linux Kernel information is as following

commit e01ee9f509a927158f670408b41127d4166db1c7
Author: Jingoo Han <jg1.han@samsung.com>
Date:   Tue Jul 30 17:00:51 2013 +0900

    usb: gadget: use dev_get_platdata()

    Use the wrapper function for retrieving the platform data instead of
    accessing dev->platform_data directly.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2013-09-24 17:51:35 +02:00
Dani Krishna Mohan
5fb5b15541 Sound: I2S: Replacing I2S1 with I2S0 channel.
This patch makes required changes to make use
of I2S0 channel instead of I2S1 channel on exynos5250.

Signed-off-by: Dani Krishna Mohan <krishna.md@samsung.com>
2013-09-24 09:10:33 -04:00
Dani Krishna Mohan
3dd22a37aa ARM: Added I2S0 clocks for audio
This patch makes the necessary changes for making use of
I2S0 channel instead of I2S1 channel on smdk board. This
changes are done to maintain the uniformity to use I2S0 channel.

Signed-off-by: Dani Krishna Mohan <krishna.md@samsung.com>
2013-09-24 09:10:33 -04:00
Dani Krishna Mohan
b7006a7f5e DTS: Addition of I2S0 channel and replacing I2S1
This patch enables default I2S0 channel.And I2S platform
parameter has been moved to a common file viz exynos5.dtsi.

Signed-off-by: Dani Krishna Mohan <krishna.md@samsung.com>
2013-09-24 09:10:33 -04:00
Jeroen Hofstee
fe1378a961 ARM: use r9 for gd
To be more EABI compliant and as a preparation for building
with clang, use the platform-specific r9 register for gd
instead of r8.

note: The FIQ is not updated since it is not used in u-boot,
and under discussion for the time being.

The following checkpatch warning is ignored:
WARNING: Use of volatile is usually wrong: see
Documentation/volatile-considered-harmful.txt

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-09-23 18:00:02 +02:00
Jeroen Hofstee
a81872ff27 ARM,relocate: do not use r9
r9 is a platform-specific register in ARM EABI and not per
definition a general purpose register. Do not use it while
relocating so it can be used for gd.

cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2013-09-23 17:58:24 +02:00
Masahiro Yamada
3102274d8b ARM: refactor compiler options in config.mk
Every ARM cpu config.mk (arch/arm/cpu/{CPUDIR}/config.mk) defines:

PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float

So, this patch moves the common compiler options to arch/arm/config.mk.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-09-23 17:03:05 +02:00
Michal Simek
7ba69b7dcc arm: zynq: Fix timer loadaddress
Reload address was written to the counter register
instead of load register.
The problem happens when timer expires but never
reload to ~0UL (it is downcount timer).

Reported-by: Stephen MacMahon <stephenm@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-09-23 16:26:32 +02:00
Jeroen Hofstee
373d798394 arm: prevent using movt/movw address loads
The movt/movw instruction can be used to hardcode an
memory location in the instruction itself. The linker
starts complaining about this if the compiler decides
to do so: "relocation R_ARM_MOVW_ABS_NC against `a local
symbol' can not be used" and it is not support by U-boot
as well. Prevent their use by requiring word relocations.
This allows u-boot to be build at other optimalization
levels then -Os.

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: TigerLiu@viatech.com.cn
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Simon Glass <sjg@chromium.org>
2013-09-23 14:36:50 +02:00
Lokesh Vutla
e22cc0cf13 ARM: OMAP5: Avoid writing into LDO SRAM bits
Writing magic bits into LDO SRAM was suggested only for OMAP5432
ES1.0. Now these are no longer applicable. Moreover these bits should
not be overwritten as they are loaded from EFUSE. So avoid
writing into these registers.

Boot tested on OMAP5432 ES2.0

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-09-20 16:57:40 -04:00