Commit graph

77 commits

Author SHA1 Message Date
Simon Glass
941338725d common: Move relocate_code() to init.h
This is an init function so move it out of the common header. Avoid using
the typedef so that we don't have to include the global_data header file.

Also tidy up the function style in comments while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17 13:26:49 -05:00
Udit Agarwal
bef1845404 freescale/powerpc: Rename the config CONFIG_SECURE_BOOT name
Rename the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid
conflicts with UEFI secure boot.

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 16:32:08 +05:30
Joakim Tjernlund
45e81f9ab3 mpc85xx: Add support for -msingle-pic-base
-msingle-pic-base is a new gcc(from 4.6) option for ppc and
it reduces the size of my u-boot with about 4-5 KB.
While at it, add -fno-jump-tables too to save a
few more bytes.

e5500 core:
size u-boot.bef
   text	   data	    bss	    dec	    hex	filename
 473043	  23772	 307104	 803919	  c444f	u-boot.bef
size u-boot.aft
   text	   data	    bss	    dec	    hex	filename
 453195	  23772	 307104	 784071	  bf6c7	u-boot.aft

e500 core:
size u-boot.bef
   text	   data	    bss	    dec	    hex	filename
 292998	  17868	  24968	 335834	  51fda	u-boot.bef
size u-boot.aft
   text	   data	    bss	    dec	    hex	filename
 288002	  17868	  24968	 330838	  50c56	u-boot.aft

Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-23 10:48:48 -08:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Andy Yan
2b71d098ee powerpc: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot
Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Christophe Leroy
ba2c5a5c9d powerpc: move get_pvr() and get_svr() into C
Avoid unnecessary assembly functions when they can easily be written
in C.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-22 22:22:51 -04:00
Ruchika Gupta
668ec87f52 powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram
For E6500 cores, L2 cache has been used as init_ram. L1 cache is a
write through cache on E6500.If lines are not locked in both L1 and
L2 caches, crashes are observed during secure boot. This patch locks/
unlocks both L1 and L2 cache to prevent the crash.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17 09:03:30 -07:00
Mark Marshall
2ec70961e7 powerpc: mpc85xx: Use symbolic names for cache control bits
We should use the symbolic names for the cache control bits.

Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at>
Reviewed-by: Thomas Graziadei <thomas.graziadei@omicronenergy.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-31 17:51:34 -08:00
York Sun
10343403af powerpc: QEMU_E500: Remove macro CONFIG_QEMU_E500
Replace CONFIG_QEMU_E500 with ARCH_QEMU_E500 in Kconfig and
clean up existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:12 -08:00
York Sun
23b36a7d48 powerpc: MPC8569: Remove macro CONFIG_MPC8569
Replace CONFIG_MPC8569 with ARCH_MPC8569 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:06 -08:00
Sumit Garg
aa36c84edf powerpc/mpc85xx: T104x: Add nand secure boot target
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In non-secure boot scenario from NAND, this address will map to CPC
configured as SRAM. But in case of secure boot, this default address
always maps to IBR (Internal Boot ROM).
The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G
address space i.e. 0x0 - 0xDFFFFFFF.

For secure boot target from NAND, the text base for SPL is kept same as
non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will
be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000)
As a the virtual and physical address of CPC would be different. The
virtual address 0xFFFx_xxxx needs to be mapped to physical address
0xBFFx_xxxx.

Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000
and update DCFG SCRTACH1 register with location of Header required for
secure boot.

The changes are similar to
commit 467a40dfe3
    powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041

While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC
is only 256K and thus SPL framework is used.
The changes are only applicable for SPL U-Boot running out of CPC SRAM
and not the next level U-Boot loaded on DDR.

Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-21 11:09:34 -07:00
Aneesh Bansal
82eda68444 powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cache
While enabling L2 cache, the value of L2PE (L2 cache parity/ECC
error checking enable) must not be changed while the L2 cache is
enabled.
So, L2PE must be set before enabling L2 cache.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-24 10:31:21 -07:00
mario.six@gdsys.cc
5068946120 powerpc: mpc85xx: Enable pre-relocation malloc for MPC85xx
To enable DM on MPC85xx, we need pre-relocation malloc, which is
implemented in this patch.

We also make sure that the IVORs are always 4-aligned on e500 to prevent
alignment exceptions caused by code changes in start.S.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Cc: York Sun <york.sun@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-04-08 15:42:10 -07:00
York Sun
2becdc6f9d powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ram
MPC85xx has been using locked L1 cache as init_ram. L1 cache is a write
through cache on E6500. L2 cache is enabled to to hold the data. This
patch locks/unlocks L2 cache to ensure no data cast out from L2 cache.

Signed-off-by: York Sun <yorksun@freescale.com>
Reported-by: Jeffery Zhu <Jefferry.Zhu@freescale.com>
2015-09-01 20:42:54 -05:00
Aneesh Bansal
467a40dfe3 powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
Secure Boot Target is added for NAND for P3041.
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF.

In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on SRAM configured
at address 0xBFF00000.
In the U-Boot code, TLB entries are created to map the virtual address
0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31 08:50:18 -07:00
Scott Wood
e1bfd1c6b7 powerpc/mpc85xx: Use GOT when loading IVORs post-relocation
Commit 96d2bb952b ("powerpc/mpc85xx: Don't relocate exception vectors")
simplified IVOR initialization a bit too much, failing to use the
post-relocation offset.  This doesn't cause a problem with normal NOR
boot, in which both the pre-relocation and post-relocation addresses
are 64 KiB aligned.  However, if TEXT_BASE is only 4 KiB aligned, such
as for NAND/SD/etc. boot on some targets, as well as the QEMU target,
the post-relocation address will not be the same in the lower 16 bits,
as reserve_uboot() ensures that the relocation address is always 64
KiB aligned even if the pre-relocation address was not.

Use the GOT to get the proper post-relocation offsets.

Fixes: 96d2bb952b ("powerpc/mpc85xx: Don't relocate exception vectors")
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
Tested-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:23:18 -07:00
Scott Wood
d87a2ad108 powerpc/mpc85xx: Remove some dead code
U-Boot does not have system calls (the services it exposes to
standalone commands use a different mechanism), so the syscall handler
is dead code.  It's also broken code, as it assumes it is located at
0xc00 -- while even before the patch to stop relocating exception
vectors to 0, U-Boot had the syscall at 0x900.

The critical and machine check return paths are never called -- the
regular exception return path is used instead, which works because
xSRR0/1 have already been saved and can be restored via the regular
SRR0/1 (we don't care too much in U-Boot about taking a critical/mcheck
inside another exception prolog/epilog).

Also remove a few other small unused functions.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-20 10:15:29 -07:00
Scott Wood
96d2bb952b powerpc/mpc85xx: Don't relocate exception vectors
Booke does not require exception vectors to be located at address zero.
U-Boot was doing so anyway, simply because that's how it had been done
on other PPC.  The downside of this is that once the OS is loaded to
address zero, the exception vectors have been overwritten -- which
makes it difficult to diagnose a crash that happens after that point.

The IVOR setup and trap entry code is simplified somewhat as a result.

Also, there is no longer a need to align individual exceptions on 0x100
byte boundaries.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-20 10:15:29 -07:00
York Sun
701e640145 powerpc/mpc85xx: Fix boot_flag for calling board_init_f()
baord_init_f takes one argument, boot_flag. It has not been used for
powerpc, until recently changing to use generic board architecture.
The boot flag is added as a return value from cpu_init_f().

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alexander Graf <agraf@suse.de>
2014-05-13 08:31:22 -07:00
Alexander Graf
a6c46b994d PPC 85xx QEMU: Don't use HID1
For the QEMU machine type, we can plug in either e500v2, e500mc, e5500
or e6500 style cores into the system. U-boot has to work with all of them.

So avoid using HID1 which is not available on e500mc systems to make sure
we don't trap on it.

Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-13 08:26:56 -07:00
Prabhakar Kushwaha
651fcf6019 powerpc:Add support of SPL non-relocation
Current SPL code base has BSS section placed after reset_vector. This means
they have to relocate to use the global variables. This put an implicit
requirement of having SPL size = Memory/2.

To avoid relocation:
	- Move bss_section within SPL range
	- Modify relocate_code()

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:50 -07:00
Prabhakar Kushwaha
b26df185c3 powerpc/mpc85xx: Move LAW_EN define outside of config
LAW_EN is only defined if CONFIG_SYS_CCSRBAR_DEFAULT is not equal to
CONFIG_SYS_CCSRBAR_PHYS. in SPL framework CCSRBAR is not relocated hence
both are same. This cause compilation error.

So LAW_EN define outside of configs

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:50 -07:00
Aneesh Bansal
fb4a2409b4 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS
Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
   So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
   code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
   keeping area. This configuration is to be disabled once in uboot.
   Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
   As a result cache invalidation function was getting skipped in
   case CPC is configured as SRAM.This was causing random crashes.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:46 -07:00
Aneesh Bansal
f978f7c203 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDS
Add NOR, SPI and SD secure boot targets for BSC9132QDS.

Changes:
- Debug TLB entry is not required for Secure Boot Target.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:46 -07:00
Alexander Graf
fa08d39517 PPC 85xx: Add qemu-ppce500 machine
For KVM we have a special PV machine type called "ppce500". This machine
is inspired by the MPC8544DS board, but implements a lot less features
than that one.

It also provides more PCI slots and is supposed to be enumerated by
device tree only.

This patch adds support for the generic ppce500 machine and tries to
rely solely on device tree for device enumeration.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:45 -07:00
Alexander Graf
46a346834b PPC: 85xx: Remove IVOR reset
There is no need to set IVORs to anything but their default values,
so let's leave them where they are.

Suggested-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
[York Sun: Add back $(obj)start.S section in mpc8572ds/Makefile]
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:45 -07:00
Masahiro Yamada
d937326ffc Remove obsolete _LINUX_CONFIG_H macro
Commit 643aae1406
deleted include/linux/config.h but missed to
delete _LINUX_CONFIG_H macro.
It is no longer used at all.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:07 -05:00
Dave Liu
24936ed1c9 powerpc/corenet: CPC1 speculation disable
In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable
CPC1 speculation and keep it till relocation. Otherwise, speculation
transactions will go to DDR controller, it will cause problem.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-12-04 14:54:10 -08:00
Prabhakar Kushwaha
e982746844 powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2
CHASSIS2 architecture never defines type of L2 cache present in SoC.
 it is dependent upon the core present in the SoC.
 for example,
    - e6500 core has L2 cluster (Kibo)
    - e5500 core has Backside L2 Cache

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-10-16 16:13:11 -07:00
Wolfgang Denk
3765b3e7bd Coding Style cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:53 -04:00
York Sun
954a1a4776 powerpc/mpc85xx: Add workaround for erratum A-005125
In a very rare condition, a system hang is possible when the e500 core
initiates a guarded load to PCI / PCIe /SRIO performs a coherent write
to memory. Please refer to errata document for more details. This erratum
applies to the following SoCs and their variants, if any.

BSC9132
BSC9131
MPC8536
MPC8544
MPC8548
MPC8569
MPC8572
P1010
P1020
P1021
P1022
P1023
P2020
C29x

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
2013-09-10 14:31:47 -07:00
Liu Gang
17b8614754 powerpc/srio-pcie-boot: Avoid the NOR_BOOT macro when boot from SRIO/PCIE
When a board (slave) boots from SRIO/PCIE, it would get the instructions
from a remote board (master) by SRIO/PCIE interface, and the slave's
u-boot image should be built with the

	SYS_TEXT_BASE=0xFFF80000;

So the u-boot of the slave should avoid the NOR_BOOT branch at the
booting stage.

For example, when a P2041RDB boots from SRIO/PCIE, it will set TLB
entry 15 from base address "CONFIG_SYS_MONITOR_BASE & 0xffc00000",
and with the 4M size as the boot window in NOR_BOOT branch. Because
the CONFIG_SYS_MONITOR_BASE = CONFIG_SYS_TEXT_BASE = 0xFFF80000, so
the TLB entry will be from base address 0xffc00000 and with 4M size.

Then the u-boot will set TLB entry 14 from base address
"CONFIG_SYS_INIT_RAM_ADDR", and with the 16K size as the initial
stack window. For the P2041RDB platform, the CONFIG_SYS_INIT_RAM_ADDR
= 0xffd00000. So the TLB entry 14 and 15 will be in confliction.

There will be right TLB entries configurations when avoid the
NOR_BOOT branch and set the boot window from 0xfff00000 with 1M
size space.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
2013-08-09 12:41:40 -07:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Ying Zhang
67ad0d52df powerpc/mpc85xx: modify the functionality clear_bss and aligning the end address of the BSS
There will clear the BSS in the function clear_bss(), the reset address of
the BSS started from the __bss_start, and increased by four-byte increments,
finally stoped depending on the address is equal to the _bss_end. If the end
address __bss_end is not alignment to 4byte, it will be an infinite loop.

1. The reset action stoped depending on the reset address is greater
than or equal the end address of the BSS.
2. The end address of the BSS should be 4byte aligned. Because the reset unit
is 4 Bytes.

This patch is on top of the patch "powerpc/mpc85xx: support application
without resetvec segment in the linker script".

Signed-off-by: Ying Zhang <b40530@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:50 -05:00
York Sun
a71d45d706 powerpc/mpc85xx: Clear L1 D-cache lock
dcbi instruction has been used to clear D-cache lock. However, the cache
lock is persistent for e6500 core. Use dcblc to clear the lock explicitly.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:14 -05:00
James Yang
9cd95ac74a Add e6500 L2 replacement policy selection
This is compile-time config.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:10 -05:00
James Yang
c416faf84f Enable L2 cache parity/ECC error checking
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:09 -05:00
Andy Fleming
3e4c3137d6 e6500: Move L1 enablement after L2 enablement
The L1 D-cache on e6500 is write-through. This means that it's not
considered a good idea to have the L1 up and running if the L2 is
disabled. We don't actually *use* the L1 until after the L2 is
brought up on e6500, so go ahead and move the L1 enablement after
that code is done.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:25 -05:00
Andy Fleming
cd7ad62996 powerpc/mpc85xx: Add definitions for HDBCR registers
Makes it a bit easier to see if we've properly set them. While
we're in there, modify the accesses to HDBCR0 and HDBCR1  to actually
use those definitions.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:24 -05:00
Simon Glass
3929fb0a14 Replace __bss_end__ with __bss_end
Note this is a tree-wide change affecting multiple architectures.

At present we use __bss_start, but mostly __bss_end__. This seems
inconsistent and in a number of places __bss_end is used instead.

Change to use __bss_end for the BSS end symbol throughout U-Boot. This
makes it possible to use the asm-generic/sections.h file on all
archs.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:13:54 -04:00
Scott Wood
31d084ddda powerpc/mpc85xx: add support for MMUv2 page sizes
e6500 implements MMUv2 and supports power-of-2 page sizes rather than
power-of-4.  Add support for such pages.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:15 -06:00
Scott Wood
4b919725b6 spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL
cpu_init_nand.c is renamed to spl_minimal.c as it is not really NAND-specific.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
v2: factor out START, and change cpu_init_nand.c to spl_minimal.c
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:24 -06:00
Scott Wood
7f0a22ff25 powerpc/mpc85xx: fix TLB alignment
In the RAMBOOT/SPL case we were creating a TLB entry starting at
CONFIG_SYS_MONITOR_BASE, and just hoping that the base was properly
aligned for the TLB entry size.  This turned out to not be the case
with NAND SPL because the main U-Boot starts at an offset into the image
in order to skip the SPL itself.

Fix the TLB entry to always start at a proper alignment.  We still assume that
CONFIG_SYS_MONITOR_BASE doesn't start immediately before a large-page boundary
thus requiring multiple TLB entries.

Signed-off-by: Scott Wood <scottwood@frescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:22 -06:00
Scott Wood
f545d300b0 powerpc/mpc85xx: move debug tlb entry after TLB is in known state
Previously, in many if not all configs we were creating overlapping TLB entries
which is illegal.  This caused a crash during boot when moving p2020rdb NAND SPL
into L2 SRAM.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Prabhakar Kushwaha <prabhakar@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
--
Prabhakar, please test that debug still works.
2012-11-26 15:41:20 -06:00
York Sun
6d2b9da19c powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500
Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.

Setup stash id for L1 cache as (coreID) * 2 + 32 + 0
Setup stash id for L2 cache as (cluster) * 2 + 32 + 1
Stash id for L2 is only set for Chassis 2.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:15 -05:00
York Sun
69c7826759 powerpc/mpc85xx: Introduce new macros to add and delete TLB entries
These assembly macros simplify codes to add and delete temporary TLB entries.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:15 -05:00
Scott Wood
3ea21536d7 powerpc/85xx: clear out TLB on boot
Instead of just shooting down the entry that covers CCSR, clear out
every TLB entry that isn't the one that we're executing out of.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:57 -05:00
Scott Wood
33eee330cc powerpc/fsl-corenet: work around erratum A004510
Erratum A004510 says that under certain load conditions, modified
cache lines can be discarded, causing data corruption.

To work around this, several CCSR and DCSR register updates need to be
made in a careful manner, so that there is no other transaction in
corenet when the update is made.

The update is made from a locked cacheline, with a delay before to flush
any previous activity, and a delay after to flush the CCSR/DCSR update.
We can't use a readback because that would be another corenet
transaction, which is not allowed.

We lock the subsequent cacheline to prevent it from being fetched while
we're executing the previous cacheline.  It is filled with nops so that a
branch doesn't cause us to fetch another cacheline.

Ordinarily we are running in a cache-inhibited mapping at this point, so
we temporarily change that.  We make it guarded so that we should never
see a speculative load, and we never do an explicit load.  Thus, only the
I-cache should ever fill from this mapping, and we flush/unlock it
afterward.  Thus we should avoid problems from any potential cache
aliasing between inhibited and non-inhibited mappings.

NOTE that if PAMU is used with this patch, it will need to use a
dedicated LAW as described in the erratum.  This is the responsibility
of the OS that sets up PAMU.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:54 -05:00
Joakim Tjernlund
89f4289958 mpc85xx: Initial SP alignment is wrong.
PowerPC mandates SP to be 16 bytes aligned.
Furthermore, a stack frame is added, pointing to the reset vector
which may in the way when gdb is walking the stack because
the reset vector may not accessible depending on emulator settings.
Also use a temp register so gdb doesn't pick up intermediate values.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-22 16:07:42 -05:00
Prabhakar Kushwaha
d16a37b864 powerpc/85xx:Fix NAND code base to support debugger
Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR
+ IVOR15 should be valid fetchable OP code address.

As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to
any fetchable valid data

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:30:30 -05:00