Commit graph

5 commits

Author SHA1 Message Date
Simon Glass
f7ae49fc4f common: Drop log.h from common header
Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:18 -04:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Hou Zhiqiang
71fe22256c fsl: serdes: ensure accessing the initialized maps of serdes protocol
Up to now, the function is_serdes_configed() doesn't check if the map
of serdes protocol is initialized before accessing it. The function
is_serdes_configed() will get wrong result when it was called before
the serdes protocol maps initialized. As the first element of the map
isn't used for any device, so use it as the flag to indicate if the
map has been initialized.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14 14:06:49 -07:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Prabhakar Kushwaha
35fe948e3b powerpc/mpc85xx: Add BSC9132/BSC9232 processor support
The BSC9132 is a highly integrated device that targets the evolving
 Microcell, Picocell, and Enterprise-Femto base station market subsegments.

 The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
 core technologies with MAPLE-B2P baseband acceleration processing elements
 to address the need for a high performance, low cost, integrated solution
 that handles all required processing layers without the need for an
 external device except for an RF transceiver or, in a Micro base station
 configuration, a host device that handles the L3/L4 and handover between
 sectors.

 The BSC9132 SoC includes the following function and features:
    - Power Architecture subsystem including two e500 processors with
	512-Kbyte shared L2 cache
    - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
	cache
    - 32 Kbyte of shared M3 memory
    - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
      Processing (MAPLE-B2P)
    - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
      ECC), up to 1333 MHz data rate
    - Dedicated security engine featuring trusted boot
    - Two DMA controllers
         - OCNDMA with four bidirectional channels
         - SysDMA with sixteen bidirectional channels
    - Interfaces
        - Four-lane SerDes PHY
	    - PCI Express controller complies with the PEX Specification-Rev 2.0
        - Two Common Public Radio Interface (CPRI) controller lanes
	    - High-speed USB 2.0 host and device controller with ULPI interface
        - Enhanced secure digital (SD/MMC) host controller (eSDHC)
	    - Antenna interface controller (AIC), supporting four industry
		standard JESD207/four custom ADI RF interfaces
       - ADI lanes support both full duplex FDD support & half duplex TDD
       - Universal Subscriber Identity Module (USIM) interface that
	   facilitates communication to SIM cards or Eurochip pre-paid phone
	   cards
       - Two DUART, two eSPI, and two I2C controllers
       - Integrated Flash memory controller (IFC)
       - GPIO
     - Sixteen 32-bit timers

Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:14 -06:00