Commit graph

838 commits

Author SHA1 Message Date
Patrick Delaunay
c3600e1f92 stm32mp1: add FUSE command support
Add support of fuse command (read/write/program/sense)
on bank 0 to access to BSEC SAFMEM (4096 OTP bits).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26 18:19:18 -04:00
Michal Simek
1d6c54ecb3 arm: zynqmp: Add ZynqMP minimal R5 support
Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot.
This patch is adding minimal support to get U-Boot boot.
U-Boot on R5 runs out of DDR with default configuration that's why
DDR needs to be partitioned if there is something else running on arm64.
Console is done via Cadence uart driver and the first Cadence Triple
Timer Counter is used for time.

This configuration with uart1 was tested on zcu100-revC.

U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200)

Model: Xilinx ZynqMP R5
DRAM:  512 MiB
WARNING: Caches not enabled
MMC:
In:    serial@ff010000
Out:   serial@ff010000
Err:   serial@ff010000
Net:   Net Initialization Skipped
No ethernet found.
ZynqMP r5>

There are two ways how to run this on ZynqMP.
1. Run from ZynqMP arm64
tftpb 20000000 u-boot-r5.elf
setenv autostart no && bootelf -p 20000000
cpu 4 disable && cpu 4 release 10000000 lockstep
or
cpu 4 disable && cpu 4 release 10000000 split

2. Load via jtag when directly to R5

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:38:23 +02:00
Alexander Graf
b123aff26f MAINTAINERS: Declare tools/zynqmp* as Xilinx maintained
The zynqmpimage.c and the new zynqmpbif.c files are all maintained by
Xilinx for the Zynq platforms. Let's match them accordingly
in the MAINTAINERS file.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Michal Simek
6de7a5b907 MAINTAINERS: zynqmp: Point to proper zynqmp folder
Point to Zynqmp arm64 cpu folder not to Zynq arm32.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Michal Simek
72c37d1221 timer: Add Cadence TTC timer counter support
This driver was tested on Xilinx ZynqMP SoC.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Fabio Estevam
08ae21af96 MAINTAINERS: Switch nxp.com domain
freescale.com domain is no longer reachable, so switch the
maintainers' emails to nxp.com domain instead.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-05-01 22:38:10 -04:00
Eugeniy Paltsev
4006200d49 ARC: Update ARC architecture maintainers
Update ARC architecture maintainers and add
uboot-snps-arc@synopsys.com mailing list.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-04-17 20:52:17 +03:00
Heinrich Schuchardt
b57aaa07f2 MAINTAINERS: ARM STM STM32MP: correct file paths
Provide correct file paths.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-04-10 15:19:14 -04:00
Tom Rini
2600df4f8e Xilinx changes for v2018.05-rc2
- Various DT changes and sync with mainline kernel
 - Various defconfig updates
 - Add SPL init for zcu102 revA
 - Add new zynqmp boards zcu100/zcu104/zcu106/zcu111/zc12XX
   and zc1751-dc3
 - Net fixes - xlnx,phy-type
 - 64bit axi ethernet support
 - arasan: Fix nand write issue
 - fpga fixes
 - Maintainer file updates
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Merge tag 'xilinx-for-v2018.05-rc2' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.05-rc2

- Various DT changes and sync with mainline kernel
- Various defconfig updates
- Add SPL init for zcu102 revA
- Add new zynqmp boards zcu100/zcu104/zcu106/zcu111/zc12XX
  and zc1751-dc3
- Net fixes - xlnx,phy-type
- 64bit axi ethernet support
- arasan: Fix nand write issue
- fpga fixes
- Maintainer file updates
2018-04-09 11:06:21 -04:00
Heinrich Schuchardt
23e7e6b6b9 MAINTAINERS: ZYNQMP: correct entries
Replace references to non-existent file.

Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-09 08:02:50 +02:00
Michal Simek
3d14228f1b MAINTAINERS: Fix zynqmp clock driver path
Fix c&p error from Zynq.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-09 08:02:50 +02:00
Heinrich Schuchardt
1914e5b5d8 efi_loader: provide new doc/README.uefi
Provides information about

- usage of the bootefi command
- overview of UEFI
- interaction between U-Boot and EFI drivers

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-04-04 11:00:06 +02:00
Philipp Tomsich
47b8583f58 rockchip: mmc: update MAINTAINERS
The Rockchip-specific wrappers to the DW-MMC and the SDHCI driver
were not covered as part of what's maintained by the architecture
maintainers.  Add them here.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-28 23:47:07 +02:00
Michal Simek
8ae3d0b50c MAINTAINERS: Fix Zynq/ZynqMP and Microblaze fragments
Fix my fragments to list all files in the repo.

Also fix path to for Xilinx Zynq SoC (mach-zynq)
It should be the part of
"ARM: zynq: move SoC sources to mach-zynq"
(sha1: 0107f24036)

And cover dts files in board MAINTAINERS files.

Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:36:15 +01:00
Stefan Roese
5cf32518ea MAINTAINERS: Remove unused ppc4xx entry
ppc4xx support was removed some time ago. Lets remove the now unused
entry in MAINTAINERS as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-03-19 16:14:23 -04:00
Patrick Delaunay
a6151916cb clk: add driver for stm32mp1
add RCC clock driver for STMP32MP157
- base on driver model = UCLASS_CLK
- support ops to enable, disable and get rate
  of all SOC clock needed by U-Boot

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-19 16:14:22 -04:00
Patrick Delaunay
e70f70aa65 ram: stm32mp1: add driver
Add driver and binding for stm32mp1 ddr controller and phy

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-19 16:14:21 -04:00
Patrick Delaunay
2514c2d0e6 arm: stm32: add new architecture for STM32MP family
- add new arch stm32mp for STM32 MPU/Soc based on Cortex A
- support for stm32mp157 SOC
- SPL is used as first boot stage loader
- using driver model for all the drivers, even in SPL
- all security feature are deactivated (ETZC and TZC)
- reused STM32 MCU drivers when it is possible

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-19 16:14:21 -04:00
Heinrich Schuchardt
02c5e891a3 MAINTAINERS: TI SYSTEM SECURITY: remove invalid file
Remove a link to a non-existent file.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Andrew F. Davis <afd@ti.com>
2018-03-16 14:54:14 -04:00
Heinrich Schuchardt
c133915eb2 MAINTAINERS: ARM TI: remove invalid paths
Remove non-existing paths.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-03-16 14:54:14 -04:00
Heinrich Schuchardt
cbc4423e87 MAINTAINERS: ARM SAMSUNG: remove invalid paths
Remove non-existing directories.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2018-03-16 14:54:14 -04:00
Heinrich Schuchardt
18fa6230ce MAINTAINERS: FLATTENED DEVICE TREE: correct maintained path
Change due to commit b08c8c4870 ("libfdt: move headers to
<linux/libfdt.h> and <linux/libfdt_env.h>")

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-03-16 14:54:14 -04:00
Heinrich Schuchardt
0f8525f5c1 MAINTAINERS: ARM HISILICON: correct maintained path
Fix an incorrect path.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-03-16 14:54:14 -04:00
Heinrich Schuchardt
f7b2849a47 MAINTAINERS: ARM FREESCALE IMX: remove invalid path
arch/arm/cpu/armv7/mx*/ does not relate to any existing directory.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-03-16 14:54:14 -04:00
Madan Srinivas
f274f26566 defconfig: k2l_hs_evm: Add k2l_hs_evm_defconfig
Adds a dedicated defconfig to build TI K2L secure
devices and updates MAINTAINERS.

k2l_hs_evm_defconfig is created from the k2l_evm_defconfig
and removes support for SPL, as SPL is not supported on K2
HS devices. Corrects SYS_TEXT_BASE for HS devices.

Also adds TI_SECURE_DEVICE and FIT_IMAGE_POST_PROCESS to
include support for secure image creation and authentication

Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Andrew F. Davis <afd@ti.com>
2018-03-16 09:42:41 -04:00
Heinrich Schuchardt
b7d6e0abab MAINTAINERS: bring sections into alphabetic order
NETWORK should be after NAND_FLASH.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-03-09 12:31:07 -05:00
Heinrich Schuchardt
4ef17f9cbe MAINTAINERS: bring sections into alphabetic order
POWER should be after ONENAND

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-03-05 10:16:30 -05:00
Philipp Tomsich
3f56552227 rockchip: video: update MAINTAINERS
The video drivers (VOP, HDMI encoder, LVDS encoder, MIPI encoder) for
Rockchip SOCs are self-contained and are mainly impacted by other
changes in the architecture support (e.g. pinctrl, clocking, etc).

Let's add these to the list of files maintained as part of the
Rockchip port.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2018-02-23 20:49:07 +01:00
Heinrich Schuchardt
f3b5056c4e efi_loader: split README.efi into two separate documents
README.efi describes two different concepts:
* U-Boot exposing the UEFI API
* U-Boot running on top of UEFI.

This patch splits the document in two.
Religious references are removed.

The separation of the concepts makes sense before detailing the internals
of U-Boot exposing the UEFI API in a future patch.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-02-10 00:24:00 +01:00
Heinrich Schuchardt
268ec6e00e efi_loader: fix building crt0 on arm
Before the patch an undefined constant EFI_SUBSYSTEM was used in the
crt0 code. The current version of binutils does not swallow the error.

https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=888403

The necessary constant IMAGE_SUBSYSTEM_EFI_APPLICATION is already
defined in pe.h. So let's factor out asm-generic/pe.h for the
image subsystem constants and use it in our assembler code.

IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER does not exist in the specification
let's use IMAGE_SUBSYSTEM_EFI_ROM instead.

The include pe.h is only used in code maintained by Alex so let him be the
maintainer here too.

Reported-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-02-10 00:24:00 +01:00
Maxime Ripard
bf8f4c4400 MAINTAINERS: Update email address for Maxime Ripard
Free Electrons is no more and is now known as Bootlin, change my email
address accordingly.

Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-02-04 19:21:00 -05:00
Heinrich Schuchardt
29a8a2828e efi_loader: add a README.iscsi describing booting via iSCSI
The appended README explains how U-Boot and iPXE can be used
to boot a diskless system from an iSCSI SAN.

The maintainer for README.efi and README.iscsi is set.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
[agraf: s/Adress/Address/]
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-01-28 21:37:13 +01:00
Alexander Graf
6001985f92 bcm2835_pl011_serial: Add BCM2835 specific serial driver
On bcm2835 we need to ensure we only access serial devices that are
muxed to the serial output pins of the pin header. To achieve this
for the pl011 device, add a bcm2835 specific pl011 wrapper device
that does this check but otherwise behaves like a pl011 device.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-01-28 12:27:36 -05:00
Alexander Graf
958d55f26c MAINTAINERS: Take over BCM2835 maintainership
It seems as if I have more interest in BCM2835 support than most others,
so I'll bite the bullet and declare myself maintainer. It'd be a shame
to leave that platform orphaned.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-01-28 12:27:36 -05:00
Alexander Graf
c8a73a26d6 mmc: Add bcm2835 sdhost controller
The BCM2835 family of SoCs has 2 different SD controllers: One based on
the SDHCI spec and a custom, home-grown one.

This patch implements a driver for the latter based on the Linux driver.
This is needed so that we can make use of device trees that assume driver
presence of both SD controllers.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-01-28 12:27:32 -05:00
Alexander Graf
caf2233b28 bcm283x: Add pinctrl driver
The bcm283x family of SoCs have a GPIO controller that also acts as
pinctrl controller.

This patch introduces a new pinctrl driver that can actually properly mux
devices into their device tree defined pin states and is now the primary
owner of the gpio device. The previous GPIO driver gets moved into a
subdevice of the pinctrl driver, bound to the same OF node.

That way whenever a device asks for pinctrl support, it gets it
automatically from the pinctrl driver and GPIO support is still available
in the normal command line phase.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-01-28 12:27:32 -05:00
Heinrich Schuchardt
ac02019616 tools: provide a tool to convert a binary file to an include
For testing EFI disk management we need an in-memory image of
a disk.

The tool file2include converts a file to a C include. The file
is separated into strings of 8 bytes. Only the non-zero strings
are written to the include. The output format has been designed
to maintain readability.

 #define EFI_ST_DISK_IMG { 0x00010000, { \
  {0x000001b8, "\x94\x37\x69\xfc\x00\x00\x00\x00"}, /* .7i..... */ \
  {0x000001c0, "\x02\x00\x83\x02\x02\x00\x01\x00"}, /* ........ */ \
  {0x000001c8, "\x00\x00\x7f\x00\x00\x00\x00\x00"}, /* ........ */ \
  {0x000001f8, "\x00\x00\x00\x00\x00\x00\x55\xaa"}, /* ......U. */ \
 ...
  {0x00006000, "\x48\x65\x6c\x6c\x6f\x20\x77\x6f"}, /* Hello wo */ \
  {0x00006008, "\x72\x6c\x64\x21\x0a\x00\x00\x00"}, /* rld!.... */ \
  {0, NULL} } }

As the disk image needed for testing contains mostly zeroes a high
compression ratio can be attained.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-01-22 23:09:12 +01:00
Heinrich Schuchardt
bc0bd77ed4 MAINTAINERS: correct entry for lib/efi*/
lib/efi* indicates files efi* in directory lib.
lib/efi*/ indicates all files in directories lib/efi*.

Fixes: 623b3a5797 efi_selftest: provide an EFI selftest application
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-01-22 23:09:12 +01:00
Rick Chen
f94c44e51e riscv: Add Kconfig to support RISC-V
Add Kconfig and makefile for RISC-V
Also modify MAINTAINERS for it.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2018-01-12 08:05:12 -05:00
Eddie Cai
1c977772a6 rockchip:usb: add a simple readme for rockusb
add a simple readme to introduce rockusb and tell people how to use it

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-10 11:11:06 +01:00
Eddie Cai
453c95e01a usb: rockchip: add rockusb command
this patch add rockusb command. the usage is
rockusb <USB_controller> <devtype> <dev[:part]>
e.g. rockusb 0 mmc 0

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-10 11:11:06 +01:00
Eddie Cai
bf2b72bef1 usb: rockchip: add the rockusb gadget
this patch implement rockusb protocol on the device side. this is based on
USB download gadget infrastructure. the rockusb function implements the rd,
wl, rid commands. it can work with rkdeveloptool

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-10 11:11:05 +01:00
Eugeniy Paltsev
e80dac0ab8 ARC: clk: introduce HSDK CGU clock driver
Synopsys HSDK clock controller generates and supplies clocks to various
controllers and peripherals within the SoC.

Each clock has assigned identifier and client device tree nodes can use
this identifier to specify the clock which they consume. All available
clocks are defined as preprocessor macros in the
dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device
tree sources.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-12-11 11:36:23 +03:00
Simon Glass
20faa27c2b log: test: Add a pytest for logging
Add a test which tries out various filters and options to make sure that
logging works as expected.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-12-07 15:17:00 -05:00
Simon Glass
ef11ed8239 log: Add a test command
Add a command which exercises the logging system.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-12-07 15:17:00 -05:00
Simon Glass
e9c8d49d54 log: Add an implementation of logging
Add the logging header file and implementation with some configuration
options to control it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-12-07 15:17:00 -05:00
Philipp Tomsich
8b45193a22 MAINTAINERS: update maintained files for Rockchip
With some of the recent cleanups (e.g. moving the DRAM controller
drivers for Rockchip devices to drivers/ram/rockchip), the files
and paths listed in MAINTAINERS no longer covered what really is
looked after as part of the Rockchip port.

This commit updates the files/paths listed in MAINTAINERS for the
Rockchip port.  I am certain, though, that this will have missed some
additional paths that should have been included...

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30 22:55:26 +01:00
Marek Vasut
9db60e257b MAINTAINERS: Add myself as RCar/RMobile comaintainer
To help out with the RCar/RMobile upstreaming, I'm adding myself
as the RCar/RMobile maintainer.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30 02:32:33 +01:00
Bin Meng
c0c5f910ad MAINTAINERS: Update maintainer for USB xHCI
As discussed with Marek, this adds myself as the maintainer to
offload the USB xHCI part.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-26 02:22:36 +01:00
Eugeniy Paltsev
3194c3cddf ARC: HSDK: introduce CREG GPIO driver
The HSDK can manage some pins via CREG registers block.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-11-24 19:37:56 +03:00