Commit graph

50025 commits

Author SHA1 Message Date
York Sun
9cfab06e79 armv8: fsl-layerscape: Fix SECURE_BOOT config
Without a prompt in Kconfig, SECURE_BOOT cannot be selected by
defconfig. The option was dropped unintentionally when defconfig
files were cleaned up. Three targets were impacted
ls1043ardb_SECURE_BOOT, ls2080ardb_SECURE_BOOT,
ls2080aqds_SECURE_BOOT.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 09:28:44 -08:00
Udit Agarwal
9ed44787f6 LS2080A: Add validation of MC & DPC images.
Add secure boot validation of MC, DPC images using
esbc_validate command.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:28:39 -08:00
Udit Agarwal
39199356e9 SECURE_BOOT: Update bootscript and its hdr addresses
Update bootscript and its hdr addresses for Layerscape Chasis 3
based platforms instead of individual SoCs.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:28:34 -08:00
Yangbo Lu
cda000f3c3 configs: ls1012a: enable driver model for eSDHC
Enable driver model for eSDHC on ls1012a rdb and qds boards.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:28:30 -08:00
Yangbo Lu
e1f39751d5 armv8: ls1012a: add eSDHC nodes
This patch is to add eSDHC nodes for ls1012a.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:28:25 -08:00
Yangbo Lu
a6473f8e3f mmc: fsl_esdhc: add 'fsl, esdhc' into of_match table
This patch is to add 'fsl,esdhc' into of_match table to support
driver model for QorIQ eSDHC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:28:20 -08:00
Yangbo Lu
fc8048a88e mmc: fsl_esdhc: make GPIO support optional
There would be compiling error as below when enable driver model for esdhc.
undefined reference to `dm_gpio_get_value'
undefined reference to `gpio_request_by_name_nodev'
This patch is to make GPIO support optional with CONFIG_DM_GPIO. Because
all boards of QorIQ platform don't need it and they just check register for
CD/WP status, only some boards of i.MX platform require this.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:28:14 -08:00
Hou Zhiqiang
3564208e01 armv8/fsl-lsch3: consolidate the clock system initialization
This patch binds the sys_info->freq_systembus to Platform PLL, and
implements the IPs' clock function individually.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:28:09 -08:00
Hou Zhiqiang
904110c7ac armv8/fsl-lsch2: refactor the clock system initialization
Up to now, there are 3 kind of SoCs under Layerscape Chassis 2,
like LS1043A, LS1046A and LS1012A. But the clocks tree has a
lot of differences, for instance, the IP modules have different
dividers to derive its clock from Platform PLL. And the core
cluster PLL and platform PLL maybe have different reference
clocks, such as LS1012A. Another problem is which clock/PLL
should be described by sys_info->freq_systembus, it is confused
in Layerscape Chissis 2.

This patch is to bind the sys_info->freq_systembus to the Platform
PLL, and handle the different divider of IP modules separately
between different SoCs, and separate reference clocks of core
cluster PLL and platform PLL.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:27:59 -08:00
Hou Zhiqiang
ee2a510221 ARMv8/fsl-layerscape: Enable data coherency between cores in cluster
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:27:53 -08:00
Mingkai Hu
3aec452e4d armv8: Enable CPUECTLR.SMPEN for coherency
For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.

For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:27:47 -08:00
Prabhakar Kushwaha
9e0bb4c1d9 arm: layerscape: Enable UUID & GPT partition for NXP's ARM SoC
Enable UUID and GPT partition support for NXP's ARM based SoCs
i.e. LS1012A, LS1021A, LS1043A, LS1046A and LS2080A.

Also enable DOS partition for LS1012AFRDM boards.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:27:43 -08:00
Tang Yuantian
57dfe200a6 armv8: ls1012: Enable CONFIG_DM_USB in defconfigs
Enables driver model flag CONFIG_DM_USB for LS1012A platform
in defconfigs.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:27:38 -08:00
Tang Yuantian
a73058740d armv8: ls1012: added usb nodes in dts
The LS1012A processor has two integrated USB controllers.
One is USB2.0 controller, the other is USB3.0 controller that
allow direct connection to the USB ports with appropriate
protection circuitry and power supplies.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:27:34 -08:00
Hou Zhiqiang
3b6bf8115f armv8/fsl_lsch2: Add the OCRAM initialization
Clear the content to zero and the ECC error bit of OCRAM1/2.

The OCRAM must be initialized to ZERO by the unit of 8-Byte before
accessing it, or else it will generate ECC error. And the IBR has
accessed the OCRAM before this initialization, so the ECC error
status bit should to be cleared.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:27:27 -08:00
Hou Zhiqiang
6930be345a ARMv8/fsl-layerscape: Correct the OCRAM size
The real size of OCRAM is 128KiB, so correct the size of OCRAM.
And OCRAM reserved 2MiB space, then add a new macro to describe
it, which is used for MMU setup.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:27:22 -08:00
Hou Zhiqiang
19538f306b kconfig: move FSL_PCIE_COMPAT to platform Kconfig
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:27:18 -08:00
Minghuan Lian
9fa2a4fc8b pci: layerscape: remove unnecessary legacy code
All Layerscape SoCs have supported new PCIe driver based on DM.
The lagecy PCIe driver code is unused and can be removed.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:27:11 -08:00
Minghuan Lian
2acfda1292 armv8: ls2080a: Enable PCIe in defconfigs
The patch enables PCIe in ls2080a defconfigs and
removes unused PCIe related macro defines.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:27:07 -08:00
Minghuan Lian
831b4e0cb6 armv8: ls1046a: Enable PCIe and E1000 in defconfigs
The patch enables PCIe and E1000 in ls1046a related defconfigs.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:27:03 -08:00
Minghuan Lian
be6430dc7a armv8: ls1043a: Enable PCIe and E1000 in defconfigs
The patch enables PCIe and E1000 in ls1043a defconfigs and
removes unused PCIe related macro defines.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:26:57 -08:00
Minghuan Lian
41873d1571 arm: ls1012a: Enable PCIe and E1000 in defconfigs
The patch enables PCIe and E1000 in ls1012a defconfigs and
removes unused PCIe related macro defines

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:26:53 -08:00
Minghuan Lian
8808aeb7a9 arm: ls1021a: Enable PCIe in defconfigs
The patch enables PCIe in ls1021a defconfigs and
removes unused PCIe related macro defines.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:26:47 -08:00
Minghuan Lian
80afc63fc3 pci: layerscape: add pci driver based on DM
There are more than five kinds of Layerscape SoCs. unfortunately,
PCIe controller of each SoC is a little bit different. In order
to avoid too many macro definitions, the patch addes a new
implementation of PCIe driver based on DM. PCIe dts node is
used to describe the difference.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:26:37 -08:00
Hou Zhiqiang
a7294aba08 pci: layerscape: move kernel DT fixup to a separate file
To make the layerscape pcie driver clear, move the kernel DT fixup
code from pcie_layerscape.c to pcie_layerscape_fixup.c.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:26:24 -08:00
Minghuan Lian
33f61e07b3 armv8: ls2080a: add PCIe dts node
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:25:55 -08:00
Minghuan Lian
b948a16f34 armv8: ls1046a: add PCIe dts node
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:25:47 -08:00
Minghuan Lian
ed9bddefb9 armv8: ls1043a: add PCIe dts node
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:25:43 -08:00
Minghuan Lian
048a045307 arm: ls1012a: add PCIe dts node
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:25:38 -08:00
Minghuan Lian
add73a1dad arm: ls1021a: add PCIe dts node
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:25:33 -08:00
Minghuan Lian
fcf45692b7 dm: pci: remove pci_bus_to_hose(0) calling
There may be multiple PCIe controllers in a SoC.
It is not correct that always calling pci_bus_to_hose(0) to get
the first PCIe controller for the PCIe device connected other
controllers. We just remove this calling because hose always point
the correct PCIe controller.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:25:22 -08:00
Minghuan Lian
d7482ca426 dm: pci: return the real controller in pci_bus_to_hose()
for the legacy PCI driver, the function pci_bus_to_hose() returns
the real PCIe controller. To keep consistency, this function is
changed to return the PCIe controller pointer of the root bus
instead of the current PCIe bus.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:25:14 -08:00
Hou Zhiqiang
1e960e15a5 configs: ls1021a: enable DT and DM support
Enable DT to support Driver Model.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:25:05 -08:00
Minghuan Lian
388f386583 armv8/layerscape: remove unnecessary function declares
For the function alloc_stream_ids() append_mmu_masters() and
fdt_fixup_smmu_pcie() there are no related definitions and they
are never called. So the patch removes the unnecessary declares.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:24:51 -08:00
Priyanka Jain
d037261f7f armv8: fsl-layerscape, ccn504: Set forced-order mode in RNI-6, RNI-20
It is recommended to set forced-order mode in RNI-6,
RNI-20 for performance optimization in LS2088A.

Both LS2080A, LS2088A families has CONFIG_LS2080A define.
As above update is required only for LS2088A, skip this
for LS2080A SoC family.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:23:49 -08:00
jerry.huang@nxp.com
97205eeab4 fsl/usb: enable usb feature for ls1046ardb
Enable usb feature for ls1046ardb

Signed-off-by: Changming Huang <jerry.huang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:23:24 -08:00
Tom Rini
755b06d1c0 Merge branch 'master' of git://git.denx.de/u-boot-i2c 2017-01-18 07:21:33 -05:00
Tom Rini
2c45f8040e Merge git://git.denx.de/u-boot-samsung 2017-01-18 07:21:12 -05:00
Moritz Fischer
19cdd5c5be i2c: i2c-cdns: No need for dedicated probe function
The generic probe code in dm works, so get rid of the leftover cruft.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: u-boot@lists.denx.de
2017-01-18 06:39:01 +01:00
Moritz Fischer
08c11aaefb i2c: i2c-cdns: Implement workaround for hold quirk of the rev 1.0
Revision 1.0 of this IP has a quirk where if during a long read transfer
the transfer_size register will go to 0, the master will send a NACK to
the slave prematurely.
The way to work around this is to reprogram the transfer_size register
mid-transfer when the only the receive fifo is known full, i.e. the I2C
bus is known non-active.
The workaround is based on the implementation in the linux-kernel.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: u-boot@lists.denx.de
2017-01-18 06:38:20 +01:00
Moritz Fischer
0ec0c58643 i2c: i2c-cdns: Reorder timeout loop for interrupt waiting
Reorder the timeout loop such that we first check if the
condition is already true, and then call udelay() so if
the condition is already true, break early.

Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: u-boot@lists.denx.de
2017-01-18 06:38:14 +01:00
Moritz Fischer
5e42985208 i2c: i2c-cdns: Detect unsupported sequences for rev 1.0
Revision 1.0 of this IP has a couple of issues, such as not supporting
repeated start conditions for read transfers.

So scan through the list of i2c messages for these conditions
and report an error if they are attempted.

This has been fixed for revision 1.4 of the IP, so only report the error
when the IP can really not do it.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: u-boot@lists.denx.de
2017-01-18 06:38:06 +01:00
Moritz Fischer
12e8d58415 i2c: mux: Allow muxes to work as children of i2c bus without i2c-parent
For mux check if the parent is already a device of UCLASS_I2C and if yes
just use that. Otherwise see if someone specified an i2c-parent phandle.
This mimics the behavior found in the Kernel, as it removes the
requirement to explicitly specify a i2c-parent phandle.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: u-boot@lists.denx.de
2017-01-18 06:37:57 +01:00
Javier Martinez Canillas
3296eeff8a exynos: video: Enable stdout env var backward compatibility for LCD
Commit bb5930d5c9 ("exynos: video: Convert several boards to driver
model for video") converted the Exynos Chromebooks machines to use DM
for video, but this breaks backward compatibility with the stdout env
var since now stdout is expected to be "vidconsole" instead of "lcd".

This causes display to not work when updating u-boot on these boards
if the old stdout env var is used. Since these are consumer devices,
there's no easy way to have a serial console so users may be confused
thinking that u-boot failed to boot, or in the best case will need to
update the stdout env var blindly to make the display to work again.

There's a CONFIG_VIDCONSOLE_AS_LCD config option to workaround this,
so enable it in the Chromebooks' default configuration files to allow
users to change their stdout env var before the workaround is removed.

Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2017-01-18 14:28:46 +09:00
Sjoerd Simons
d64c31dd93 exynos: Enable XHCI on exynos5250 boards
Once upon a time u-boot didn't support building with two usb host
controller types, these days it does. Enable XHCI in addition to the
existing EHCI support so user can plug usb devices in all available
ports regardless of the controller type.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2017-01-18 14:28:36 +09:00
Sjoerd Simons
701e740f59 exynos5: Don't potentially undervoltage the CPU
For snow when chainloading u-boot the CPU seems to be running at full
speed. The lower CPU voltage seems to be ok for u-boot, but when booting
linux (bringing up all cores) I'm seeing random crashes.

Bump the voltage up to a level that's safe for all cpu frequencies.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2017-01-18 13:29:36 +09:00
Jaehoon Chung
9c796784aa board: samsung: universal_c210: remove the codes relevant to soft_i2c
Removes the codes of soft_i2c.
There is no usasge for universal_c210, also didn't define
CONFIG_SOFT_I2C_GPIO_SCL.
This code seems a dead code.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2017-01-18 13:25:56 +09:00
Jaehoon Chung
1d61ad959e i2c: Kconfig: Add SYS_I2C_S3C24X0 entry
Adding Kconfig for SYS_I2C_S3C24X0.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2017-01-18 13:25:56 +09:00
Jaehoon Chung
a298712e94 i2c: s3c24x0: fix the compiler error for exynos4
If CONFIG_SYS_I2C_S3C24X0_SLAVE isn't defined, then complie error should
be occurred.
This patch is for preventing it.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2017-01-18 13:25:56 +09:00
Jaehoon Chung
816d8b5008 board: samsung: universal_210: use the driver model for max8998
Revmoe the "ifndef CONFIG_DM_I2C".
Intead, use the driver model for max8998.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2017-01-18 13:25:56 +09:00