- 'pciconfighost' is set by default in order to be able to scan bridges
behind the primary host/PCIe
- 'pciscandelay' env variable is recognized to allow for user-controlled
delay before the PCIe bus enumeration; some peripheral devices require a
significant delay before they can be scanned (e.g. LSI8408E); without the
delay they are not detected
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
- correct configuration space mapping
- correct bus numbering
- better access to config space
Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the
first device on the first bus. We now allow to configure up to 16 buses;
also, scanning for devices behind the PCIe-PCIe bridge is supported, so
peripheral devices farther in hierarchy can be identified.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Affects boards: icecube (lite5200), jupiter, motionpro, tqm5200
Tested on: lite5200b
Note: the fixup functions have not been moved to a common place. This
patch is targeted for immediate merging as in solves a build issue, but
the final name/location of the fixups is still subject to debate. I
propose to merge this now, and move the fixups in the next merge window
to be usable by all targets.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
The RTC on the M1575 ULI chipset requires a dummy read before
we are able to talk to the RTC. We accomplish this by adding a
second memory region to the PHB the ULI is on and read from it.
The second region is added to maintain compatiabilty with Linux's
view of the PCI memory map.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is
set to non-zero, because it doesn't support MRM (memory-read-
multiple) correctly. We now added the possibility to configure
this register in the board config file, so that the default value
of 8 can be overridden.
Here the details of this patch:
o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow
board-specific settings. As an example the sequoia board requires 0.
Idea from Stefan Roese <sr@denx.de>.
o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the
PCI IO-space. Obtained from Stefan Roese <sr@denx.de>.
o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set
CFG_PCI_CACHE_LINE_SIZE to 0.
Signed-off-by: Gary Jennejohn <garyj@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Restore CONFIG_EXTRA_ENV_SETTINGS definition which contains the
correct consoledev needed for linux boot.
Standardize on fdt{file,addr} var to hold dtb file name.
Set PCI inbound memory region from CFG_MEMORY_{BUS,PHYS}.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
if a board/$(VENDOR)/common/Makefile exists, build it.
also add the first such case, board/freescale/common/Makefile, to
handle building board-shared EEPROM, PIXIS, and MDS-PIB code, as
dictated by board configuration.
thusly get rid of alternate build dir errors such as:
FATAL: can't create /work/wd/tmp/u-boot-ppc/board/freescale/mpc8360emds/../common/pq-mds-pib.o: No such file or directory
by putting the common/ mkdir command in its proper place (the common
Makefile). Common bits from existing individual board Makefiles have
been removed.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
omap2420h4 switched to cfi, so remove old (already disabled) flash.c
and flash_probe() calls in env_flash.c.
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
define there own I/O functions.
(Needed for the pcs440ep board).
- The default I/O Functions are again 8 Bit accesses.
- Added CONFIG_CMD_IDE for the pcs440ep Board.
Signed-off-by: Heiko Schocher <hs@denx.de>
This patch adds support for the 2nd EEPROM (AT24C128) on the lwmon5
board. Now the "eeprom" command can be used to read/write from/to this
device. Additionally a new command was added "eepromwp" to en-/disable
the write-protect of this 2nd EEPROM.
The 1st EEPROM is not affected by this write-protect command.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds support for the matrix keyboard on the lwmon5 board.
Since the implementation in the dsPCI is kind of compatible with the
"old" lwmon board, most of the code is copied from the lwmon
board directory.
Signed-off-by: Stefan Roese <sr@denx.de>
platforms wishing to display RAM diagnostics in addition to size,
can do so, on one line, in their own board_add_ram_info()
implementation.
this consequently eliminates CONFIG_ADD_RAM_INFO.
Thanks to Stefan for the hint.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
add board_add_ram_info, to make memory diagnostic output more
consistent. u-boot banner output now looks like:
DRAM: 256 MB (DDR1, 64-bit, ECC on)
and for boards with SDRAM on the local bus, a line such as this is
added:
SDRAM: 64 MB (local bus)
also replaced some magic numbers with their equivalent define names.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The patch split the PIB init code from pci.c to a single file board/freescale/common/pq-mds-pib.c
And add Qoc3 ATM card support for MPC8360EMDS and MPC832XEMDS board.
Signed-off-by Tony Li <tony.li@freescale.com>
The PCIe bus that the ULI M1575 is connected to has no possible way of
needing more than the fixed amount of IO & Memory space needed by the ULI.
So make it use far less IO & memory space and have it use the shared LAW. This
free's up a LAW for PCIe1 IO space. Also reduce the amount of IO space needed
by each bus.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
It looks like we had a merge issue that duplicated a bit of code
in ft_board_setup. Also, we need to set CONFIG_HAS_ETH0 to get
the MAC address properly set in the device tree on boot for TSEC1
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Minor cleanups to confirm to the u-boot coding style.
Some german expressions -> english.
HCU5 enforces a unique IP adress for a given slot in the rack.
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
Make ecc initialisation robust, as DDR2-ECC errors may be generated
while zeroing the RAM.
Return 16 bytes (a cacheline) less than the available memory, as the
board and/or PPC440EPx might have problems accessing the last bytes.
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
bzip2 requires a significant chunk of malloc space, and there isn't
enough room on mpc885ads (with only 8MB RAM) for both bzip2's malloc area
and a downloaded image at 0x400000.
Signed-off-by: Scott Wood <scottwood@freescale.com>
This small CPCI750 update extends the board specific command
"show_config" to display the Marvell strapping registers and
extends the PCI IDE controller.
Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
this adds libfdt support code for the freescale
mpc8313erdb, mpc832xemds, mpc8349emds, mpc8349itx,
and gp boards.
Boards remain compatible with OF_FLAT_TREE.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
PCI clocks and QE frequencies weren't being updated, and the core clock
was being updated incorrectly. This patch also adds a /memory node if
it doesn't already exist prior to update.
plus some cosmetic trimming to single line comments.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Merge to two at45.c files into a common file, split to at45.c and spi.c
Fix spelling error in DM9161 PHY Support.
Initialize at91rm9200 board (and set LED).
Add PIO control for at91rm9200dk LEDs and Mux.
Change dataflash partition boundaries to be compatible with Linux 2.6.
Signed-off-by: Peter Pearse <peter.pearse@arm.com>
Signed-off-by: Ulf Samuelsson <ulf@atmel.com>
The PCI ID select values on the Arcadia main board differ depending
on the version of the hardware. The standard configuration supports
Rev 3.1. The legacy target supports Rev 2.x.
Signed-off-by Randy Vinson <rvinson@mvista.com>
Author: Randy Vinson <rvinson@linuxbox.(none)>
Enable the PCI-to-ISA bridge in the VIA Southbridge located on the
Arcadia main board.
Signed-off-by: Randy Vinson <rvinson@mvista.com>
Signed-off-by: York Sun <yorksun@freescale.com>
This patch is against u-boot-mpc85xx.git of www.denx.com
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>
Some patches had inserted warnings into the build:
* mpc8560ads declared data without using it
* cpu_init declared ecm and immap without using it in all CONFIGs
* MPC8548CDS.h had its default filenames changed so that they contained
"\m" in the paths. Made the defaults not Windows-specific (or
anything-specific)
Signed-off-by: Andy Fleming <afleming@freescale.com>
Make the early L1 cache stack region guarded to prevent speculative
fetches outside the locked range.
Use _PHYS defines, not _MEM for cpu-side PCI memory mapped regions.
init.S whitespace cleanup.
Allow TEXT_BASE value to be specified on command line. This allows it
to be set to 0xfffc0000 which cuts the uboot binary in half.
Clear and enable lbc and ecm errors.
Update last_busno in device-tree for pci and pcie.
Remove load of obsolete cpu/mpc85xx/pci.0
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address.
Enable LBC and ECM errors and clear error registers.
Add tftpflash env var to get uboot from tftp server and flash it.
Add pci/pcie convenience env vars to display register space:
"run pcie3regs" to see all pcie3 ccsr registers
"run pcie3cfg" to see all cfg registers
Whitespace cleanup and MPC8544DS.h
Enable CONFIG_INTERRUPTS.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
PCI-Express sockets 1 and 2 verified working with Intel Pro/1000 PT
adapter.
Signed-off-by: Joe Hamman <joe.hamman@embeddedspecialties.com>
Signde-off-by: Jon Loeliger <jdl@freescale.com>
The update procedure was modified to turn off the USB subsystem
before exit for MCC200 and TRAB. This is necessary as otherwise the
USB controller continues to write periodically to system memory!
MCC200-specific notes:
- the patch disables the magic key check for MCC200
- the patch contains the configuration changes made
for the new revision of the board.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Add support for Wind River's SBC8641D reference board.
Signed-off by: Joe Hamman <joe.hamman@embeddedspecialties.com>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Jon Loeliger <jdl@freescale.com>
Add support for the following DaVinci boards:
- DV_EVM
- SCHMOOGIE
- SONATA
Changes:
- Split into separate board directories
- Removed changes to MTD_DEBUG (or whatever it's called)
- New CONFIG_CMD party line followed
- Some cosmetic fixes, cleanup etc.
- Patches against the latest U-Boot tree as of now.
- Fixed CONFIG_CMD_NET in net files.
- Fixed CONFIG_CMD_EEPROM for schmoogie.
- Made sure it compiles and works (forceenv() link problem) on SCHMOOGIE and
DV_EVM. Can't check if it works on SONATA, don't have a board any more,
but it at least compiles.
Here is an excerpt from session log on SCHMOOGIE...
U-Boot 1.2.0-g6c33c785-dirty (Aug 7 2007 - 13:07:17)
DRAM: 128 MB
NAND: 128 MiB
In: serial
Out: serial
Err: serial
ARM Clock : 297MHz
DDR Clock : 162MHz
ETH PHY : DP83848 @ 0x01
U-Boot > iprobe
Valid chip addresses: 1B 38 3A 3D 3F 50 5D 6F
U-Boot > ping 192.168.253.10
host 192.168.253.10 is alive
U-Boot >
Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
Acked-by: Dirk Behme <dirk.behme@gmail.com>
Acked-by: Zach Sadecki <Zach.Sadecki@ripcode.com>
Acked-by: Stefan Roese <sr@denx.de>
When I rebased Ed's patch and cleaned up a few compilation
problems, I apparently rebased my brain on crack first.
Fix that by doing (char *) sized pointer math as needed.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
make: *** No rule to make target `/work/wd/tmp/board/mpc8349itx/u-boot.lds', needed by `/work/wd/tmp/u-boot'. Stop.
Both the ITX and ITX-GP fail when you use "make O=<some dir> ..." or
"BUILD_DIR=<some dir> ./MAKEALL ..."
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Remove the duplicated source code of ecc command on the <board>.c,
for reused, move these code to cpu/mpc83xx directory.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
MPC8323E based board with 64MB fixed SDRAM, 16MB flash,
five 10/100 ethernet ports connected via an ICPlus IP175C
switch, one PCI slot, and serial. Features not supported
in this patch are SD card interface, 2 USB ports, and the
two phone ports.
Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
..and not the global fdt. Rename local fdt vars to blob so as not to
be confused with the global var with the same three-letter name.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The new name matches more closely the kernel's name, which is also
a much better description.
These are the mpc83xx changes made necessary by the function name change.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This change adds 8360 silicon revision 2.1 support to u-boot.
Signed-off-by: Lee Nipper <lee.nipper@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The bios emulator in the MAI board can not pass compile
and have a lot of crap in it. remove it and will have a
clean and small bios emulator in the drivers directory
which can be uesed for every board.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
This patch add definition of the BIOS emulator and the ATI framebuffer
driver for MPC8641HPCN board.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
Additionally export the following fuctions (to make trab_config build again):
- simple_strtol()
- strcmp()
Also bump the ABI version to reflect this change
Signed-off-by: Martin Krause <martin.krause@tqs.de>
All of the PCI/PCI-Express driver and initialization code that
was in the MPC8641HPCN port has now been moved into the common
drivers/fsl_pci_init.c. In a subsequent patch, this will be
utilized by the 85xx ports as well.
Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added.
Also enable the second PCI-Express controller on 8641
by getting its BATS and CFG_ setup right.
Fixed a u16 vendor compiler warning in AHCI driver too.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Add the ability for modules from the Schindler cm5200 family to use a
single U-Boot image:
- rename cm1_qp1 to cm5200
- add run-time module detection
- parametrize SDRAM configuration according to the module we are running on
Few minor, board-specific fixes included in this patch:
- better MAC address handling
- updated default environment ('update' command uses +{filesize} now)
- improved error messages in the auto-update code
- allow booting U-Boot from RAM (CFG_RAMBOOT)
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
Changed storage type of cfg_simulate_spd_eeprom to const
Changed storage type of gpio_tab to stack storage
(Cannot access global data declarations in .bss until afer code relocation)
Improved SDRAM tests to catch problems where data is not uniquely addressable
(e.g. incorrectly programmed SDRAM row or columns)
Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules
Fixed AM29LV320DT (OpCode Flash) sector map
Signed-off-by: Eugene OBrien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>
- Clear ECC status regs after ECC POST test
- Set dcbz for ECC generation with caches enabled as default
- Code cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
Change Lime SDRAM initialization to now support 100MHz and
133MHz (if enabled). Also the framebuffer is initialized to
display a blue rectangle with a white border.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds ECC Post test for the Lwmon5 board based
on PPC440EPx to U-Boot.
Signed-off-by: Pavel Kolesnikov <concord@emcraft.com>
Acked-by: Yuri Tikhonov <yur@emcraft.com>
Acked-by: Stefan Roese <sr@denx.de>
The new boardspecific DDR2 controller configuration is used for the Yucca
board. Now the Yucca board with 440SPe Rev. A chips is also supported.
Signed-off-by: Stefan Roese <sr@denx.de>
The OBJTREE != SRCTREE build scenario was broken.
This fixes it.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Adds code to modify CPM frequencies
* Cleans up the config file to #define TSEC and (for now) #undef FCC
* Adds the MII command for all 8560 ADS configurations
* Updates config file to provide convenience commands for booting
with a device tree
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
- now the Flash ST M29W040B is supported (not tested)
- fix the "led" command
- fix compile error, if BUILD_DIR is used
Signed-off-by: Heiko Schocher <hs@denx.de>
There is a Common Flash Interface Driver existed. To use the CFI driver, define CFG_FLASH_CFI in configuration file.
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Fixed some broken instances of "#ifdef CMD_CFG_IDE" too.
Those always evaluated TRUE, and thus were always compiled
even when IDE really wasn't defined/wanted.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Fixed some broken instances of "#ifdef CMD_CFG_IDE" too.
Those always evaluated TRUE, and thus were always compiled
even when IDE really wasn't defined/wanted.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h
used to be included but CONFIG_BOOTP_MASK was not defined.
Remove lingering references to CFG_CMD_* symbols.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
This patch prepares the migration from the legacy NAND driver
to U-Boot's new NAND subsystem for esd boards.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Since ADS860.h includes "board/fads/fads.h" with ramifications
on the CONFIG_COMMAND treatment, it too has to be adjusted to
exclude already configured commands in this same commit.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
- Add optional ECC generation routine to preserve existing
RAM values. This is needed for the Linux log-buffer support
- Add optional DDR2 setup with CL=4
- GPIO50 not used anymore
- Lime register setup added
Signed-off-by: Stefan Roese <sr@denx.de>
This is a compatibility step that allows both the older form
and the new form to co-exist for a while until the older can
be removed entirely.
All transformations are of the form:
Before:
#if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT)
After:
#if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT)
Signed-off-by: Jon Loeliger <jdl@freescale.com>
This is a compatibility step that allows both the older form
and the new form to co-exist for a while until the older can
be removed entirely.
All transformations are of the form:
Before:
#if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT)
After:
#if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT)
Signed-off-by: Jon Loeliger <jdl@freescale.com>
This patch removes the CFG_PCI_PRE_INIT option completely, since
it's not needed anymore with the patch from Matthias Fuchs with
the "weak" pci_pre_init() implementation.
Signed-off-by: Stefan Roese <sr@denx.de>
- Show on the Status LEDs, some States of the board.
- Get the MAC addresses from the EEProm
- use PREBOOT
- use the CF on the board.
- check the U-Boot image in the Flash with a SHA1
checksum.
- use dynamic TLB entries generation for the SDRAM
Signed-off-by: Heiko Schocher <hs@denx.de>
This patch adds a board command to configure the I2C bootstrap EEPROM
values. Right now 533 and 667MHz are supported for booting either via NOR
or NAND FLASH. Here the usage:
=> bootstrap 533 nor ;to configure the board for 533MHz NOR booting
=> bootstrap 667 nand ;to configure the board for 667MHz NNAND booting
Signed-off-by: Stefan Roese <sr@denx.de>
The latest changes showed a problem with the location of the NAND-SPL
image in the OCM and the init-data area (incl. cache). This patch
fixes this problem.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds NAND booting support for the AMCC Acadia eval board.
Please make sure to configure jumper J7 to position 2-3 when booting
from NOR, and to position 1-2 when booting for NAND.
I also added a board command to configure the I2C bootstrap EEPROM
values. Right now only 267MHz is support for booting either via NOR
or NAND FLASH. Here the usage:
=> bootstrap 267 nor ;to configure the board for 267MHz NOR booting
=> bootstrap 267 nand ;to configure the board for 267MHz NNAND booting
Signed-off-by: Stefan Roese <sr@denx.de>
e600 does not have a bootpg restriction.
Move the version string to beginning of image at fff00000.
Resetvec.S is not needed.
Update flash copy instructions.
Add tftpflash env variable
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
This patch undoes the patch by Jeff Mann with commit-id ada4697d. As
suggested by AMCC it is not recommended to dynamically change the EBC
speed after bootup. So we undo this change to be on the safe side.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch updates the "normal" Bamboo NOR booting port, so
that it is compatible with the coming soon NAND booting
Bamboo port.
It also enables the 2nd NAND flash on the Bamboo.
Signed-off-by: Stefan Roese <sr@denx.de>
After being reset in mpc5xxx_fec_init_phy(), PHY goes into FX mode, in which
networking does not function. This commit switches PHY to TX mode by clearing
the FX_SEL bit of Mode Control Register. It also reverses commit
008861a2f3, i.e., a temporary workaround.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
This patch updates the Acadia (405EZ) support for the new 1.1 board
revision. It also adds support for NAND FLASH via the 4xx NDFC.
Please note that the jumper J7 must be in position 2-3 for this
NAND support. Position 1-2 is for NAND booting only. NAND booting
support will follow later.
Signed-off-by: Stefan Roese <sr@denx.de>
For all practical u-boot purposes, TSECs don't differ throughout the
mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Because the Sequoia board does not boot with an EBC faster than 66MHz,
the clock divider are changed after the initial boot process.
This allows for maximum clocking speeds to be achieved on newer boards.
Sequoia boards with 666.66 MHz processors require that the EBC divider
be set to 3 in order to start the initial boot process at a slower EBC
speed. After the initial boot process, the divider can be set back to 2,
which will cause the boards to run at 83.333MHz. This is backward
compatible with boards with 533.33 MHz processors, as these boards will
already be set with an EBC divider of 2.
Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
