Commit graph

7694 commits

Author SHA1 Message Date
Stefan Roese
ef5cd33064 dm: core: Enable optional use of fdt_translate_address()
The current "simple" address translation simple_bus_translate() is not
working on some platforms (e.g. MVEBU). As here more complex "ranges"
properties are used in many nodes (multiple tuples etc). This patch
enables the optional use of the common fdt_translate_address() function
which handles this translation correctly.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-10-21 02:25:01 +02:00
Fabio Estevam
2727f3bfba dfu: dfu_sf: Take the start address into account
The dfu_alt_info_spl variable allows passing a starting point
for the binary to be flashed in the SPI NOR.

For example, if we have 'dfu_alt_info_spl=spl raw 0x400', this means
that we want to flash the binary starting at address 0x400.

In order to do so we need to erase the entire sector and write to
the the subsequent SPI NOR sectors taking such start address
into account for the address calculations.

Tested by succesfully writing SPL binary into 0x400 offset and
the u-boot.img at offset 64 kiB of a SPL NOR.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Use lldiv for the math]
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-10-19 17:05:13 -04:00
Fabio Estevam
f4c9258213 dfu: dfu_sf: Use the erase sector size for erase operations
SPI NOR flashes need to erase the entire sector size and we cannot pass
any arbitrary length for the erase operation.

To illustrate the problem:

Copying data from PC to DFU device
Download    [=========================] 100%       478208 bytes
Download done.
state(7) = dfuMANIFEST, status(0) = No error condition is present
state(10) = dfuERROR, status(14) = Something went wrong, but the
device does not know what it was
Done!

In this case, the binary has 478208 bytes and the M25P32 SPI NOR
has an erase sector of 64kB.

478208  = 7 entire sectors of 64kiB + 19456 bytes.

Erasing the first seven 64 kB sectors works fine, but when trying
to erase the remainding 19456 causes problem and the board hangs.

Fix the issue by always erasing with the erase sector size.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
2015-10-19 13:47:06 -04:00
Tom Rini
a7e2c6f6bb Merge branch 'master' of git://git.denx.de/u-boot-samsung 2015-10-16 07:19:47 -04:00
Fabio Estevam
aaf87f03ad pci: pcie_imx: Fix hang on mx6qp
PCI driver currently hangs on mx6qp.

Toggle the reset bit with the appropriate timings to fix the issue.

Based on the FSL kernel driver implementation.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-10-15 09:05:13 -04:00
Tom Rini
cb4c833b74 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-10-15 08:43:38 -04:00
Stefan Agner
e24bb2b732 mtd: nand: vf610_nfc: resync with upstream Linux version
This resyncs the driver changes with the Linux version of the
driver. The driver received some feedback in the LKML and got
recently acceppted, the latest version can be found here:
https://lkml.org/lkml/2015/9/2/678

Notable changes are:
- On ECC error, reread OOB and count bit flips in OOB too.
  If flipped bits are below threshold, also return an empty
  OOB buffer.
- Return the amount of bit flips in vf610_nfc_read_page.
- Use endianness aware vf610_nfc_read to read ECC status.
- Do not enable IDLE IRQ (since we do not operate with an
  interrupt service routine).
- Use type safe struct for buffer variants (vf610_nfc_alt_buf).
- Renamed variables in struct vf610_nfc (column and page_sz)
  to reflect better what they really representing.

The U-Boot version currently does not support RAW NAND write
when using the HW ECC engine.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Tested-by: Stefan Agner <stefan@agner.ch>
Acked-by: Scott Wood <scottwood@freescale.com>
2015-10-15 11:10:44 +02:00
Tobias Jakobi
2308ea7c6f exynos: more debug and cleanup in do_sdhci_init()
Add more debug printfs in do_sdhci_init() for calls
that can potentially fail.

Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-10-13 20:22:28 +09:00
Tobias Jakobi
995a54cc12 exynos: be more verbose in process_nodes()
In case sdhci_get_config() or do_sdhci_init() fail, show
the error code that was returned.

Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-10-13 20:22:28 +09:00
Tobias Jakobi
6a9fbb6e20 exynos: Fix passing of errors in exynos_mmc_init()
exynos_mmc_init() always returns zero, so for the caller
it looks like it never fails.

Correct this by returning the error code of process_nodes().
For process_nodes() do something similar and return early
when do_sdhci_init() fails.

v2: Only fail in process_nodes() if we fail on all
    available nodes.

Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-10-13 20:22:28 +09:00
Tobias Jakobi
1a9d1731f9 exynos: Properly zero initialize host in s5p_sdhci_init()
This makes sure that setting the host_caps in s5p_sdhci_core_init()
doesn't operate on potentially uninitialized memory.

Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-10-13 20:22:28 +09:00
Fabio Estevam
f861f51c46 ls102xa: Fix reset hang
Since commit 623d96e89aca6("imx: wdog: correct wcr register settings")
issuing a 'reset' command causes the system to hang.

Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian.

This means that the watchdog on LS1021 has been working by accident as
it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c.
Commit 623d96e89aca6("imx: wdog: correct wcr register settings") only
revelead the endianness problem on LS102x.

In order to fix the reset hang, introduce a reset_cpu() implementation that
is specific for ls102x, which accesses the watchdog WCR register in big-endian
format. All that is required to reset LS102x is to clear the SRS bit.

This approach is a temporary workaround to avoid a regression for LS102x
in the 2015.10 release. The proper fix is to make the watchdog driver
endian-aware, so that it can work for i.MX, Vybrid and LS102x.

Reported-by: Sinan Akman <sinan@writeme.com>
Tested-by: Sinan Akman <sinan@writeme.com>
Reviewed-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-10-12 12:56:32 -04:00
Fabio Estevam
f532727d16 imx_watchdog: Add a header file for watchdog registers
Create fsl_wdog.h to store the watchdog registers and bit fields.

This can be useful when accesses to the watchdog block are made from other
parts, such as arch/arm/ cpu code.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-10-12 12:56:26 -04:00
Ezequiel García
d1d0167663 nand: omap_gpmc: Change correctable bit-flips messages to debug()
Messages on corrected bit-flips are not really useful,
as bit-flips are perfectly normal. Let's avoid cluttering
the console and make them debug.

Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
2015-10-11 17:12:13 -04:00
Stefan Roese
04386f656b Revert "powerpc: ppc4xx: remove lwmon5 support"
This reverts commit 8fe11b8901.

I'll add support to lwmon5 in the next patch and will remove
support for the broken lcd4_lwmon5 as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-10-11 17:12:09 -04:00
Yao Yuan
f2b76c6037 mtd: sf: Add support AT26DF081A chip
AT26DF081A is the spi flash type of TWR-MEM(SCH-26248) card.
We can access the flash through DSPI2 on LS1021ATWR board.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-10-11 16:43:06 +05:30
Mirza Krak
5cb1b7b395 spi: tegra20: Add support for mode selection
Respect the mode passed in set_mode ops.

Signed-off-by: Mirza Krak <mirza.krak@hostmobility.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-10-11 16:43:06 +05:30
Jagan Teki
a22bba81e4 spi: zynq_spi: Fix to configure CPOL, CPHA mask
priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.

This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-11 16:43:06 +05:30
Jagan Teki
d5f60737db spi: xilinx_spi: Fix to configure CPOL, CPHA mask
priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.

This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-11 16:43:06 +05:30
Tom Rini
38ab75a2aa Merge git://git.denx.de/u-boot-x86 2015-10-09 09:55:33 -04:00
Bin Meng
7445435fb3 pci: Fix expansion ROM programming for multi-function devices
PCI_HEADER_TYPE register (offset 0x0e) bit 7 is an indicator
for multi-function devices. We should mask it off before using
it as the header type.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-08 20:09:09 +02:00
Tom Rini
739c5e0833 Merge git://git.denx.de/u-boot-dm 2015-10-08 03:03:41 -04:00
Simon Glass
7bb91dd109 sandbox: Correct operaion of 'reset' command
Currently 'reset' only works with the test device tree. When run without a
device tree, or with the normal device tree, the following error is
displayed:

   Reset not supported on this platform

Fix the driver and the standard device tree to avoid this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
2015-10-05 15:47:49 +01:00
Simon Glass
84d26e296a dm: core: Don't use pinctrl for the root device
Currently when driver model starts up it finds the root uclass and the
pinctrl uclass. This is because even the root node handles pinctrl
processing.

But this is not useful. The root node is not a real hardware device so
cannot require any particular pinmux settings. Also it means that the
memory leak tests fails, since they end up freeing more memory than
they allocate: the marker it set after the root device and pinctrl
uclass are allocated, and later once the pinctrl uclass is freed the memory
used by driver model is less than when the marker was set.

If a platform needs 'core' pin mulitplex settings it can do this with
a driver that is probed on start-up. It would be an abuse of the root node
to use this for pinctrl.

To avoid this problem, only process pinctrl settings for non-root nodes.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-10-05 15:47:49 +01:00
Masahiro Yamada
d18f37c72b serial: rockchip: make ROCKCHIP_SERIAL depend on ARCH_ROCKCHIP
It looks like this line was copy-pasted, but not modified.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-03 10:24:33 -06:00
Przemyslaw Marczak
6f183e869e gpio: s5p: call: dev_get_addr() instead of fdtdec_get_addr()
After rework in lib/fdtdec.c, the function fdtdec_get_addr()
doesn't work for nodes with #size-cells property set to 0.

To get GPIO's 'reg' property, the code should use one of:
fdtdec_get_addr_size_auto_no/parent() function.

Fortunately dm core provides a function to get the property.

This commit reworks function gpio_exynos_bind(), to properly
use dev_get_addr() for GPIO device.

This prevents setting a wrong base register for Exynos GPIOs.

Tested on: Odroid U3/X2, Trats, Trats2, Odroid XU3, Snow (by Simon).

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-10-03 14:39:19 +01:00
Tom Rini
fbb0c7bd92 Merge branch 'master' of git://git.denx.de/u-boot-tegra 2015-10-02 20:35:49 -04:00
Stephen Warren
fe82857c4b gpio: tegra: use named constants
In order to make it clear what the parameters to set_config() and
set_direction() mean, and similarly for the return values from the
respective get_*(), define named constants for these values.

Disassembly shows no diff in the generated code, except that the
order of the code in the branches of tegra_gpio_get_function() gets
modified without affecting behaviour.

Suggested-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-10-02 11:05:56 -07:00
Stephen Warren
9f75a222c7 gpio: tegra: remove unused type
These enum values aren't used anywhere. Remove them.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-10-02 11:05:44 -07:00
Stephen Warren
0c35e3a8b4 ARM: tegra: don't enable GPIOs until direction is set
Tegra's GPIO driver currently enables pins as GPIO as soon as they're
requested. This is not safe, since the desired direction and output value
are not yet known. This could cause a glitch on the output pins between
gpio_request() and gpio_direction_*(), depending on what values happen to
be in the GPIO controller's in/out and out-value registers vs. the final
desired configuration.

To solve this, defer enabling pins as GPIOs until some gpio_direction_*()
is invoked, and the desired configuration is explicitly programmed.

In theory this change could cause regressions, if code exists that claims
a GPIO, never explicitly sets a direction, and then gets/sets the GPIO
value based on that assumption. However, I've read through all the Tegra-
related board files and device drivers that touch GPIOs and I do not see
such buggy code anywhere.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-10-02 11:05:01 -07:00
Stephen Warren
f9d3cab091 ARM: tegra: fix GPIO init table programming
Tegra's gpio_config_table() currently uses common GPIO APIs. These used
to work without requesting the GPIO, but since commit 2fccd2d96b "tegra:
Convert tegra GPIO driver to use driver model" no longer do so. This
prevents any of the GPIO initialization table from being applied to HW.
Fix gpio_config_table() to directly program the HW to solve this.

Fixes: 2fccd2d96b ("tegra: Convert tegra GPIO driver to use driver model")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-10-02 11:04:34 -07:00
Tom Rini
b8d242121d Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-10-02 09:38:44 -04:00
Albert ARIBAUD \\(3ADEV\\)
03544c6640 I2C: mxc_i2c: make I2C1 and I2C2 optional
The driver assumed that I2C1 and I2C2 were always enabled,
and if they were not, then an asynchronous abort was (silently)
raised, to be caught much later on in the Linux kernel.

Fix this by making I2C1 and I2C2 optional just like I2C3 and I2C4
are.

To make the change binary-invariant, declare I2C1 and I2C2 in
every include/configs/ file which defines CONFIG_SYS_I2C_MXC.

Also, while updating README about CONFIG_SYS_I2C_MXC_I2C1 and
CONFIG_SYS_I2C_MXC_I2C2, add missing descriptions for I2C4 speed
(CONFIG_SYS_MXC_I2C4_SPEED) and slave (CONFIG_SYS_MXC_I2C4_SLAVE)
config options.

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-10-02 10:42:31 +02:00
Tom Rini
02c2c51cf7 Merge branch 'master' of git://git.denx.de/u-boot-net 2015-09-30 18:51:51 -04:00
Bernhard Nortmann
c163e43679 net: fix netconsole when CONFIG_DM_ETH is set
This patch uses the eth_is_active() function to work around
issues that prevented compilation with the newer driver model.

Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-09-29 21:54:45 -05:00
Mugunthan V N
26d3acdab8 net: phy: on phy device create do not initialize link to 1
Currently when phy device is created the link variable is
initialized to 1 which denoted phy link is already up. On a power
reset there is no issue as phy status register link status will
not be set, so phy auto negotiate will be started. But when a cpu
reset is issued (ex: dra72x-evm) phy's link status bit is already
set which leads to assume that link is already setup in
genphy_update_link() initial check which results in ehternet not
working. So do not assume that link is already up and on phy
device create set link to zero. This is verified on dra72x-evm.

Reported-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-09-29 16:01:29 -05:00
Hans de Goede
be90974c43 sunxi: mmc: Fix clk-delay settings
In recent allwinner kernel sources the mmc/sdio clk-delay settings have
been slightly tweaked, and for sun9i they are completely different then
what we are using.

This commit brings us in sync with what allwinner does, fixing problems
accessing sdcards on some A33 devices (and likely others).

For pre sun9i hardware this makes the following changes:
-At 400Khz change the sample delay from 7 to 0 (first introduced in A31 sdk)
-At 50 Mhz change the sample delay from 5 to 4 (first introduced in A23 sdk)
-Above 50 MHz change the out delay from 2 to 1 (first introduced in A20 sdk)

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-09-29 11:50:07 +02:00
Hans de Goede
31c5614af4 sunxi_nand_spl: Be smarter about where to look for backup u-boot.bin
We know when u-boot is written to its own partition, in this case the
layout always is:

eb 0 spl
eb 1 spl-backup
eb 2 u-boot
eb 3 u-boot-backup

eb: erase-block

So if we cannot load u-boot from its primary offset we know exactly where
to look for it.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-09-29 11:50:07 +02:00
Łukasz Majewski
4d58e10e3e mmc: dw_mmc: Increase timeout to 4 minutes (as in Linux kernel)
The commit: d9dbb97be0
"mmc: dw_mmc: Zap endless timeout" removed endless loop waiting for end
of dw mmc transfer.

For some workloads - dfu test @ Odroid XU3 (sending 8MiB file) -
and SD cards (e.g. MicroSD Kingston 4GiB, Adata 4GiB)
the default timeout is to short.

The new value - 4 minutes (240 seconds) - is the same as the one used in
Linux kernel driver. Such fix should be good enough until we come up
with better fix for this issue.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Tom Rini <trini@konsulko.com>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
2015-09-28 11:03:56 -04:00
Tom Rini
1a9c229bf7 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-09-24 12:28:10 -04:00
Tom Rini
7bb839d672 Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2015-09-24 12:28:02 -04:00
Masahiro Yamada
8497ccc4c2 ARM: uniphier: rename CONFIG_MACH_* to CONFIG_ARCH_UNIPHIER_*
I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify
they belong to UniPhier SoC family.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
080b7a5b45 pinctrl: uniphier: add UniPhier PH1-LD6b pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-LD6b SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:47 +09:00
Masahiro Yamada
833de5fafb pinctrl: uniphier: add UniPhier ProXstream2 pinctrl driver
Add pin configuration and pinmux support for UniPhier ProXstream2
SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:26:27 +09:00
Masahiro Yamada
b82ca82ed2 pinctrl: uniphier: add UniPhier PH1-Pro5 pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-Pro5 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:25:29 +09:00
Masahiro Yamada
06b2ae5890 pinctrl: uniphier: add UniPhier PH1-sLD8 pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-sLD8 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:24:30 +09:00
Masahiro Yamada
a343812461 pinctrl: uniphier: add UniPhier PH1-Pro4 pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-Pro4 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:23:15 +09:00
Masahiro Yamada
e4410e8207 pinctrl: uniphier: add UniPhier PH1-LD4 pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-LD4 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:21:13 +09:00
Masahiro Yamada
5dc626f836 pinctrl: uniphier: add UniPhier pinctrl core support
The core support for the pinctrl drivers for all the UniPhier SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-09-23 23:21:32 +09:00
Tom Rini
ce50916ca1 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-09-22 22:09:31 -04:00