Commit graph

5 commits

Author SHA1 Message Date
Eugen Hristev
67fd5d85d1 ARM: dts: sam9x60ek: add i2c0 as flexcom0 subnode and eeprom memory
Add i2c0 bus as subnode to flx0.
Add eeprom memory as slave device to i2c0.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-10-24 13:01:57 +03:00
Eugen Hristev
c69ce8029a ARM: dts: at91: sam9x60ek: add onewire support
Add support for onewire memory.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-10-08 09:16:11 +03:00
Tudor Ambarus
228f9e0244 ARM: dts: at91: sam9x60ek: Enable qspi node
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register
access, the other for the qspi core and phy. Both are mandatory.

Enable the qspi node together with the SST26VF064B qspi nor flash
memory. Booting from the QSPI NOR flash is now possible.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-10-08 09:16:11 +03:00
Nicolas Ferre
885554360d ARM: dts: at91: sam9x60: Add macb0 Ethernet controller
Add Ethernet controller to dtsi file and enable it on sam9x60ek
platform connected with rmii.

Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2019-10-08 09:16:11 +03:00
Sandeep Sheriker Mallikarjun
f99e0ad25a ARM: dts: Add dts files for sam9x60ek
add device tree files for sam9x60ek board with below changes.

- Add initial device nodes (pmc, pinctrl, sdhc, dbgu & pit)
- Add the reg property for the pinctrl node.
- Add the "u-boot,dm-pre-reloc" property to determine which nodes
  are used by the board_init_f stage.

Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
[prasanthi.chellakumar@microchip.com: fix style/whitespace issues]
Signed-off-by: Prasanthi Chellakumar <prasanthi.chellakumar@microchip.com>
[nicolas.ferre@microchip.com:
- fix gclk,
- fix pio/pinctrl controller definition and allow to have more
  than only PIOA for this SoC,
- removing pinctrl address]
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
[claudiu.beznea@microchip.com:
- use SAM9X60's compatible for pinctrl
- add drive strength and slew rate options for SDMMC0 pins.]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
[tudor.ambarus@microchip.com:
- u-boot,dm-pre-reloc property in dedicated file,
- fix pit len, starts from 0xFFFFFE40 and it is of len 0x10]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-10-08 09:16:11 +03:00