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3 commits

Author SHA1 Message Date
Kever Yang
7cf04ad1f6 ram: rockchip: update lpddr4 timing for rk3399 
Update lpddr timing in lpddr4-400 and lpddr4-800 file from rockchip
vendor code;

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-11-17 16:23:56 +08:00
YouMin Chen
a922d0d102 ram: rk3399: migrate to use common code 
For there are some structures and functions are common for all rockchip SoCs,
migrate to use the common code so that we can clean up reduandent codes.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-11-17 16:23:56 +08:00
Jagan Teki
dd2c633b2a ram: rk3399: Add LPPDDR4-800 timings inc 
LPDDR4 initialization start with at board selected frequency
and then it switches into 400MHz and 800MHz simultaneously to
make the proper sequence work on each channel with associated
training.

So, add LPDDR4-800 timings inc file in driver area so-that
these timings will take during LPDDR4 initialization phase.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
 2019-07-21 00:00:30 +08:00