Commit graph

48137 commits

Author SHA1 Message Date
Derald D. Woods
a47ca2cf67 ARM: omap3: evm: Add kernel image loading from UBIFS and EXT4
This commit adds UBIFS_NAND to BOOT_TARGET_DEVICES. This will
allow the kernel zImage to be loaded from '/boot/zImage' in UBIFS
(ubi0:rootfs).

Additionally update the *_MMC devices to also load kernel image from
the MMC 0:2 EXT4 file system.

DISTRO_DEFAULTS Setup

=====================

[primary] Check MMC 0:1 for /extlinux/extlinux.conf and boot
[fallback 1] Check MMC 0:2 /boot/zImage and run mmcbootz
[fallback 2] Check MMC 0:2 /boot/uImage and run mmcboot
[fallback 3] Check NAND UBIFS /boot/zImage and run nandbootubifs
[fallback 4] Check NAND partitions and run nandboot

The following "extlinux.conf" can be used to load images in the
top-level of the MMC 0:1 FAT partition.

[MMC(0:1)/extlinux/extlinux.conf]
---8<-------------------------------------------------------------------
default omap3-evm
label omap3-evm
	kernel /zImage
	fdt /omap3-evm.dtb
	append console=ttyO0,115200n8 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait
---8<-------------------------------------------------------------------

Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
2018-01-19 15:49:30 -05:00
Heinrich Schuchardt
7341714d6e board_r: remove superfluous #ifdef CONFIG_PRAM
initr_mem() is already enclosed by
	#if defined(CONFIG_PRAM)
	#endif

So there is no need to check CONFIG_PRAM again inside the
function.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-19 15:49:29 -05:00
Tom Rini
bb2277b3ee GPIO: tca642x: Rework to not include commands in SPL
The command portion of the GPIO driver can only be used in full SPL so
re-work to guard the command related portions and mark it as static.

Cc: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-01-19 15:49:29 -05:00
Tom Rini
0d097b774d GPIO: pca953x: Rework to not include commands in SPL
The command portion of the GPIO driver can only be used in full SPL so
re-work to guard the command related portions and mark it as static.

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-19 15:49:29 -05:00
Klaus Goger
7e37a88465 cmd: pmic: update help description
Change help description to match the style of the other U-Boot commands
and get rid of the leading whitespace.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2018-01-19 15:49:29 -05:00
Heinrich Schuchardt
d2f7158028 fs/fat: remove distractive message in file_fat_read_at()
The message "reading %s\n" may be interesting when
debugging but otherwise it is superfluous.

Only output the message when debugging.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-19 15:49:28 -05:00
Heinrich Schuchardt
a327bde783 fs: remove distractive message in fs_read()
The message
"** %s shorter than offset + len **\n"
may be interesting when debugging but it does not indicate an
error.

So we should not write it if we are not in debug mode.

Fixes: 7a3e70cfd8 fs/fs.c: read up to EOF when len would read past EOF
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-19 15:49:28 -05:00
Adam Ford
3cf0061ab5 DA850evm: Remove dead code
There is an #ifdef and #endif with nothing in between.  This patch simply
removes this dead/useless code.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-01-19 15:49:28 -05:00
Derald D. Woods
4b37928d35 ARM: dts: omap3-beagle{-xm}: Enable DM and devicetree for BeagleBoard
This commit updates the configuration files needed to support OF_CONTROL
on the OMAP3 BeagleBoard(s).
2018-01-19 15:49:28 -05:00
Derald D. Woods
3ff0d80181 ARM: dts: omap3-beagle{-xm}: Add support for BeagleBoard
This commit adds OMAP3 BeagleBoard devicetree files from
Linux v4.15-rc5. This includes standard OMAP34XX board revisions as
well as the 'xM' which is OMAP36XX.

Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
2018-01-19 15:49:28 -05:00
Lokesh Vutla
3741c044cb env: ti: Select dtb name for dra76x and am574
Select dtb name for am574x-idk and dra76x evm with acd package.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-01-19 15:49:27 -05:00
Lokesh Vutla
b4185e4fef ARM: dts: am574x-idk: Add initial support
Add initial dts support for am574x-idk

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-01-19 15:49:27 -05:00
Lokesh Vutla
1f126897d8 board: ti: am57xx: Enable CMD_DDR3
Enable CMD_DDR3 on all am57xx based platforms.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-01-19 15:49:27 -05:00
Lokesh Vutla
443b0df361 board: ti: am574x-idk: Update pinmux using latest PMT
Update the board pinmux for AM574x-IDK board using latest PMT[1] and the
board files named am574x_idk_v1p3b_sr2p0 that were auto generated on
13th October, 2017 by "Ahmad Rashed <a-rashed@ti.com>".

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-01-19 15:49:27 -05:00
Lokesh Vutla
7b16de8595 board: ti: am574x-idk: Add ddr data support
AM574x-idk has the following DDR parts attached:
EMIF1: MT41K256M16HA (1GB with ECC)
EMIF2: MT41K256M16HA (1GB without ECC)

Enabling 2GB DDR without interleaving between EMIFs. And
enabling ECC on EMIF1.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Krunal Bhargav <k-bhargav@ti.com>
2018-01-19 15:49:27 -05:00
Lokesh Vutla
10f430f3f1 board: ti: am574x-idk: Add hw data support
Update prcm, voltages and pinmux support for am574x-idk.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-01-19 15:49:26 -05:00
Lokesh Vutla
9646b95f64 board: ti: am574x-idk: Add epprom support
am574x-idk is a board based on TI's am574 processor
Add eeprom support.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-01-19 15:49:26 -05:00
Lokesh Vutla
941f2fcc5b arm: dra762: Add support for device package identification
DRA762 comes in two packages:
- ABZ: Pin compatible package with DRA742 with DDR@1333MHz
- ACD: High performance(OPP_PLUS) package with new IPs

Both the above packages uses the same IDCODE hence needs to
differentiate using package information in DIE_ID_2.
Add support for the same. Also update clock, ddr, emif information.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-01-19 15:49:26 -05:00
Lokesh Vutla
8a8af8a2fd cmd: ti: Generalize cmd_ddr3 command
Keystone and DRA7 based TI platforms uses same
EMIF memory controller. cmd_ddr3 command is customized
for keystone platforms, make it generic so that it can
be re used for DRA7  platforms.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-01-19 15:49:26 -05:00
Lokesh Vutla
5cd9661dc6 arm: keystone: Move cmd_ddr3 to a common place
Move cmd_ddr3 to cmd/ti in order to make
it build for non-keystone TI platforms.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Rename to ddr3.c not cmd_ddr3.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-01-19 15:49:26 -05:00
Lokesh Vutla
650fda93c8 arm: emif-common: Add suppport for enabling ECC
For data integrity, the EMIF1 supports ECC on the data
written or read from the SDRAM. Add support for enabling
ECC support in EMIF1.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Krunal Bhargav <k-bhargav@ti.com>
2018-01-19 15:49:25 -05:00
Lokesh Vutla
e18cd3d796 arm: emif-common: Add ecc specific emif registers
This is a slight difference in emif_ddr_phy_status register offsets for
DRA7xx EMIF and older versions. And ecc registers are available only
in DRA7xx EMIC. Add support for this difference and ecc registers.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-01-19 15:49:25 -05:00
Tero Kristo
72b7af5a04 drivers: dma: ti-edma3: add support for memory fill
Add support for simple memory fill operation. With large data sizes
it is much faster to use EDMA for memory fill rather than CPU.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-01-19 15:49:25 -05:00
Felix Brack
445277b9d1 dt-bindings: leds: adopt Linux PCA9532 binding constants
I'm working on a v2 patch to add support for a board named pdu001. Its
Linux DTS file uses the include file added by this patch. To keep Linux
and U-Boot DTS files in sync U-Boot requires a copy of this file,
although there is no driver for NXP's PCA9532 i2c LED driver chip (yet).

Signed-off-by: Felix Brack <fb@ltec.ch>
2018-01-19 15:49:25 -05:00
Lokesh Vutla
f1627bdc19 board: ti: k2g: Make ddr3* declarations as static
All ddr3_emif declarations are not used outside ddr3_k2g.c
file. So make all of them as static.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-19 15:49:25 -05:00
Tomi Valkeinen
8d0dcbf212 board: ti: dra76: mux wakeup2 as gpio1_2
gpio1_2 is used for HPD interrupt with DRA76's DVI add-on board, so mux
the pin as gpio and PIN_INPUT.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2018-01-19 15:49:24 -05:00
Lokesh Vutla
9b88a4bda2 arm: am33xx: Avoid writing into reserved DPLL divider
DPLL DRR doesn't have an M4 divider. But the clock driver is trying
to configure M4 divider as 4(writing into a reserved register).
Fixing it by making M4 divider as -1.

Reported-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-01-19 15:49:24 -05:00
Lokesh Vutla
3a0e70f181 tools: omapimage: Fix mismatch of image size in header
The size field in GP header that is expected by ROM is size of the
image + size of the header. But omapimage tool is updating size
as image size + 2 * header size. Remove this extra header size bytes.

Reported-by: Denys Dmytriyenko <denys@ti.com>
Debugged-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-01-19 15:49:24 -05:00
Rex Chang
4849d95407 board: ti: K2G FC SoC 1GHz and DDR3 1066 MT/s support
Added support for K2G EVM with FlipChip SoC of which
ARM/DDR3 runs at 1GHz/1066 MT/s. The patch is also
backward compatible with old revision EVM and EVM
with WireBond SoC. Their ARM/DDR3 run at 600MHz/800 MT/s.

The new SoC supports 2 different speeds at 1GHz and 600MHz.
Modyfied the CPU Name to show which SoC is used in the EVM.
Modified the DDR3 configuration to reflect New SoC supports
2 different CPU and DDR3 speeds, 1GHz/1066MT and 600MHz/800MT.

Added new inline function board_it_k2g_g1() for the new FlipChip 1GHz,
and set the u-boot env variable board_name accordingly.

Modified findfdt script in u-boot environment variable to include new k2g board type.

Signed-off-by: Rex Chang <rchang@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-01-19 15:49:24 -05:00
Lokesh Vutla
19f3feaed1 configs: k2g_evm: Allocate more space for u-boot
Now that we have multi dtb enabled in u-boot allocate
128K space for u-boot.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-01-19 15:49:24 -05:00
Vignesh R
e36edcec0a board: ti: dra7xx: Select MCAN instead of DCAN on DRA76 EVM
MCAN can be accessed via DCAN1 or DCAN2. Determining which DCAN instance
to use if any at all is done through
CTRL_CORE_CONTROL_SPARE_RW.SEL_ALT_MCAN. Since general pinmuxing is
handled in U-boot. Handle this additional pinmuxing requirement in U-boot
to ensure that MCAN is used by default via the DCAN1 pins.

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
[fcooper@ti.com: Update commit message and use DCAN1 not DCAN2 for MCAN]
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2018-01-19 15:49:23 -05:00
Kishon Vijay Abraham I
29171dcfaa mmc: omap_hsmmc: Fix incorrect bit operations for disabling a bit
omap_hsmmc driver uses "|" in a couple of places for disabling a bit.
While it's okay to use it in "mmc_reg_out" (since mmc_reg_out has a
_mask_ argument to take care of resetting a bit), it's incorrectly used
for resetting flags in "omap_hsmmc_send_cmd".

Fix it here by using "&= ~()" to reset a bit.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-19 15:49:23 -05:00
Kishon Vijay Abraham I
866bb98468 mmc: omap_hsmmc: Enable Auto command (CMD12) enable
Instead of sending STOP TRANSMISSION command from MMC core, enable
the auto command feature so that the Host Controller issues CMD12
automatically when last block transfer is completed.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-19 15:49:23 -05:00
Kishon Vijay Abraham I
f0d53e88a6 mmc: omap_hsmmc: Add support for DMA (ADMA2)
The omap hsmmc host controller can have the ADMA2 feature. It brings better
read and write throughput.
On most SOC, the capability is read from the hl_hwinfo register. On OMAP3,
DMA support is compiled out.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-19 15:49:17 -05:00
Chris Packham
672e559830 ddr: marvell: update ddr controller init and freq
Update the calculation for tWR and tPD. This improves the DDR refresh
interval and brings the initialization into line with the binary blobs
currently being supplied by Marvell.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-19 16:30:29 +01:00
Chris Packham
8bddf678db ddr: marvell: update additional ODT setting
The RD_SAMPLE_DELAY field is 5 bits so it needs to be masked with 0x1f
instead of 0xf. Rather than checking the read sample delay for all DDR
chip selects use the values for the chip selects that are actually
configured. Finally continue searching for the max_phase value even if the
current read_sample is the same as the max_read_sample.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-19 16:30:29 +01:00
Chris Packham
2efd27f76a ddr: marvell: use correct TREFI value
The ternary operation had the HIGH/LOW values the
wrong way round. Update it to use the correct value.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-19 16:30:29 +01:00
Chris Packham
dbaf09590d ddr: marvell: only assert M_ODT[0] on write for a single CS
When using only a single DDR chip select only assert M_ODT[0] on write.
Do not assert it on read and do not assert M_ODT[1] at all. Also set
tODT_OFF_WR to 0x9 which contradicts the recommendation from the
functional spec but is what Marvell's binary training blob does and
seems to give better results when ODT is active during writes.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-19 16:30:29 +01:00
Alexey Brodkin
8f44e1ee79 ARC: devboards: Allow huge uImages (up to 128 MiB)
Even though in production uImage usually is quite small as
it contains just Linux kernel image during development it might
be pretty convenient to have root-FS built into the same image.

That makes uImage much larger but given on our dev platforms we have
quite a lot of DDR (> 512 MiB) we may afford loading huge uImages.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-19 17:59:35 +03:00
Eugeniy Paltsev
c0e6769a82 ARC: Invalidate instruction and data caches early on boot
This is useful to make sure no stale data exists in caches after bootloaders.

The worst thing could be some lines of cache were locked in a bootloader
for example during DDR recalibration and never unlocked. This may lead
to really unpredictable issues later down the line.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-19 17:59:35 +03:00
Eugeniy Paltsev
7897f4e54c ARC: HSDK: DTS: Add cgu-clk node
Add cgu-clk (clock generation unit) node to HSDK device tree.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-19 17:59:35 +03:00
Eugeniy Paltsev
320c8a1a86 ARC: HSDK: CGU: Add 'Hz' when printing clock frequency
Add 'Hz' when printing clock frequency in error messages.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-19 17:59:35 +03:00
Eugeniy Paltsev
f6d7812d8d ARC: HSDK: CGU: Use plat data instead of priv data
Correctly allocate hsdk_cgu_clk private data structure using
priv_auto_alloc_size instead of platdata_auto_alloc_size.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-19 17:59:35 +03:00
Eugeniy Paltsev
075cbae163 ARC: HSDK: CGU: Update AXI, TUN, ARC clock options
Update default AXI, TUN, ARC clock set options:
instead of changing only IDIV divider settings adjust also domain PLL
settings.

Add support of TUN_ROM and TUN_PWM clocks (subclocks of TUNN_PLL)

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-19 17:59:35 +03:00
Eugeniy Paltsev
5aec2569a6 ARC: HSDK: Hang on panic
As HSDK is a development board it is better to hang on panic instead of
reset the board when panic occurs. That way we preserve a state of HW
for possibility to do post-mortem debug via JTAG.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-19 17:59:35 +03:00
Eugeniy Paltsev
19b10a42f6 ARC: Cache: Fix style violations reported by checkpatch
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-19 17:59:35 +03:00
Eugeniy Paltsev
b0146f9e29 ARC: Cache: Disable IOC by default
We'd like to keep IOC HW at the same state as t is right after reset when we
start Linux kernel so there will be no re-configuration of IOC on the go.

The point is U-Boot doesn't benefit a lot from IOC as it doesn't do a
lot of DMA operations especially on multiple cores simultaneously.

At the same time re-configuration of IOC in run-time might become quite
a tricky experience because we need to make sure there're no DMA
trannsactions in flight otherwise unexpected consequencses might affect
us much later and debugging those kinds of issues will be a real
nightmare.

That said let's make our life easier a little bit.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-19 17:59:34 +03:00
Eugeniy Paltsev
41cada4d24 ARC: ARCv2: Cache: Fixed operation without IOC
Previous SLC management implementation is broken. Seems like it was
never sufficiently tested probably because most of the time IOC was used
instead (i.e. no manual cache operations were done).

Now if we disable IOC in U-boot we'll get a lot of errors while using
DMA-enabled peripherals.

This time we fix it by substitution of broken per-line SLC operations
region operations as it is done in the Linux kernel (we took it from
v4.14 which is the latest stable as of today).

Among other things this implementation might be a bit faster because
instead of iteration over each and every cache line we're taking care
about entire region in one go.

Main changes:
 * Replaced __slc_line_op (per line operations) by __slc_rgn_op
   (region operations).

 * Reworked __slc_entire_op to get rid of __after_slc_op and
   __before_slc_op functions.
   Note flush fix (flush only instead of flush-n-inv when OP_FLUSH is
   used, see [1] for more details) is already incorporated here.

 * Added SLC invalidation to invalidate_icache_all().

 * Added (start >= end) check to invalidate_dcache_range() and
   flush_dcache_range() as some buggy drivers pass region start == end.

 * Added read-out of MMU BCR so we may know if PAE40 exists in HW and then
   act on a particular AUX regs accordingly.

[1] http://lists.infradead.org/pipermail/linux-snps-arc/2018-January/003357.html

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-19 17:59:34 +03:00
Jean-Jacques Hiblot
f844d5f4e6 omap: Update the base address of the MMC controllers
Align the base address defined in header files with the base address used
in the DTS. This will facilitate the introduction of the DMA support.

Of all HSMMC users, only omap3 doesn't have the 0x100 reserved region at
the top. This region will be used to determine if the controller supports
DMA transfers

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-18 22:04:21 -05:00
Jean-Jacques Hiblot
741726ae4c Revert "omap_hsmmc: update struct hsmmc to accommodate omap3 from DT"
This reverts commit 46831c1a4c.
This reserved area at the beginning of struct hsmm, will be used later to
support ADMA

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-18 22:04:21 -05:00