Commit graph

6 commits

Author SHA1 Message Date
Cristian Sovaiala
1f06c9af31 powerpc/mpc85xx: Changed LIODN offset values
Extending LIODN offset range from 1-5 to 1-10
While using a qman portal with a higher index the LIODN offset
is incorrectly set, thus extending the range of offsets covers
all 10 qman portals

Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
Acked-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:57:34 -05:00
Timur Tabi
5c5befda58 powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNs
The SET_PCI_LIODN() macro takes a compatible property string as a parameter, so that it knows
which PCI device tree node to look for.  The calls to these macros are using a hard-coded string,
but we already have the CONFIG_SYS_FSL_PCIE_COMPAT macro which contains the same string, so we
should use that.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 18:32:16 -05:00
Kumar Gala
4d28db8a1e powerpc/85xx: Add support for RMan LIODN initialization
This patch is intended to initialize RMan LIODN related registers on
P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to
qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-18 00:36:48 -05:00
Kumar Gala
1a0c64219d powerpc/85xx: Update setting of SRIO LIODNs
Properly set the LIODN values associated with SRIO controller.  On
P4080/P3060 we have an LIODN per port and one for the RMU.  On
P2041/P3041/P5020 we have 2 LIODNs per port.

Update the tables for all of these devices to properly handle both
styles.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-18 00:36:15 -05:00
Haiying Wang
510f28cff9 powerpc/p2041: fixup portal config info
P2041 has 10 qman portals, we need to configure all of them:
* As there are only 4 physical cores sdest can only be 0 to 3
* We assign dqrr & frame data LIODNs for all portals so if they
  are utilized the proper mapping tables can be setup uniquely
  (PAMU stashing)
* We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN
  assignments are tuned around an assumption of at most 5
  partitions.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-13 23:38:10 -05:00
Kumar Gala
88b91f2d3b powerpc/85xx: Rename P2040 id & SERDES to P2041
P2041 is the superset part that covers both P2040 & P2041.  The only
difference between the two devices is that P2041 supports 10g/XAUI and
has an L2 cache.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29 08:53:37 -05:00
Renamed from arch/powerpc/cpu/mpc85xx/p2040_ids.c (Browse further)