Commit graph

1167 commits

Author SHA1 Message Date
Mike Frysinger
bb83875d5d Blackfin: switch to common display_options()
Use common code to output the version string rather than doing it
ourselves.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-12 02:17:46 -04:00
Mike Frysinger
e8e35efc8f Blackfin: serial: move early debug strings into .rodata section
Rewrite the assembly serial_early_puts() helper to place the strings
in the .rodata section rather than embedding them directly in the
.text section.  Using .text is a little simpler, but it doesn't let
people execute out of internal L1 sram (since core reads don't work
on those regions).

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-12 02:17:46 -04:00
Mike Frysinger
bc9c64273d Blackfin: update anomaly lists to latest public info
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-12 02:17:46 -04:00
Mike Frysinger
b1e574d95b Blackfin: serial: convert to bfin_{read,write} helpers
Since the serial struct declares the sizes for us, no need to hardcode
them in the accessor functions.  Let the bfin_{read,write} helpers do
it for us.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-12 02:17:46 -04:00
Mike Frysinger
4150cec335 Blackfin: split out async setup
We really only need to tweak the async banks in the initcode if the
processor is booting out of it, otherwise we can wait until later
on in the CPU booting setup.

This also makes testing in the sim and early bring up over JTAG work
much smoother when the initcode gets bypassed.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-12 02:17:46 -04:00
Mike Frysinger
ed7496349d Blackfin: drop unused dma.h header from start code
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-12 02:17:45 -04:00
Mike Frysinger
f75e8b32ad Blackfin: portmux: allow header to be included in assembly files
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-12 02:17:45 -04:00
Mike Frysinger
7ed998f629 Blackfin: sync MMR read/write helpers with Linux
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-12 02:17:45 -04:00
Mike Frysinger
95b4b9d97a Blackfin: gpio: optimize free path a little
When we aren't doing resource tracking, the gpio_free() function is a
stub that simply returns, so pull this logic up a level and make it an
inline stub in the header.  Now we don't have to waste time at any of
the call sites.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-12 02:17:45 -04:00
Mike Frysinger
272d2fc2f5 Blackfin: post: setup default CONFIG_SYS_POST_WORD_ADDR
Set the default post word location to an L1 data location for all
Blackfin parts so things "just work" for most people.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-12 02:17:45 -04:00
Mike Frysinger
f9aee4b4b6 Blackfin: uart: fix printf warning
The code uses %i to printf a size_t when it should use %zu, otherwise
we get a warning from gcc about it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-12 02:17:45 -04:00
Mike Frysinger
fb5166ce35 Blackfin: add init.elf helper code
This creates a standalone ELF that executes just the Blackfin initcode.
This is useful for people who want to program the low level aspects of
the CPU (memory/clocks/etc...) and can easily be used with JTAG for
quick booting while developing.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-12 02:17:45 -04:00
Mike Frysinger
08a82a447b Blackfin: dont reset SWRST on newer bf526 parts
The bug in the BF526 rom when doing a software reset exists only in older
silicon versions, so don't clear SWRST on newer parts.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-12 02:17:45 -04:00
Mike Frysinger
635f330fc7 Blackfin: uart: add multiple serial support
This brings CONFIG_SERIAL_MULTI support to the Blackfin on-chip UARTs.
Ends up adding only ~512bytes per additional UART.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-12 02:17:45 -04:00
Mike Frysinger
34a6d0b84a Blackfin: uart: move debug buffers into local bss
There's no need for these saved buffers to be global symbols, or in
the data section.  So mark them static to move them into the bss.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-12 02:17:45 -04:00
Timur Tabi
26002826c7 powerpc/85xx: remove SERDES4 soft-reset work-around
Some P4080 rev1 errata work-arounds, notably erratum SERDES4, required a
bank soft-reset after the bank was configured and enabled, even though
enabling a bank causes it to reset.  Because the reset was required for
multiple errata, it was not properly enclosed in an #ifdef, and so was
not removed with all the other rev1 errata work-arounds.

Erratum SERDES-8 says that the clocks for bank 3 needs to be enabled if
bank 2 is enabled, but this was not being done for SERDES protocols 0xF
and 0x10.  The bank reset also happened to enable bank 3 (apparently an
undocumented feature).  Simply removing the reset breaks these two
protocols.

It turns out that every time we call enable_bank(), we do want at least
one lane of the bank enabled, either because the bank is supposed to be
enabled, or because we need the clock from that bank enabled.

For erratum SERDES-A001, we don't want to modify srds_lpd_b[] when we
call enable_bank(), because that array is used elsewhere to determine if
the bank is available.

Note that the side effect of these changes is that the work-arounds for
these two errata are now linked.  Specifically, if SERDES-A001 is
enabled, then we need SERDES-8 enabled as well.

Because this was the only SERDES bank soft-reset, there is no need to
implement a work-around for erratum SERDES-A003.

Also fix an off-by-one error in a printf().

Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Ed Swarthout <swarthou@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:21 -05:00
York Sun
23f9670f1a powerpc/mpc8xxx: Allow override DDR read-to-write turnaround time
Add this option to allow boards to override the default read-to-write
turnaround time for better performance.

Signed-off-by: York Sun <yorksun@freescale.com>
2011-07-11 13:24:20 -05:00
Ramneek Mehresh
72f4980b40 powerpc/8xxx: Update USB mode device tree fixup
Modify support for USB mode fixup:
        - Add common support for USB mode and phy type
          device tree fix-up for all USB controllers
          mentioned in hwconfig string
        - Fetch USB mode and phy type via hwconfig; if not
          defined in hwconfig, then fetch them from env

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:20 -05:00
York Sun
4c99cb9190 powerpc/mpc8xxx: fix DDR data width checking
Checking width before setting DDR controller. SPD for DDR1 and DDR2 has
data width and primary sdram width. The latter one has different meaning
for DDR3.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:20 -05:00
York Sun
f2d264b660 powerpc/mpc8xxx: Adding fallback to raw timing on supported boards
In case of empty SPD or checksum error, fallback to raw timing on
supported boards.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:20 -05:00
York Sun
1b3e3c4f26 powerpc/mpc8xxx: Enable calculation for fixed DDR chips
We used to have fixed parameters for soldered DDR chips. This patch
introduces CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing
data from DDR chip datasheet, implemneted in board-specific files or header
files.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:20 -05:00
Felix Radensky
aeb6716a12 powerpc/85xx: Fix pin muxing for second USB controller
On P1022/P1013 second USB controller is muxed with second
Ethernet controller. The current code to enable second USB
fails to properly clear pinmux bits used by ethernet. As a
result, Linux freezes when this controller is used. This
patch fixes the problem.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:20 -05:00
York Sun
51d498f175 powerpc/mpc8xxx: Add 16-bit support for DDR3
Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit
DDR devices.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:20 -05:00
York Sun
d2246549c7 powerpc/mpc8xxx: check SPD length before using part number
Only use DDR DIMM part number if SPD has valid length, to prevent from
display garbage in case SPD doesn't cover these fields.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:19 -05:00
York Sun
e090aa7cf0 powerpc/mpc8xxx: adjust DDR burst length and chop accroding to sdram width
If the bus width is 32-bit, burst chop should be disabled and burst length
should be 8. Read from SPD or other source to determine the width.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:19 -05:00
Kumar Gala
1f97987a51 powerpc/85xx: Add P2041 processor support
The P2041 is similar to P2040, however has a 10G port and backside L2

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:19 -05:00
Mingkai Hu
526cbff292 powerpc/p2040: Add various p2040 specific information
Add P2040 SoC specific information:
* LIODN setup
* Portal configuration
* etc

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:19 -05:00
Kumar Gala
58b2f96e38 powerpc/85xx: Fix compile errors if CONFIG_SYS_DPAA_QBMAN isn't set
Add ifdef protection for qp_info and liodn associated with Q/BMan.  Also
rearrange setting of _tbl_sz variables to utilize existing ifdef
protection for things like FMAN.

Also add protection around setup_portals() call in corenet_ds board
code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:19 -05:00
Kumar Gala
9829feffec powerpc/85xx: Fix compile errors if CONFIG_SYS_{BR,OR}0_PRELIM aren't set
Add ifdef protection in LBC code to handle the case in which
CONFIG_SYS_BR0_PRELIM and CONFIG_SYS_OR0_PRELIM arent defined for a
build.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:19 -05:00
Bill Cook
810cb19003 MPC83XX: Fix PCI express clock setup
On a 8308 based board it was found that the PEX_GLK_RATIO register
(programmed in arch/powerpc/cpu/mpc83xx/pcie.c) was getting set to 0, This
was tracked to the fact that the pci express clock frequency was not being
assigned to the pciexp1_clk entry in the global data structure in file
arch/powerpc/cpu/mpc83xx/speed.c. Fix this and a similiar issue in
'do_clocks' command.

Signed-off-by: Bill Cook <cook@isgchips.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-07-06 19:09:28 -05:00
Andre Schwarz
03c0a92440 MPC83xx: add config options for memory setup.
CPO value and driver strength settings are board specifc.
Also allow SPD data fetch from any accessible I2C EEPROM.

Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-07-06 19:09:27 -05:00
Andre Schwarz
1bda1624b0 MPC837x: set i2c1_clk
Running on mpc837x without CONFIG_FSL_ESDHC leads to
 i2c1_clk not being set at all. It is bound to clock
 of encryption module. fix this.

Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-07-06 19:09:27 -05:00
Holger Brunck
b31a82e95f arm/kirkwood: if CONFIG_SOFT_I2C is set don't set CONFIG_I2C_MVTWSI
Some boards e.g. keymile arm boards have CONFIG_CMD_I2C switched on
but they use soft i2c on kirkwood. So don't switch CONFIG_I2C_MVTWSI
on in this case.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>
2011-07-04 10:55:28 +02:00
Jens Scharsig
24e50461c0 Fix compiler error for cpu at91sam9, if lowlevel init is enabled
* Fix compiler error for cpu at91sam9, if lowlevel init is enabled
* use correct ATMEL_ name scheme to define ATMEL_BASE_SDRAMC

Signed-off-by: Jens Scharsig
2011-07-04 10:55:28 +02:00
Andreas Bießmann
d703355fd1 arm920t/at91: add at91rm9200_devices.c
This is a copy of arm926ejs/at91 api for perpherial initialisation.
At the moment we just need the usart part of the api.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2011-07-04 10:55:27 +02:00
Andreas Bießmann
6a372e940d arm920t/at91: use new clock.c features
This patch enables the new clock features from arm920t/at91/clock.c. This
is an required step to get at91rm9200_usart replaced by atmel_usart driver.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Jens Scharsig <js_at_ng@scharsoft.de>
Cc: Eric Bénard <eric@eukrea.com>
2011-07-04 10:55:27 +02:00
Andreas Bießmann
c3a383f5bd arm920t/at91: add clock.c
This patch adds an copy of arm926ejs/at91/clock.c to arm920t/at91. The
arm926ejs specialities are removed from arm920t version and vice versa.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2011-07-04 10:55:27 +02:00
Andreas Bießmann
876ef43d2a at91rm9200.h: fix ATMEL_PMX_AA_TXD2
This patch sets the ATMEL_PMX_AA_TXD2 to the correct value.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
CC: Jens Scharsig <js_at_ng@scharsoft.de>
CC: eric@eukrea.com
Acked-by: Eric Bénard <eric@eukrea.com>
2011-07-04 10:55:27 +02:00
Fabio Estevam
a6e961c292 MX5: Introduce a function for setting the chip select size
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-07-04 10:55:26 +02:00
Fabio Estevam
a682b3f76b MX5: Add iomux structure
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-07-04 10:55:26 +02:00
Fabio Estevam
ac4020e3c0 MX5: Make the weim structure complete
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-07-04 10:55:26 +02:00
John Rigby
aadcfc179a OMAP[34]: fix broken timer
As implemented now the timer used to implement __udelay counts
to 0xffffffff and then gets stuck there because the the programmed
reload value is 0xffffffff.  This value is not only wrong but
illegal according to the reference manual.

One can reproduce the bug by leaving a board at the u-boot prompt
for sometime then issuing a sleep command.  The sleep will hang
forever.

The timer is a count up timer that reloads as it rolls over
from 0xffffffff so the correct load value is 0.

Change TIMER_LOAD_VAL from 0xffffffff to 0 and introduce
a new constant called TIMER_OVERFLOW_VAL set to 0xffffffff.

Signed-off-by: John Rigby <john.rigby@linaro.org>
Tested-by: Igor Grinberg <grinberg@compulab.co.il>
2011-07-04 10:55:26 +02:00
Tom Warren
4e5ae09e56 GPIO: Tegra2: add GPIO driver for Tegra2
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-07-04 10:55:26 +02:00
Aneesh V
137db2d7f5 armv7: adapt s5pc1xx to the new cache maintenance framework
adapt s5pc1xx to the new layered cache maintenance framework

Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04 10:55:25 +02:00
Aneesh V
45bf05854b armv7: adapt omap3 to the new cache maintenance framework
adapt omap3 to the new layered cache maintenance framework

Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04 10:55:25 +02:00
Aneesh V
8b457fa828 armv7: adapt omap4 to the new cache maintenance framework
adapt omap4 to the new layered cache maintenance framework

Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04 10:55:25 +02:00
Aneesh V
93bc21930a armv7: add PL310 support to u-boot
PL310 is the L2$ controller from ARM used in many SoCs
including the Cortex-A9 based OMAP4430

Add support for some of the key PL310 operations
	- Invalidate all
	- Invalidate range
	- Flush(clean & invalidate) all
	- Flush range

Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04 10:55:25 +02:00
Aneesh V
e05f00792b arm: minor fixes for cache and mmu handling
1. make sure that page table setup is not done multiple times
2. flush_dcache_all() is more appropriate while disabling cache
   than a range flush on the entire memory(flush_cache())

   Provide a default implementation for flush_dcache_all()
   for backward compatibility and to avoid build issues.

Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04 10:55:25 +02:00
Aneesh V
c2dd0d4554 armv7: integrate cache maintenance support
- Enable I-cache on bootup
- Enable MMU and D-cache immediately after relocation
	- Do necessary initialization before enabling d-cache and MMU
- Changes to cleanup_before_linux()
	- Make changes according to the new framework

Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04 10:55:25 +02:00
Aneesh V
e47f2db537 armv7: rename cache related CONFIG flags
Replace the cache related CONFIG flags with more meaningful
names. Following are the changes:

CONFIG_L2_OFF	     -> CONFIG_SYS_L2CACHE_OFF
CONFIG_SYS_NO_ICACHE -> CONFIG_SYS_ICACHE_OFF
CONFIG_SYS_NO_DCACHE -> CONFIG_SYS_DCACHE_OFF

Signed-off-by: Aneesh V <aneesh@ti.com>
V2:
 * Changed CONFIG_L2_OFF -> CONFIG_SYS_NO_L2CACHE
V4:
 * Changed all three flags to the final names suggested as above
   and accordingly changed the commit message
2011-07-04 10:55:25 +02:00
Aneesh V
2c451f7831 armv7: cache maintenance operations for armv7
- Add a framework for layered cache maintenance
	- separate out SOC specific outer cache maintenance from
	  maintenance of caches known to CPU

- Add generic ARMv7 cache maintenance operations that affect all
  caches known to ARMv7 CPUs. For instance in Cortex-A8 these
  opertions will affect both L1 and L2 caches. In Cortex-A9
  these will affect only L1 cache

- D-cache operations supported:
	- Invalidate entire D-cache
	- Invalidate D-cache range
	- Flush(clean & invalidate) entire D-cache
	- Flush D-cache range
- I-cache operations supported:
	- Invalidate entire I-cache

- Add maintenance functions for TLB, branch predictor array etc.

- Enable -march=armv7-a so that armv7 assembly instructions can be
  used

Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04 10:55:25 +02:00
Aneesh V
4c93da7c39 arm: make default implementation of cache_flush() weakly linked
make default implementation of cache_flush() weakly linked so that
sub-architectures can override it

Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04 10:55:25 +02:00
Wolfgang Denk
177f38609b Minor coding style fixes.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-06-27 22:22:16 +02:00
Wolfgang Denk
9623c158f6 Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
  run arm_pci_init after relocation
  IXP42x PCI rewrite
  update/fix PDNB3 board
  update/fix IXDP425 / IXDPG425 boards
  add dvlhost (dLAN 200 AV Wireless G) board
  IXP NPE: add support for fixed-speed MII ports
  update/fix AcTux4 board
  update/fix AcTux3 board
  update/fix AcTux2 board
  update/fix AcTux1 board
  use -ffunction-sections / --gc-sections on IXP42x
  support CONFIG_SYS_LDSCRIPT on ARM
  fix "depend" target in npe directory
  Fix IXP code to work after relocation was added
  trigger hardware watchdog in IXP42x serial driver
  add support for IXP42x Rev. B1 and newer
  add XScale sub architecture (IXP/PXA) to maintainer list

Conflicts:
	arch/arm/lib/board.c

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-06-23 15:37:33 +02:00
Michael Schwingen
1ed63c5498 run arm_pci_init after relocation
Signed-off-by: Michael Schwingen <michael@schwingen.org>
2011-06-23 08:25:19 +02:00
Michael Schwingen
29161f47d0 IXP42x PCI rewrite
clean up IXP PCI handling: get rid of IXP-private bus scan, BAR assign etc.
code and use u-boot's PCI infrastructure instead.  Move board-specific PCI
setup code (clock/reset) to board directory.

Signed-off-by: Michael Schwingen <michael@schwingen.org>
2011-06-23 08:25:18 +02:00
Michael Schwingen
d697d79f8d IXP NPE: add support for fixed-speed MII ports
Signed-off-by: Michael Schwingen <michael@schwingen.org>
2011-06-23 08:25:18 +02:00
Michael Schwingen
66463e60df use -ffunction-sections / --gc-sections on IXP42x
Signed-off-by: Michael Schwingen <michael@schwingen.org>
2011-06-23 08:24:55 +02:00
Michael Schwingen
363613a08d support CONFIG_SYS_LDSCRIPT on ARM
Signed-off-by: Michael Schwingen <michael@schwingen.org>
2011-06-23 08:24:55 +02:00
Michael Schwingen
3053fa0bfb fix "depend" target in npe directory
Signed-off-by: Michael Schwingen <michael@schwingen.org>
2011-06-23 08:24:55 +02:00
Michael Schwingen
ce04bb41a6 Fix IXP code to work after relocation was added
- jump to real flash location after reset before turning off flash mirror
 - fix timer system to use HZ == 1000, remove broken interrupt-based code

Signed-off-by: Michael Schwingen <michael@schwingen.org>
2011-06-23 08:24:55 +02:00
Michael Schwingen
20f172815d add support for IXP42x Rev. B1 and newer
Signed-off-by: Michael Schwingen <michael@schwingen.org>
2011-06-23 08:24:55 +02:00
Wolfgang Denk
566e5cf451 ARM: drop unsupported 'trab' board
The 'trab' board configuration is broken, and there is nobody who is
interested and willing to fix it.  Drop it.

This includes support for VFD displays which have always been used by
this board only.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-06-22 20:00:51 +02:00
Eric Benard
fd2f565809 include/asm/arch-at91: update several .h files to ATMEL_xxx name scheme
Signed-off-by: Eric Bénard <eric@eukrea.com>
2011-06-21 22:26:22 +02:00
Eric Benard
96fd99067f arm926ejs/at91/lowlevel_init.S: fix defines
atmel rework changed define names which broke this file

Signed-off-by: Eric Bénard <eric@eukrea.com>
2011-06-21 22:26:22 +02:00
Jens Scharsig
8073399444 update arm/at91rm9200 work with rework rework110202
* convert at91rm9200ek and eb_cpux9k2 board to ATMEL_xxx name scheme
 * Fix: timer.c compile error io.h not found with arm/at91rm9200
 * update arm920t/at91 to ATMEL_xxx name scheme
 * update arm920t/at91 soc lib
 * update at91_emac driver

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
Tested-by: Andreas Bießmann <andreas.devel@gmail.com>
2011-06-21 22:26:21 +02:00
Mike Frysinger
9aeab10bd4 Blackfin: use on-chip reset func with newer parts
Turns out the documentation is wrong and doing "RAISE 1" does not result
in a software reset, only a core reset.  So when the on-chip rom has a
functioning reset helper, use it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-03 13:26:45 -04:00
Mike Frysinger
867f54cc35 Blackfin: use common LDSCRIPT logic
Now that common code is a bit smarter when it comes to default LDSCRIPT
values, rename the default Blackfin file and drop the Blackfin-specific
config.mk logic.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-03 13:26:45 -04:00
Wolfgang Denk
4c9640865b Minor coding style cleanup
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-06-02 23:18:32 +02:00
Wolfgang Denk
033cd2c42b Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
  SMDKV310: Fix incorrect conditional compilation for MIU linear mapping
  SMDKV310: CPU fequency and mmc_pre_ratio modified
  armv7: Add support for ST-Ericsson U8500 href platform
  I2C: Add driver for ST-Ericsson U8500 i2c
  armv7: Add ST-Ericsson u8500 arch
  Kirkwood: boards cleanup for deprecated CONFIG_CMD_AUTOSCRIPT
  ARMV7: Vexpress: Add missing MMC header
  arm/km: update mgcoge3un board support
  mvgbe: enable configurability of PORT_SERIAL_CONTROL_VALUE
  arm/km: rename mgcoge2un to mgcoge3un
  arm/km: add second serial interface for kirkwood
  arm/km: disable ls (through jffs2 support)
  arm/km: introduce bootcount env variable and clean km_arm
  arm/km: move CONFIG_EXTRA_ENV_SETTINGS from board to km_arm file
  arm/km: remove CONFIG_SYS_KWD_CONFIG from keymile-common.h
  ARMV7: MMC SPL Boot support for SMDKV310 board
  ARMV7: Add support for Samsung SMDKV310 Board
  S5PC2XX: clock: support pwm clock for evt1 (cpu revision 1)
  S5P: add set_mmc_clk for external clock control
  S5PC2XX: Support the cpu revision
  S5P:SROM config code moved to s5p-common directory
  Add _end for the end of u-boot image for SMDK6400
  MMC S5P: Fix typo
  S5P: GPIO Macro Values Corrected.
  SMDK2410: various cleanup/code style fixes
  SMDK2410: use the CFI driver (and remove the old one)
  SMDK2410: remove unneeded config.mk
  SMDK2410: activate ARM relocation feature
  BeagleBoard: fixed typo in typecast
  mvsata: issue hard reset on initialization
  VCMA9: use ARM relocation feature to fix build error
  MX31: drop warnings due to missing prototype for mxc_watchdog_reset()
  MX5: drop config.mk from efikamx board
  MX31: Make get_reset_cause() static and drop unreachable code
  MX53: Remove CONFIG_SYS_BOOTMAPSZ from mx53 config files.
  MX53: Handle silicon revision 2.1 case
  mx5: board: code clean up for checkboard code
  MX51: vision2: Fix build for vision2 board.
  MX51: vision: Let video mode struct be independant of watchdog.
  MX53: Add initial support for MX53SMD board.
  MX53: support for freescale MX53LOCO board
  mx5: Fix CONFIG_OF_LIBFDT redefined warning
  mx5: Remove unnecessary CONFIG_SYS_BOOTMAPSZ definition
  mx31pdk: Clean up mx31pdk.h file
2011-06-01 22:04:12 +02:00
John Rigby
be72e0c8c5 armv7: Add ST-Ericsson u8500 arch
Based on ST-Ericsson internal git repo.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
CC: Albert Aribaud <albert.aribaud@free.fr>
2011-06-01 19:22:41 +02:00
Minkyu Kang
b4f73910d9 S5PC2XX: clock: support pwm clock for evt1 (cpu revision 1)
The source of pwm clock is fixed at evt1.
And some registers for pwm clock are removed.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2011-05-26 19:33:25 +09:00
Jaehoon Chung
68a8cbfad9 S5P: add set_mmc_clk for external clock control
This patch added set_mmc_clk for external clock control.

c210 didn't support host clock control.
So We need external_clock_control function for c210.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2011-05-26 19:33:09 +09:00
Minkyu Kang
5d845f2758 S5PC2XX: Support the cpu revision
S5PC210 SoC have two cpu revisions, and have some difference.
So, support the cpu revision for each revision.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2011-05-26 19:31:11 +09:00
Chander Kashyap
b0ad862177 S5P:SROM config code moved to s5p-common directory
SROM config code is made common for S5P series of boards.
smdkc100.c now refers to s5p-common/sromc.c for SROM related
subroutines.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2011-05-26 19:30:46 +09:00
Chander Kashyap
898ddf0a36 S5P: GPIO Macro Values Corrected.
S5PC2XX: Macro values for Pull Up and Driver Strength were wrong.
S5PC1XX: Macro values for Driver Strength were wrong.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2011-05-26 19:30:06 +09:00
Stefano Babic
bdb3c20386 MX31: drop warnings due to missing prototype for mxc_watchdog_reset()
Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-05-23 08:36:46 +02:00
Stefano Babic
d43458d237 MX31: Make get_reset_cause() static and drop unreachable code
get_reset_cause() should not be exported. Drop code in the function
after return statement that can generate warnings due to unreachable code.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-05-23 08:36:46 +02:00
Fabio Estevam
aa1cb689d5 MX53: Handle silicon revision 2.1 case
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-05-23 08:36:46 +02:00
Kumar Gala
8f29084a4f powerpc/fsl_pci: Fix device tree fixups for newer platforms
We assumed that only a small set of compatiable strings would be needed
to find the PCIe device tree nodes to be fixed up.  However on newer
platforms the simple rules no longer work.  We need to allow specifying
the PCIe compatiable string for each individual SoC.

We introduce CONFIG_SYS_FSL_PCIE_COMPAT for this purpose and set it if
the default isn't sufficient.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-05-20 00:48:41 -05:00
Wolfgang Denk
cd6881b519 Minor coding style cleanup.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-05-19 22:22:44 +02:00
Wolfgang Denk
0ea91423f4 Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: (40 commits)
  avr32: add ATAG_BOARDINFO
  at91: reworked support for otc570 board
  at91: reworked support for meesc board
  hammerhead: move CONFIG_SYS_TEXT_BASE to header
  mimc200: move CONFIG_SYS_TEXT_BASE to header
  favr-32-ezkit: move CONFIG_SYS_TEXT_BASE to header
  atstk100x: move CONFIG_SYS_TEXT_BASE to header
  atngw100: move CONFIG_SYS_TEXT_BASE to header
  mimc200: fix "#define XXXX 1"
  hammerhead: fix "#define XXXX 1"
  favr-32-ezkit: fix "#define XXXX 1"
  atstk1006: fix "#define XXXX 1"
  atstk1004: fix "#define XXXX 1"
  atstk1003: fix "#define XXXX 1"
  atstk1002: fix "#define XXXX 1"
  atngw100: fix "#define XXXX 1"
  avr32: use single linker script
  avr32/config.mk: simplify PLATFORM_RELFLAGS
  avr32: fix linking
  Add support for Bluewater Systems Snapper 9260 and 9G20 modules
  ...
2011-05-18 14:31:56 +02:00
Andreas Bießmann
24890f1198 avr32: add ATAG_BOARDINFO
This patch adds a new ATAG_BORADINFO to U-Boot. This tag is intended to hand
over the bd->bi_board_number to the linux kernel for early stage board
information like a board revision or other kind of board specific decisions
necessary before the linux peripherial drivers are up.

Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
2011-05-18 07:56:54 +02:00
Andreas Bießmann
bb7dc6af20 avr32: use single linker script
This patch move the atstk100x linker script to $(CPUDIR) and delete other
pure copies of this file in each board directory.

Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
2011-05-18 07:56:53 +02:00
Andreas Bießmann
758472cc7b avr32/config.mk: simplify PLATFORM_RELFLAGS
This patch removes PLATFORM_RELFLAGS from board specific config.mk files and
define them in arch specific config.mk file.

Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
2011-05-18 07:56:53 +02:00
Andreas Bießmann
c8e7ddd4c6 avr32: fix linking
This patch fixes following error:

---8<---
avr32-linux-ld: --gc-sections and -r may not be used together
--->8---

Since 8aba9dceeb all avr32 boards are broken due
to linking error as seen above.

Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
2011-05-18 07:56:52 +02:00
Daniel Gorsulowski
1069a5cf30 at91: fixed at91sam9263 system file
Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
2011-05-18 07:56:52 +02:00
Jens Scharsig
673678eacf remove __attribute__ ((packed)) in at91 headers
* remove __attribute__ ((packed)) to prevent byte access
  to soc registers in some gcc version

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
2011-05-18 07:56:52 +02:00
Jens Scharsig
ce26582606 at91rm9200: fix lowlevel_init() SMRDATA size
* use start/end label for initialization tables instead of fix values

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
2011-05-18 07:56:52 +02:00
Reinhard Meyer
cfff263f41 AT91: fix timer.c - remove reset_timer()
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18 07:56:52 +02:00
Reinhard Meyer
50f750022b AT91: remove LEGACY from at91_rstc.h
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18 07:56:51 +02:00
Reinhard Meyer
86592f6059 AT91: change includes from asm/arch/io.h to asm/io.h
and remove the now unused asm/arch-at91/io.h

Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18 07:56:51 +02:00
Reinhard Meyer
60af568038 AT91: cleanup at91sam9260_matrix.h to struct SoC access
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18 07:56:51 +02:00
Reinhard Meyer
9f3fe90f09 AT91: fix related at91 system/driver files
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18 07:56:51 +02:00
Reinhard Meyer
83f1072e06 AT91: fix related arch-at91 header files
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18 07:56:51 +02:00
Reinhard Meyer
405e5919f2 AT91: cleanup hardware.h, remove memory-map.h
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18 07:56:50 +02:00
Reinhard Meyer
4b1f9b1b36 AT91: rework at91sam9g45.h
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18 07:56:50 +02:00
Reinhard Meyer
09aca70fa4 AT91: rework at91sam9263.h
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18 07:56:50 +02:00
Reinhard Meyer
5e5925930b AT91: rework at91sam9261.h
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18 07:56:50 +02:00
Reinhard Meyer
aa0f5ef20d AT91: rework at91sam9260.h
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2011-05-18 07:56:50 +02:00
Andreas Bießmann
f4278b716c avr32: fixup definitions to ATMEL_BASE_xxx
Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
2011-05-18 07:56:50 +02:00
Andreas Bießmann
5d73bc7af7 avr32: rename memory-map.h -> hardware.h
Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
2011-05-18 07:56:50 +02:00
Thomas Chou
e09e083f7f nios2: Make STANDALONE_LOAD_ADDR configurable per board
Follow commit 8ae86b76c6
which changed the variable name.

Fix this error,
nios2-elf-ld: invalid hex number `-o'

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2011-05-16 21:00:43 -04:00
York Sun
d49f8e04db powerpc/mpc8xxx: reword max tCKmin message
Reword "The DIMM max tCKmin is ..." to "The DDR clock is faster than the slowest
DIMM(s) can support". Fixed interger type in printf as well.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-05-13 00:36:11 -05:00
Timur Tabi
ee4756d4cb powerpc/85xx: fix compatible property for the L2 cache node
The compatible property for the L2 cache node (on 85xx systems that don't
have a CPC) was using a value for the property length that did not match
the actual length of the property.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-05-13 00:36:11 -05:00
Wolfgang Denk
0e0c0892a1 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2011-05-12 19:27:42 +02:00
Steven A. Falco
644362c40a PPC405EX CHIP_21 erratum
APM errata CHIP_21 for the 405EX/EXr (from the rev 1.09 document dated
4/27/11) states that rev D processors may wake up with the wrong feature
set.  This patch implements the APM-proposed workaround.

To enable this patch for your board, add the appropriate define for your
CPU to your board header file.  See kilauea.h for more information.  The
following variants are supported:

#define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY

Please note that if you select the wrong define, your board will not
boot, and JTAG will be required to recover.

Tested on custom boards using:

CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY  <sfalco@harris.com>
CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY     <eibach@gdsys.de>

Signed-off-by: Steve Falco <sfalco@harris.com>
Acked-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2011-05-12 16:10:51 +02:00
Simon Guinot
29d53d19f3 Kirkwood: allow to override CONFIG_SYS_TCLK
This patch allow to override CONFIG_SYS_TCLK from board configuration
files. This is needed for the Network Space v2 which use a non standard
core clock frequency (166MHz instead of 200MHz for a 6281 SoC).

As a possible enhancement for 6281 and 6282 devices, TCLK could be
dynamically detected by checking the Sample at Reset register bit 21.

Additionally this patch fix a typo.

Signed-off-by: Simon Guinot <sguinot@lacie.com>
Acked-by: Prafulla Wadaskar <Prafulla@marvell.com>
2011-05-11 23:03:15 +02:00
Stefano Babic
2f22045be5 MX31: change return value of get_cpu_rev
Drop warnings in get_cpu_rev and changes the return value
(a u32 instead of char * is returned) of the function
to be coherent with other processors.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Detlev Zundel <dzu@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
2011-05-11 23:03:15 +02:00
Stefano Babic
d109b11e54 MX31: removed warning due to missing prototype
Drop warning caused by missing prototype for
mxc_hw_watchdog_reset().

Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-05-11 23:03:15 +02:00
Wolfgang Denk
8c65b8a937 Merge branch 'master' of git://git.denx.de/u-boot-mips 2011-05-10 22:34:24 +02:00
Wolfgang Denk
909e9bf3ae Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2011-05-10 22:30:07 +02:00
Shinya Kuribayashi
68cebb8027 MIPS: Move timer code to arch/mips/cpu/$(CPU)/
Current timer routines (arch/mips/lib/timer.c) are implemented assuming
that MIPS32 coprocessor (CP0) resources, Counter and Compare registers
in this case, are available.  But this doesn't always work.

We need to make sure that all MIPS-based systems don't necessarily use
CP0 counter/compare registers as time keeping resources.  And some MIPS
variant processors might come with different hardware specs with genuine
MIPS32 CP0 registers.

With this change, each $(CPU)/ directory can have its own timer code.

Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-10 00:12:31 +09:00
Daniel Schwierzeck
660da0947a MIPS: Introduce --gc-sections for MIPS
All architectures but MIPS are using --gc-sections on final linking.
This patch introduces that feature for MIPS to reduce the memory and
flash footprint.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Thomas Lange <thomas@corelatus.se>
Cc: Vlad Lungu <vlad.lungu@windriver.com>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-10 00:08:10 +09:00
Shinya Kuribayashi
7aa1f198c8 MIPS: Coding style cleanups on common assembly files
Fix style issues and alignments globally.  No logical changes.
- Replace C comments with AS line comments where possible
- Use ifndef where possible, rather than if !defined for simplicity
- An instruction executed in a delay slot is now indicated by a leading
  space, not by C comment

Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-07 00:18:13 +09:00
Shinya Kuribayashi
522171a087 MIPS: Remove mips_cache_lock() feature
As requested in commit e1390801a3 ([MIPS]
Request for the 'mips_cache_lock()' removal), such feature is no longer
needed for current MIPS implementation of U-Boot, and no one in the tree
uses it for years.

Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-07 00:18:13 +09:00
Wolfgang Denk
aeabdeb7a3 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2011-04-30 22:45:55 +02:00
Scott Wood
83b7e2a7f2 Handle most LDSCRIPT setting centrally
Currently, some linker scripts are found by common code in config.mk.
Some are found using CONFIG_SYS_LDSCRIPT, but the code for that is
sometimes in arch config.mk and sometimes in board config.mk.  Some
are found using an arch-specific rule for looking in CPUDIR, etc.

Further, the powerpc config.mk rule relied on CONFIG_NAND_SPL
when it really wanted CONFIG_NAND_U_BOOT -- which covered up the fact
that not all NAND_U_BOOT builds actually wanted CPUDIR/u-boot-nand.lds.

Replace all of this -- except for a handful of boards that are actually
selecting a linker script in a unique way -- with centralized ldscript
finding.

If board code specifies LDSCRIPT, that will be used.
Otherwise, if CONFIG_SYS_LDSCRIPT is specified, that will be used.

If neither of these are specified, then the central config.mk will
check for the existence of the following, in order:

$(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds (only if CONFIG_NAND_U_BOOT)
$(TOPDIR)/$(CPUDIR)/u-boot-nand.lds (only if CONFIG_NAND_U_BOOT)
$(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
$(TOPDIR)/$(CPUDIR)/u-boot.lds

Some boards (sc3, cm5200, munices) provided their own u-boot.lds that
were dead code, because they were overridden by a CPUDIR u-boot.lds under
the old powerpc rules.  These boards' own u-boot.lds have bitrotted and
no longer work -- these lds files have been removed.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Tested-by: Graeme Russ <graeme.russ@gmail.com>
2011-04-30 00:59:47 +02:00
Heiko Schocher
62ddcf05e7 mpc832x: add support for the mpc8321 based suvd3 board
- serial console on UART1
- Ethernet RMII over UCC4
- PHY SMSC LAN8700
- 64MB Flash
- 128 MB DDR2 RAM
- I2C
- bootcount

This board is similiar to the kmeter1 (8360) board,
so common config options are extracted into the
include/configs/km83xx-common.h file.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
cc: Kim Phillips <kim.phillips@freescale.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
2011-04-30 00:44:29 +02:00
Kyle Moffett
a2879634c4 fsl-ddr: Fix mixed-case macro names
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-29 10:31:01 -05:00
Mingkai Hu
273feafefd powerpc: eSPI and eSPI controller support
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Singed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-29 07:34:09 -05:00
Kumar Gala
66412c6371 powerpc/85xx: Change timebase divisor to be defined per processor
Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because
different SoCs have different divisor amounts.  All the PQ3 parts are
/8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28 22:09:24 -05:00
Timur Tabi
d90fdba6ca powerpc/85xx: Implement work-around for P4080 erratum SERDES-A001
Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1
are swapped.

Erratum SERDES-A001 says that if bank two is kept disabled and after bank
three is enabled, then the PLL for bank three won't lock properly.  The
work-around is to enable and then disable bank two after bank three is
enabled.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28 22:09:23 -05:00
Timur Tabi
f68d306349 powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORA
Part of the SERDES9 erratum work-around is to set some bits in the SerDes
TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA.  The
current code does this only for XAUI, so extend it to the other protocols.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28 22:09:23 -05:00
Timur Tabi
7d6d9ba9d0 powerpc/85xx: Display SERDES 8 erratum warning if banks are not disabled
The work-around for P4080 erratum SERDES-8 requires all lanes of banks two
and three to be disabled (powered down) in the RCW.  Display a warning
message if this is not the case.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28 22:09:23 -05:00
Timur Tabi
da30b9fd97 powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005
SerDes PLL bandwidth default setting is incorrect when no lanes are
configured as PCI Express.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28 22:09:23 -05:00
Timur Tabi
ba8e76bd49 powerpc: use 'video-mode' environment variable to configure DIU
Use the 'video-mode' environment variable (for Freescale chips that have a
DIU display controller) to designate the full video configuration.  Previously,
the DIU driver used the 'monitor' variable, and it was used only to determine
the output video port.

The old definition of the "monitor" environment variable only determines
which video port to use for output.  This variable was set to a number (0,
1, or sometimes 2) to specify a DVI, LVDS, or Dual-LVDS port.  The
resolution was hard-coded into board-specific code.  The Linux command-line
arguments needed to be hard-coded to the proper video definition string.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2011-04-28 21:31:16 +02:00
Matthew McClintock
ae425c1eca powerpc/85xx: Don't set FT_FSL_PCI_SETUP if CONFIG_PCI is not set
A lot of boards set FT_FSL_PCI_SETUP directly in their board code
and don't check to see if CONFIG_PCI is actually defined. This
will cause the board compilation to fail if CONFIG_PCI is not
defined. The p1022ds board is one such example.

Instead of fixing every board this patch wraps FT_FSL_PCI_SETUP
around CONFIG_PCI so we can remove CONFIG_PCI and boards will
still build properly.

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:40:32 -05:00
Kim Phillips
416202f672 powerpc/85xx: handle both "secX.Y" and "sec-vX.Y" properties
versioned SEC properties changed names during development, so
for now search and update LIODNs for both "secX.Y" and
"sec-vX.Y" based properties.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:29:04 -05:00
Lei Xu
300097669c powerpc/85xx: Enable ESDHC111 erratum on P2040/P3041/P5010/P5020 SoCs
The workaround for ESDHC111 should also be applied on
P2040/P3041/P5010/P5020 SoCs.

Signed-off-by: Lei Xu <B33228@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:29:04 -05:00
Roy Zang
86221f09fb powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020
The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we
need to enable for them to function.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:29:04 -05:00
Kumar Gala
e02aea61cb powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code)
The P3041DS & P5020DS boards are almost identical (except for the
processor in them).  Additionally they are based on the P4080DS board
design so we use the some board code for all 3 boards.

Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have
meaning on P3041DS/P5020DS.  We utilize some of these for SERDES clock
configuration.

Additionally, the P3041DS/P5020DS support NAND.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:29:04 -05:00
Emil Medve
df8af0b4a6 p4080/serdes: Implement the XAUI workaround for SERDES9 erratum
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:29:04 -05:00
Emil Medve
3d28c5c8ed powerpc/85xx: fsl_corenet_serdes code rework
Rework and add some new APIs to the fsl_corenet_serdes code for use by
erratum and drivers.

* Rename serdes_get_bank() to serdes_get_bank_by_lane()
* Add serdes_get_first_lane returns which SERDES lane is used by device

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:29:04 -05:00
Haiying Wang
2a0ffb84c7 powerpc/85xx: Add device tree fixup for bman portal
Fix fdt bportal to pass the bman revision number to kernel via device tree.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:29:03 -05:00
Ramneek Mehresh
2bad42a0c8 powerpc/85xx: Add support for 2nd USB controller on p1_p2_rdb
Second USB controller only works for SPI and SD boot because of pin muxing

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2011-04-27 22:29:03 -05:00
Dipen Dudhat
4b77047c2a powerpc/85xx: Added PMUXCR1 and PMUXCR2 defines for P1010/P1014 SoC
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:29:03 -05:00
Dipen Dudhat
d7da1484cc powerpc/85xx: Change CS timing params before changing CS properties on IFC
To make sure that machine change operation work successfully, change
timing parameters first before changing machine for chip select on IFC.

Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:29:03 -05:00
Timur Tabi
1fade70203 powerpc: fix implementation of out_8 to match the other out_XX functions
Signed-off-by: Timur Tabi <timur@freescale.com>
2011-04-28 00:55:16 +02:00
Wolfgang Denk
f38536f913 Merge branch 'master' of git://git.denx.de/u-boot-arm 2011-04-27 21:48:09 +02:00
Minkyu Kang
d32a1a4caa Don't grab memory for LCD if FB address is defined
If FB address is defined specific address then don't grab memory for LCD

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Cc: Albert Aribaud <albert.aribaud@free.fr>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kumar Gala <kumar.gala@freescale.com>
2011-04-27 19:38:11 +02:00
Macpaul Lin
00d10eb041 ftsmc020: move ftsmc020 static mem controller to driver/mtd
Move the header file and definitions of ftsmc020
static memory control unit from a320 SoC folder to
"drivers/mtd" folder.

This change will let other SoC which also use ftsmc020
could share the same header file.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2011-04-27 19:38:10 +02:00
Macpaul Lin
5656b40bb3 ftsdmc020: move ftsdmc020.h to include/faraday
Move the header file "ftsdmc020.h" (SDRAM Controller)
to "include/faraday" folder.

This change will let other SoC which also use ftsdmc020
could share the same header file.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2011-04-27 19:38:10 +02:00
Luca Ceresoli
6cbec7b3ba ARMV7: OMAP3: Cleanup extern variables in mem.c
Removed boot_flash_* extern variables.
boot_flash_type was totally unused. The other ones were actually constants, so
they have been replaced with #defines in the board config files.

Signed-off-by: Luca Ceresoli <luca.ceresoli@comelit.it>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.aribaud@free.fr>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-04-27 19:38:10 +02:00
Tom Warren
c5e93131fa arm: Tegra2: GPIO: Add basic GPIO definitions
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-04-27 19:38:10 +02:00
Tom Warren
1436d51076 arm: Tegra2: Add missing PLLX init
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-04-27 19:38:09 +02:00
Eric Cooper
6445a3051e ARM: fix stack pointer adjustment in board_init_f()
Since addr_sp is a byte address, it should be adjusted by 12 here.

Signed-off-by: Eric Cooper <ecc@cmu.edu>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Wolfgang Denk <wd@denx.de>
2011-04-27 19:38:09 +02:00
Tom Warren
74652cf684 arm: Tegra2: add support for A9 CPU init
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-04-27 19:38:09 +02:00
Luca Ceresoli
c2b626c199 ARMV7: OMAP3: Add GPMC_CONFIGx register value definitions
Signed-off-by: Luca Ceresoli <luca.ceresoli@comelit.it>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-04-27 19:38:09 +02:00
Luca Ceresoli
b32e8126a3 ARMV7: OMAP3: Fix preprocessor check for CONFIG_OMAP34XX
CONFIG_OMAP34XX must be checked for existence, not value.

Signed-off-by: Luca Ceresoli <luca.ceresoli@comelit.it>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.aribaud@free.fr>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-04-27 19:38:09 +02:00