Commit graph

17488 commits

Author SHA1 Message Date
Ashok Reddy Soma
34dec6a443 cadence_qspi: Enable flash reset for Versal NET platform
Enable flash reset functionality for Versal NET platform.
In cadence_qspi.c there is weak function defined for reset, hence remove
the check for config, so that it will work for Versal and Versal NET
platforms.

Add register defines in Versal NET hardware.h for mini U-Boot flash
reset.

Add read_delay initialization for Versal NET also.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614120452.21019-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21 09:00:38 +02:00
Sharath Kumar Dasari
85a2d124cd arm64: zynqmp: Fix the memory node for k26/k24 kria som boards
PMUFW requires top 1MB of the lower DDR memory reserved for its operation,
this is missing in k26/k24 sm static dts files because of which U-Boot
throws warning messages "efi_free_pool: illegal free" as EFI puts
some code to that space which shouldn't happen.

Signed-off-by: Sharath Kumar Dasari <sharath.kumar.dasari@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/57452d16df2d48593de206bebf877d2c2cfe7bf1.1685966389.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Tom Rini
e896279ac3 binman mkimage and template enhancements
misc fixes
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Merge tag 'dm-pull-20jul23' of https://source.denx.de/u-boot/custodians/u-boot-dm

binman mkimage and template enhancements
misc fixes
2023-07-20 21:31:31 -04:00
Mikhail Kalashnikov
ecb896cec7 sunxi: H616: add LPDDR3 DRAM support
The H616 SoC has support for several types of DRAM: DDR3, LPDDR3,
DDR4 and LPDDR4.
At the moment, the driver only supports DDR3 memory.
Let's extend the driver to support the LPDDR3 memory. All "magic"
values obtained from the boot0.

Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-07-21 00:54:19 +01:00
Mikhail Kalashnikov
5d6f013adc sunxi: H616: add DRAM type selection
Allwinner H616 SoC supports several types of DRAM memory. To further
integrate other types of memory, we need to add this delimitation.

Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-07-21 00:54:13 +01:00
Andre Przywara
78aa00c38e sunxi: H616: dram: split struct dram_para
Currently there is one DRAM parameter struct for the Allwinner H616 DRAM
"driver". It contains many fields that are compile time constants
(set by Kconfig variables), though there are also some fields that are
probed and changed over the runtime of the DRAM initialisation.

Because of this mixture, the compiler cannot properly optimise the code
for size, as it does not consider constant propagation in its full
potential.

Help the compiler out by splitting that structure into two: one that only
contains values known at compile time, and another one where the values
will actually change. The former can then be declared "const", which will
let the compiler fold its values directly into the code using it.

We also add "const" tags for some new "struct dram_config" pointers, to
further increase code optimisation.
To help the compiler optimise the code further, the definition of the
now "const struct dram_para" has to happen at a file-global level, so
move that part out of sunxi_dram_init().

That results in quite some code savings (almost 2KB), and helps to keep
the code small with the LPDDR3 support added later.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21 00:29:42 +01:00
Andre Przywara
457e2cd665 sunxi: H616: dram: const-ify DRAM function parameters
There are quite some functions in the Allwinner H616 DRAM "driver", some
of them actually change the parameters in the structure passed to them,
but many are actually not.
To increase the optimisation potential for the code, mark those functions
that just read members of the passed dram_para struct as "const".
This in itself does not decrease the code size, but lays the groundwork
for future changes doing so.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21 00:29:42 +01:00
Andre Przywara
c9dd624a38 sunxi: dram: make MBUS configuration functions static
The usage of the C keyword "inline" seems to be a common
misunderstanding: it's a *hint* only, and modern compilers will inline
(or not) functions based on their own judgement and provided compiler
options.
So while marking functions as "inline" does not do much, missing the
"static" keyword will force to compiler to spell out a version of the
function for potential external callers, which actually increases the
code size (though hopefully the linker will drop the function).

Change the "inline" attribute for the mbus_configure_port() functions in
some Allwinner DRAM drivers to "static", so that the explicit version
can actually be dropped from the object file, reducing the code size.

"static inline" has a use case in header files, where it avoids a warning
if a .c file including this header does not use the particular function.
In a .c file itself "static inline" is not useful otherwise, so just use
static here as well.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21 00:29:42 +01:00
Andre Przywara
fcd9220d66 sunxi: Kconfig: rework PHY_USB_SUN4I selection
At the moment we use "select" in each Allwinner SoC's Kconfig section to
include the USB PHY driver in the build. This means it cannot be disabled
via Kconfig, although USB is not really a strictly required core
functionality, and a particular board might not even include USB ports.

Rework the Kconfig part by removing the "select" lines for each SoC's
section, and instead letting it default to "y" in the PHY driver section
itself. We use "depends on !" to exclude the few SoCs we don't support
(yet). The Allwinner V3s does not enable USB (PHY) support at the moment,
even though it should work: let the PHY default to "n" to keep the
current behaviour.

Also the MUSB USB driver directly calls some functions from the PHY
driver, so let the former depend on the PHY driver.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Sam Edwards <CFSworks@gmail.com>
2023-07-21 00:26:36 +01:00
Simon Glass
8163907adf stm32mp15: Avoid writing symbols in SPL
These boards use SPL in a mkimage entry and apparently access the symbol
containing the image position of U-Boot, but put U-Boot in another
image. This means that binman is unable to fill in the symbol correctly
in the SPL binary.

This doesn't matter at present since mkimage doesn't support symbol
writing. But with the upcoming conversion to a section, it will. So add
a property to disable symbol writing.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-20 14:10:58 -06:00
Tom Rini
9ef4166ff9 arm: mx5: Correct mxc_set_clock function prototype
With gcc-13.1 we get a warning about enum vs int here, so correct the
declaration to match the implementation.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-07-20 14:48:20 -04:00
Jim Liu
4b7f29ff14 arch: arm: npcm8xx: add cpu version and 4G ram support
Add npcm8xx A2 cpu version check
and add 4G RAM support

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-07-14 12:52:18 -04:00
Jim Liu
f4e086cdf1 ARM: dts: npcm8xx: fix dts node error
The SHA and OTP should under the ahb node

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-07-14 12:52:18 -04:00
Tom Rini
c990ecba4d Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- mvebu: Thecus: Misc enhancement and cleanup (Tony)
- mvebu: Add AC5X Allied Telesis x240 board support incl NAND
  controller enhancements for this SoC (Chris)
2023-07-13 20:38:50 -04:00
Chris Packham
366a863e65 arm: mvebu: Remove unused alias from RC AC5X dts
The sar-reg0 alias was left over from an earlier iteration of the
patches adding support for this board. Remove the unused alias.

Fixes: 6cc8b5db40 ("arm: mvebu: Add RD-AC5X board")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-07-13 15:54:11 +02:00
Chris Packham
4c97c4b590 arm: mvebu: Add Allied Telesis x240 board
The x240 and SE240 are a series of L2+ switches from Allied Telesis.
There are a number of them in the range but as far as U-Boot is
concerned all the CPU block components are the same so there's only one
board defined.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-07-13 15:53:57 +02:00
Fabio Estevam
e713364f36 mx23_olinuxino: Convert to CONFIG_DM_SERIAL
The conversion to CONFIG_DM_SERIAL is mandatory, so select this option.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-07-13 11:29:41 +02:00
Fabio Estevam
9a38d889a1 mx23evk: Convert to CONFIG_DM_SERIAL
The conversion to CONFIG_DM_SERIAL is mandatory, so select this option.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-07-13 11:29:41 +02:00
Fabio Estevam
68bad63ee0 mx28evk: Convert to CONFIG_DM_SERIAL
The conversion to CONFIG_DM_SERIAL is mandatory, so select this option.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-07-13 11:29:41 +02:00
Andrejs Cainikovs
214a986f13 arm64: dts: verdin-imx8mp: add ctrl_sleep_moci# hog
Drive CTRL_SLEEP_MOCI# high at boot (SPL) using a GPIO hog, this signal
may be used to control some power-rails on the carrier board, therefore
it should be set to high when the module is booting.

To do this as early as possible is generally a good idea and the issue
was noticed on the Yavia carrier board where it is needed to power the
I2C EEPROM on the carrier board.

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-07-13 11:29:41 +02:00
Andrejs Cainikovs
cf77093e31 arm64: dts: verdin-imx8mm: add ctrl_sleep_moci# hog
Drive CTRL_SLEEP_MOCI# high at boot (SPL) using a GPIO hog, this signal
may be used to control some power-rails on the carrier board, therefore
it should be set to high when the module is booting.

To do this as early as possible is generally a good idea and the issue
was noticed on the Yavia carrier board where it is needed to power the
I2C EEPROM on the carrier board.

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-07-13 11:29:41 +02:00
Marcel Ziswiler
cd9a3e3f90 verdin-imx8mm/verdin-imx8mp: synchronise device trees with linux
Synchronise device trees with linux v6.5-rc1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-07-13 11:29:40 +02:00
Adam Ford
788ff422e5 arm: dts: imx8mp-beacon-kit: Enable USB Power domains
The USB Power domains should not have been removed as it causes
the board to hang if the USB is started.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-07-13 11:29:40 +02:00
Adam Ford
451799a6ce arm: dts: imx8mp: Sync the DT with kernel 6.4-rc4
Several changes have been made to the device tree
in the kernel, so update that as well as the
corresponding imx8mp-u-boot.dtsi files to prevent
breaking the booting.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-07-13 11:29:40 +02:00
Hugo Villeneuve
1b4c3e6125 imx8mn-var-som: adjust PHY reset gpios according to hardware configuration
For SOM with the EC configuration, the ethernet PHY is located on the
SOM itself, and connected to the CPU ethernet controller. It has a
reset line controlled via GPIO1_IO9. In this configuration, the PHY
located on the carrier board is not connected to anything and is
therefore not used.

For SOM without EC configuration, the ethernet PHY on the carrier
board is connected to the CPU ethernet controller. It has a reset line
controlled via the GPIO expander PCA9534_IO5.

The hardware configuration (EC) is determined at runtime by
reading from the SOM EEPROM.

To support both hardware configurations (EC and non-EC), adjust/fix
the PHY reset gpios according to the hardware configuration
read at runtime from the SOM EEPROM. This adjustement is done in
U-Boot (OF_BOARD_FIXUP) and kernel (OF_BOARD_SETUP) device trees.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2023-07-13 11:29:40 +02:00
Marek Vasut
cb5fe9e336 ARM: imx: romapi: Fix signed integer bitwise ops misuse
Bitwise operations on signed integers are not defined,
replace them with per-call checks.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-07-13 11:29:40 +02:00
Tim Harvey
c8645e7411 configs: imx8m: Prepare imx8m-venice boards for HAB support
In order to enable HAB, FSL_CAAM, ARCH_MISC_INIT and
SPL_CRYPTO should be enabled in Kconfig like other i.MX8M
boards.

This also needs to occur in the SPL so enable CONFIG_SPL_BOARD_INIT and
add a void spl_board_init function which calls arch_misc_init to probe
the CAAM driver.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Maximus Sun
2159f7d9b6 imx: priblob: Update to use structure
Use structure to avoid define CAAM_SCFGR for each platform

Signed-off-by: Maximus Sun <maximus.sun@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
14d7eedf77 imx: imx8m: add CAAM_BASE_ADDR
Add CAAM_BASE_ADDR which will be used by priblob.c

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Gaurav Jain
d7b5fba9a5 imx: imx8: ahab: sha256: enable image verification using ARMv8 crypto extension
add support for SHA-256 secure hash algorithm using the ARM v8
SHA-256 instructions for verifying image hash.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Ye Li
00ce4153fb imx: ahab: Update AHAB for iMX8 and iMX8ULP
Abstract common interfaces for AHAB authentication operations.
Then share some common codes for AHAB and SPL container authentication

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Nitin Garg
6e81ca220e imx: parse-container: Use malloc for container processing
If the container has image which conflicts with
spl_get_load_buffer address, there are processing failures.
Use malloc instead of spl_get_load_buffer.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
dc2d49209e imx: imx8m: clock: not configure reserved SRC register
i.MX8M[M,N,P] SRC not has 0x1004 offset register, so drop it.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Ye Li
e8cd1f60d9 imx: imx8: bootaux: Add i.MX8 M4 boot support
1. Implement bootaux for the M4 boot on i.MX8QM and QXP. Users need to download
   M4 image to any DDR address first. Then use the
   "bootaux <M4 download DDR address> [M4 core id]" to boot CM4_0
   or CM4_1, the default core id is 0 for CM4_0.

   Since current M4 only supports running in TCM. The bootaux will copy
   the M4 image from DDR to its TCML.

2. Implment bootaux for HIFI on QXP
   command: bootaux 0x81000000 1

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Ye Li
8d84a8f487 imx: bootaux: Fix bootaux issue when running on ARM64
The bootaux uses ulong to read private data and write to M4 TCM,
this cause problem on ARM64 platform where the ulong is 8bytes.
Fix it by using u32 to replace ulong.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
9395eb05ee imx: bootaux: change names of MACROs used to boot MCU on iMX devices
The current bootaux supports i.MX8M and i.MX93, but the name "_M4_"
implies that the SoCs have Cortex-M4. Actually i.MX8MM/Q use Cortex-M4,
i.MX8MN/P use Cortex-M7, i.MX93 use Cortex-M33, so use "_MCU_" in place
of "_M4_" to simplify the naming.

Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
455ebf8f45 imx: iamge-container: support secondary container
Add the support for loading image from secondary container set on
iMX8QM B0, iMX8QXP C0.

Using the SCFW API to get container set index, if it is the secondary
boot, get the offset from fuse and apply to offset of current container
set beginning for loading.

Also override the emmc boot partition to check secondary boot and switch
to the other boot part.

This patch is modified from NXP downstream:
imx8: Fix the fuse used by secondary container offset
imx: container: Skip container set check for ROM API
imx8: spl: Support booting from secondary container set

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Ye Li
3b5c1d0ea1 imx: image-container: Fix container header checking
Checking container header tag and version is wrong, it causes to fail
to bypass invalid container

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Ye Li
b645f95da9 imx: hab: Fix coverity issue in HAB event decoding
Fix below coverity issues caused by get_idx function where "-1" is
compared with uint8_t "element"
343336 Unsigned compared with neg
343337 Operands don't affect result

Additional, this function returns "-1" will cause overflow to
event string array.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
1c3f5df259 imx: imx8ulp: start the ELE RNG at boot
On the imx8ulp A1 SoC, the ELE RNG needs to be manually started.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Clement Faure
859f4e02a8 imx: cmd_dek: add ELE DEK Blob generation support
Add ELE DEK Blob generation for the cmd_dek command.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Ye Li
f0e974e1e4 imx: cmd_dek: Fix Uninitialized pointer read
Fix Coverity (CID 21143558).
When tee_shm_register returns failure, the shm_input pointer is
invalid, should not free it. Same issue also exists on registering
shm_output.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
d0e2a012a3 imx: ele_api: add DEK Blob generation
- Add crc computation.
- Add ele_generate_dek_blob API for encrypted boot support.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
31e5ec2323 imx: ele_api: support program secure fuse and return lifecycle
Add two ELE API: ele_return_lifecycle_update and ele_write_secure_fuse
Add two cmd: ahab_return_lifecycle and ahab_sec_fuse_prog

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
ef5bdfc273 imx: ele_ahab: use hextoul
Use hextoul which looks a bit simpler.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
914ede6978 imx: parse-container: fix build warning
Fix build warning:
warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 3
has type ‘u64’ {aka ‘long long unsigned int’} [-Wformat=]
         printf("can't find memreg for image %d load address 0x%x, error %d\n",
warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but
argument 3 has type ‘sc_faddr_t’ {aka ‘long long unsigned int’} [-Wformat=]
          debug("memreg %u 0x%lx -- 0x%lx\n", mr, start, end);

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
d3ee9dbd59 imx: use generic name ele(EdgeLockSecure Enclave)
Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave
code including comment, folder and API name to ELE to align.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
dd654caac0 imx: mach: correct SCU API usage
The return value is int type, not sc_err_t(u8), correct the usage.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Chris Packham
f52e2d884c arm: mvebu: ac5: Define mvebu_get_nand_clock()
The NF_CLK for the AC5 SoC runs at 400MHz. There's no strapping
or gating require so just add a mvebu_get_nand_clock() that
returns this value.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-07-13 10:26:27 +02:00
Chris Packham
b04c21afd6 arm: mvebu: ac5: Add nand-controller node
The AC5/AC5X SoC has a NAND flash controller. Add this to the
SoC device tree.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-07-13 10:26:27 +02:00
Tony Dinh
71222816d2 arm: mvebu: Enable gpio-fan for Thecus N2350 board
Add gpio-fan in the DTS and enable the GPIO in board file to start the fan
during boot.

Note that this patch depends on
https://patchwork.ozlabs.org/project/uboot/patch/20230606214539.4229-1-mibodhi@gmail.com/

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-07-13 10:26:27 +02:00
Tony Dinh
f69f67e4ef arm: mvebu: Clean up Thecus N2350 board DTS
- Update the Thecus N2350 DTS to conform with latest device-tree binding
and styles.
- Correct typo in mdio node.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Pali Rohár <pali@kernel.org>
2023-07-13 10:26:27 +02:00
Tim Harvey
48c6f9777c board: gateworks: venice: add imx8mp-gw7905-2x support
The Gateworks imx8mp-venice-gw7905-2x consists of a SOM + baseboard.

The GW702x SOM contains the following:
 - i.MX8M Plus SoC
 - LPDDR4 memory
 - eMMC Boot device
 - Gateworks System Controller (GSC) with integrated EEPROM, button
   controller, and ADC's
 - PMIC
 - SOM connector providing:
  - eQoS GbE MII
  - 1x SPI
  - 2x I2C
  - 4x UART
  - 2x USB 3.0
  - 1x PCI
  - 1x SDIO (4-bit 3.3V)
  - 1x SDIO (4-bit 3.3V/1.8V)
  - GPIO

The GW7905 Baseboard contains the following:
 - GPS
 - microSD
 - off-board I/O connector with I2C, SPI, GPIO
 - EERPOM
 - PCIe clock generator
 - 1x full-length miniPCIe socket with PCI/USB3 (via mux) and USB2.0
 - 1x half-length miniPCIe socket with USB2.0 and USB3.0
 - USB 3.0 HUB
 - USB Type-C with USB PD Sink capability and peripheral support
 - USB Type-C with USB 3.0 host support

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2023-07-11 14:40:05 +02:00
Hugo Villeneuve
2ae1267342 imx8mn-var-som: read eth MAC address from EEPROM
Read ethernet MAC address from EEPROM located on the SOM.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2023-07-11 14:40:04 +02:00
Hugo Villeneuve
89bd008da4 arm: dts: imx8mn-var-som: fix PHY detection bug by adding deassert delay
While testing the ethernet interface on a Variscite symphony carrier
board using an imx8mn SOM with an onboard ADIN1300 PHY (EC hardware
configuration), the ethernet PHY is not detected.

The ADIN1300 datasheet indicate that the "Management interface
active (t4)" state is reached at most 5ms after the reset signal is
deasserted.

The device tree in Variscite custom git repository uses the following
property:

    phy-reset-post-delay = <20>;

Add a new MDIO property 'reset-deassert-us' of 20ms to have the same
delay inside the ethphy node. Adding this property fixes the problem
with the PHY detection.

Note that this SOM can also have an Atheros AR8033 PHY. In this case,
a 1ms deassert delay is sufficient. Add a comment to that effect.

Fixes: c4c1ed68c1 ("imx8mn_var_som: Add support for Variscite
VAR-SOM-MX8M-NANO board")

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2023-07-11 14:40:04 +02:00
Hugo Villeneuve
26f4bfae73 imx8mn-var-som: fix non-applied PHY reset-gpios properties
Select DM_ETH_PHY so that the reset-gpios property of the ethphy node
can be used.

Also select DM_PCA953X, which is needed for resetting the
ethernet PHY on the carrier board via the PCA9534 I/O expander.

Commit 4e5114daf9 ("imx8mn: synchronise device tree with linux") did
synchronise device tree with linux, which in effect removed obsolete
PHY reset properties and replaced them with new mdio DM
properties. But the commit didn't activate DM_ETH_PHY or DM_PCA953X.

Fixes: 4e5114daf9 ("imx8mn: synchronise device tree with linux")

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2023-07-11 14:40:04 +02:00
Hugo Villeneuve
fc1b8e1e7e imx8mn-var-som: read and print SoM infos from eeprom on startup
Enable support to read and display configuration/manufacturing infos
from 4Kbit EEPROM located on SOM board.

Note: CONFIG_DISPLAY_BOARDINFO is automatically selected for ARM arch.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2023-07-11 14:40:04 +02:00
Rasmus Villemoes
cb4e79b7ba imx8m: soc.c: demote some printfs to debug
Getting

  Found /vpu_g1@38300000 node
  Modify /vpu_g1@38300000:status disabled
  Found /vpu_g2@38310000 node
  Modify /vpu_g2@38310000:status disabled

etc. on the console on every boot is needlessly verbose. Demote the
"Found ..." lines to debug(), which is consistent with other instances
in soc.c.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-07-11 14:40:04 +02:00
Lukasz Majewski
474c086651 arm: Kconfig: Switch XEA (imx287 based) board to use CONFIG_PL01X_SERIAL
The CONFIG_PL011 used by all other ARCH_MX28 based boards is not
supporting DM_SERIAL. Instead, other define - namely CONFIG_PL01X_SERIAL
shall be used by boards supporting DM_SERIAL.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2023-07-11 14:40:04 +02:00
Lukasz Majewski
191f683ee2 arm: mxs: Prevent serial console init when in very early SPL boot code
When DM_SERIAL is enabled on mxs (i.e. imx28) platform, the console
early initialization must be postponed until the driver model is
correctly setup.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2023-07-11 14:40:04 +02:00
Lukasz Majewski
b8ce78a8c9 dts: xea: Disable 'clks' node for xea (imx287)
As imx28 family of SoCs is NOT supporting the Common Clock Framework (CCF)
the 'clks' property shall NOT be enabled by default.

Without this change u-boot proper before relocation tries to bind driver
(which doesn't exists) for this device. As a result, pre-relocation DTB
parsing is finished with error and the board hangs in a very early stage
of u-boot proper boot process.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2023-07-11 14:40:04 +02:00
Lukasz Majewski
01744484cb dts: xea: Remove clocks property from debug UART on XEA
The imx287 SoC doesn't support common clock framework (CCF), so the
'clocks' property is removed to avoid early (i.e. in SPL) errors when
SPL_OF_PLATDATA is used.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2023-07-11 14:40:04 +02:00
Lukasz Majewski
70b4d610f8 dts: xea: Add u-boot specific 'type' property to duart
The DM_SERIAL implicitly requires CONFIG_PL01X_SERIAL, which
allows support for both serial IP block versions (i.e. PL011 and
PL010).

The decision about used IP block is based on the compatible string,
when DM is used.

In the XEA, the OF_PLATDATA is used to allow usage of serial driver in
the SPL (as the size of SPL is crucial). In this case one cannot extract
the type of IP block from .data field (corresponding to compatible) and
it must be explicitly read at probe from dtoc generated, u-boot specific
property.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2023-07-11 14:40:04 +02:00
Lukasz Majewski
9a1efecb2c dts: xea: Enable debug UART support in XEA's SPL (DM_SERIAL)
After enabling DM_SERIAL for XEA board, the same serial shall be used
in the SPL (with SPL_OF_PLATDATA support).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2023-07-11 14:40:04 +02:00
Lukasz Majewski
c5e8c336ec dts: xea: Provide missing FEC required properties (mac0 and reg_fec_3v3)
After the commit (SHA1: 7d08ddd09b) some
u-boot specific XEA FEC related properties have been replaced by ones
from the Linux kernel.

To be more specific - XEA board (and imx287 in general) has built L2
switch connected to FEC, which needs some special treatment.

In u-boot it is handled with 'mac0' node, whereas Linux uses dedicated
switch DTS node.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2023-07-11 14:40:04 +02:00
Lukasz Majewski
0d30b6c4ec dts: xea: Delete not used in u-boot DTS nodes
After the re-sync with Linux Kernel's DTS
(SHA1: 7d08ddd09b), the XEA's
descripion has nodes and properties, which are NOT utilized
in the u-boot.

To avoid confusion - those are deleted.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2023-07-11 14:40:04 +02:00
Lukasz Majewski
301c6e6e69 arm: mxs: Add function to dump PMU registers
This commit provides function, which when debugging
output is enabled dumps the IMX28 PMU registers.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2023-07-11 14:40:03 +02:00
Lukasz Majewski
79230640cb arm: mxs: Provide Kconfig option to not enable 4P2 regulator in IMX28 PMU
The IMX28 PMU (Power Management Unit) has a dedicated Linear Regulator
to produce (by default) 4.2V output - available outside the chip as
VDD_4P2.

When system is supposed to not use VDD5V as a main power source - instead
the DCDC_BATT is used; it is safe to disable this regulator.

As the in-PMU DCDC switching regulator (from which DCDC_VDDA, DCDC_VDDIO
and DCDC_VDDD are generated) can be driven from DCDC_BATT or output
of this 4P2 regulator - by disabling the latter the use of the DCDC_BATT
is forced.

To be more specific - according to NXP's AN4199 the DCDC_BATT source is
preferred (over VDD5V), as more efficient and stable source for
industrial applications.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2023-07-11 14:40:03 +02:00
Lukasz Majewski
249a3cc1af arm: mxs: Provide Kconfig option to disable battery charging at IMX28 PMU
This new Kconfig option allows disabling the in-PMU battery charging
block. This may be required when DCDC_BAT source is powered not from
battery, but from already regulated, good quality source.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2023-07-11 14:40:03 +02:00
Lukasz Majewski
1c3c601ac5 arm: mxs: Provide Kconfig option to to not use VDD5V as IMX28 PMU source
This option sets the current limit for 5V source to zero, so all
the PMU outputs are primarily powered from battery source (DCDC_BAT).

This option may be set on systems, where the 5V is NOT supposed to be
in any scenario powering the system - for example on systems where
DCDC_BAT is connected to fixed and regulated 4.2V source (so the
"battery" is not present).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2023-07-11 14:40:03 +02:00
Oleksandr Suvorov
d31ffce81d ARM: imx9: support env in fat and ext4
Change boot device logic to also allow environment stored in fat and
in ext4 when booting from SD or eMMC.

As the boot device check for SD and for eMMC was depending on
ENV_IS_IN_MMC being defined, change the ifdef blocks at
env_get_location to use IS_ENABLED instead for all modes, returning
NOWHERE when no valid mode is found.

This solution is based on (with added SPL support):
Link: https://lore.kernel.org/all/20211020191626.3648540-1-ricardo@foundries.io/
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-07-11 14:40:02 +02:00
Giulio Benetti
04e08e3c54 arm: mx6: module_fuse: fix build failure due to wrong argument name
nodeoff variable should be variable off returned by fdt_path_offset() so
let's rename it to off.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-07-11 14:40:02 +02:00
Adam Ford
5054560e0c imx: imx8mm-beacon: Enable FlexSPI in U-Boot
In order to use the FlexSPI interface in U-Boot, configure
the alias to make spi0 point to flexspi.

With that enabled, sf probe detects the QSPI part as:
SF: Detected n25q256ax1 with page size 256 Bytes, erase size 4 KiB, total 32 MiB

Signed-off-by: Adam Ford <aford173@gmail.com>
2023-07-11 14:40:02 +02:00
Camelia Groza
cc6f1bf0a2 arch: arm: dts: ls1046a: tag serial nodes with bootph-all
Make sure the serial driver is initialized before relocation by tagging
the serial nodes with "bootph-all".

In order to keep the serial nodes in sync with their representation in
the Linux dts, add these u-boot specific properties to *-u-boot.dtsi
files.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-07-06 13:04:55 +08:00
Camelia Groza
250f745ae8 arch: arm: dts: ls1046a: sync serial nodes with Linux
Pick up the serial node descriptions from Linux v6.3 for the ls1046ardb
and ls1046afrwy boards and their dependencies. Including the
fsl,qoriq-clockgen.h and arm-gic.h headers forces us to change the include
directives to explicitly go through the C preprocessor for all boards in
the ls1046a SoC family.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-07-06 13:04:55 +08:00
Camelia Groza
164d1ae5b0 arch: arm: dts: ls1043a: tag serial nodes with bootph-all
Make sure the serial driver is initialized before relocation by tagging
the serial nodes with "bootph-all".

In order to keep the serial nodes in sync with their representation in
the Linux dts, add these u-boot specific properties to *-u-boot.dtsi
files.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-07-06 13:04:55 +08:00
Camelia Groza
41651ea098 arch: arm: dts: ls1043a: sync serial nodes with Linux
Pick up the serial node descriptions from Linux v6.3 for the ls1043ardb
board and its dependencies. Including the fsl,qoriq-clockgen.h and
arm-gic.h headers forces us to change the include directives to explicitly
go through the C preprocessor for all boards in the ls1043a SoC family.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-07-06 13:04:54 +08:00
Tom Rini
e80f4079b3 Prepare v2023.07-rc6
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Merge tag 'v2023.07-rc6' into next

Prepare v2023.07-rc6
2023-07-05 11:28:55 -04:00
Fabio Estevam
a1ddcf7cee sunxi: u-boot-spl.lds: Pass _image_binary_end
Pass _image_binary_end to make a standard way to indicate the end
of the text section in SPL.

The motivation for this is to have a uniform way to handle
the SPL boundary checks.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-07-03 10:20:13 -04:00
Marek Vasut
2b17dd1d9d ARM: arm11: Add C wrapper for allow_unaligned()
Rename current assembler implementation of allow_unaligned() to
arm11_arch_cp15_allow_unaligned() and add it into arm11.h header,
then add C wrapper of allow_unaligned().

This fixes misbehavior when linking U-Boot, where the CPU specific
allow_unaligned() implementation was ignored and instead the
__weak allow_unaligned() implementation from lib/efi_loader/efi_setup.c
was used, which led to "data abort" just before booting Linux via tftp,
in efi_dp_from_file() -> path_to_uefi() -> utf16_put() .

The problem is triggerd by c7c0ca3767 ("efi_loader: fix efi_dp_from_file()") .
Adding the wrapper fixes the problem.

Fixes: d47a774680 ("arm: arm11: allow unaligned memory access")
Signed-off-by: Marek Vasut <marex@denx.de>
2023-07-01 17:29:15 +02:00
Marek Vasut
c32248601c ARM: armv7: Add C wrapper for allow_unaligned()
Rename current assembler implementation of allow_unaligned() to
v7_arch_cp15_allow_unaligned() and add it into armv7.h header,
then add C wrapper of allow_unaligned().

This fixes misbehavior when linking U-Boot on ARMv7a i.MX6Q, where the
CPU specific allow_unaligned() implementation was ignored and instead the
__weak allow_unaligned() implementation from lib/efi_loader/efi_setup.c
was used, which led to "data abort" just before booting Linux via tftp,
in efi_dp_from_file() -> path_to_uefi() -> utf16_put() .

The problem is triggerd by c7c0ca3767 ("efi_loader: fix efi_dp_from_file()") .
Adding the wrapper fixes the problem.

Fixes: 78f90aaeec ("arm: armv7: allow unaligned memory access")
Signed-off-by: Marek Vasut <marex@denx.de>
2023-07-01 17:29:15 +02:00
Svyatoslav Ryhel
bdf9dead86 board: htc: endeavoru: add One X support
The HTC One X is a touchscreen-based, slate-sized smartphone
designed and manufactured by HTC that runs the Android operating
system. The One X features a 4.7" display, an Nvidia Tegra 3
quad-core chip, 1 GB of RAM and non-extendable 32 GB of internal
storage. UART-A is default debug port.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com>
Tested-by: Ion Agorria <ion@agorria.com>
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-30 15:20:37 +02:00
Svyatoslav Ryhel
623a8c812e board: lg: x3: add Optimus 4X HD and Optimus Vu support
LG X3 is a development board based on Nvidia Tegra 3 SoC
on base of which Optimus 4X HD and Optimus Vu were created.
Both smartphones feature a 4.7" and 5" panels respectively,
an Nvidia Tegra 3 quad-core chip, 1 GB of RAM and 16/32 GB
of internal storage. Optimux 4X HD additionally has a micro
SD slot.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # LG P880 T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-30 15:20:37 +02:00
Svyatoslav Ryhel
855ffdfa65 board: asus: grouper: add Google Nexus 7 (2012) support
Nexus 7 is a mini tablet computer co-developed by Google and Asus
that runs the Android operating system. The Nexus 7 features a 7"
display, an Nvidia Tegra 3 quad-core chip, 1 GB of RAM and 8/16 GB
of internal storage.

This patch brings support for all 3 known ASUS/Google devices:
- Nexus 7 (2012) E1565
- Nexus 7 (2012) PM269
- Nexus 7 (2012) 3G - tilapia

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS Grouper E1565
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-30 15:20:37 +02:00
Svyatoslav Ryhel
15be9a7b3b board: asus: transformer: add ASUS Transformer T30 family support
The ASUS Transformer T30 family are 2-in-1 detachable tablets
and AiO developed by ASUS that run the Android operating system
(TF600T runs Windows RT and P1801-T runs Android and Windows).
The T30 Transformers feature a 10.1-inch display (apart P1801-T),
an Nvidia Tegra 3 quad-core chip, 1/2 GB of RAM, and 16/32 GB of
storage. Transformers board derives from Nvidia Cardhu development
board.

This patch brings support for 7 known Transformer devices:
- ASUS Transformer Prime TF201
- ASUS Transformer Pad TF300T/TF300TG/TF300TL
- ASUS VivoTab RT TF600T (Windows RT based)
- ASUS Transformer Infinity TF700T
- ASUS Portable AiO P1801-T

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # all devices
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-30 15:20:37 +02:00
Svyatoslav Ryhel
d83721f1d4 ARM: tegra: add SoC UID calculation function
This is a small tool for calculation of SoC UID based on the same
Linux function. It can be further used for generation of device
unique data like mac address or exposing it as serial number.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-30 15:20:37 +02:00
Eugen Hristev
d77d5301d7 board: rockchip: rock5b-rk3588: fix description
Update description with correct specifications

Fixes: 3bf8e40807 ("board: rockchip: add Radxa ROCK5B Rk3588 board")
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-06-29 18:43:42 +08:00
Alexey Romanov
eb0a01e603 arch/arm: meson: sm: introduce power domain functions
This commit adds functions to manage secure power domain for
Amlogic SoC's using smc functionality.

Signed-off-by: Alexey Romanov <avromanov@sberdevices.ru>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230531093156.29240-2-avromanov@sberdevices.ru
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-06-28 10:05:34 +02:00
Ferass El Hafidi
deff94a15e arm: dts: add support for Videostrong KII Pro
Import the device tree from mainline linux (v6.4-rc1) and add the
old PHY reset bindings in the PHY node, else U-Boot and linux won't
be able to use the PHY.

Signed-off-by: Ferass El Hafidi <vitali64pmemail@protonmail.com>
Link: https://lore.kernel.org/r/20230507124109.31778-2-vitali64pmemail@protonmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-06-28 10:05:34 +02:00
Igor Prusov
1f0d2e870d board: amlogic: add support for AD401 board
The AD401 board is the Amlogic A1 SoC reference board

Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230505125639.3605-6-ivprusov@sberdevices.ru
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-06-28 10:05:34 +02:00
Igor Prusov
0e3f7e9c98 ARM: meson: add A1 support
Add support for Amlogic A1 SoC family.

Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
Signed-off-by: Evgeny Bachinin <eabachinin@sberdevices.ru>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230505125639.3605-4-ivprusov@sberdevices.ru
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-06-28 10:05:34 +02:00
Igor Prusov
aacf821bf0 ARM: dts: sync meson-a1-ad401 from Linux 6.3-rc7
Add meson-a1-ad401.dts file from Linux 6.3-rc7

Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230505125639.3605-3-ivprusov@sberdevices.ru
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-06-28 10:05:34 +02:00
Igor Prusov
8d72c796b4 ARM: dts: Add Amlogic Meson A1 DT from Linux 6.3-rc7
Import Linux 6.3-rc7 Device tree and necessary bindings for Amlogic A1
board from 6a8f57ae2eb0 ("Linux 6.3-rc7").

Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230505125639.3605-2-ivprusov@sberdevices.ru
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-06-28 10:05:34 +02:00
Marek Vasut
6039e0edc8 imx: hab: Simplify the mechanism
The current mechanism is unnecessarily complex. Simplify the whole mechanism
such that the entire fitImage is signed, IVT is placed at the end, followed
by CSF, and this entire bundle is also authenticated. This makes the signing
scripting far simpler.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-06-24 13:47:02 -04:00
Marek Vasut
6a412faea3 imx: hab: Fix a couple of build warnings with DEBUG enabled
In case the DEBUG is enabled, these three lines warn about cast of
pointer to integer of different size, add the missing casts to fix
the warnings.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-06-24 13:47:01 -04:00
Marek Vasut
68dcbdd594 ARM: imx: Add weak default reset_cpu()
Add weak default reset_cpu() implementation needed by e.g. panic().

Signed-off-by: Marek Vasut <marex@denx.de>
2023-06-24 13:46:58 -04:00
Tomasz Maciej Nowak
da880bf7c1 ARM: dts: trimslice: sync SPI node with Linux dts
After "spi: spi_flash_probe_bus_cs() rely on DT for spi speed and mode"
series flash speed and mode wasn't passed to driver anymore, which
resulted in:

Loading Environment from SPIFlash... tegra20_sflash spi@7000c380: Invalid chip select 0:0 (err=-19)
*** Warning - spi_flash_probe_bus_cs() failed, using default environment

Fix it by syncing SPI node of affected device dts with Linux kernel dts.
The changed SPI bus frequency doesn't influence stability of read/write
operations.

Ref: https://patchwork.ozlabs.org/project/uboot/cover/20220518064648.1843664-1-patrice.chotard@foss.st.com
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
2023-06-23 13:43:48 +02:00
Sam Edwards
8dc2c66680 psci: fix use of clobbered registers in asm
The functions `psci_get_context_id` and `psci_get_target_pc`
are written in C, so the C compiler may clobber registers r0-r3.
Do not use these registers to save data across calls.

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
2023-06-20 16:08:13 -04:00
Michal Simek
bb922ca3eb global: Use proper project name U-Boot (next)
Use proper project name in DTs, messages and READMEs.

Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-06-19 16:45:36 -04:00
Rui Miguel Silva
b3870dd492 corstone1000: add fwu-metadata store info
Add fwu-mdata node and handle for the reference
nvmxip-qspi.

Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
2023-06-19 14:34:16 -04:00
Dario Binacchi
13e364b3d2 ARM: dts: stm32f769-disco: remove the dsi_host node
The node has become useless, as described in the
commit 754815b854 ("video: stm32: remove the compatible "synopsys, dw-mipi-dsi" support")

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-06-16 11:24:45 +02:00
Patrick Delaunay
08002ffd08 ARM: dts: stm32mp: alignment with v6.3
Device tree alignment with Linux kernel v6.3:
- f5a058023239 - ARM: dts: stm32: add i2c nodes into stm32mp131.dtsi
- 8539ebb435a5 - ARM: dts: stm32: enable i2c1 and i2c5 on
  stm32mp135f-dk.dts
- 8539ebb435a5 - ARM: dts: stm32: add spi nodes into stm32mp131.dtsi
- 15f72e0da4da - ARM: dts: stm32: add pinctrl and disabled spi5 node in
  stm32mp135f-dk
- ea99a5a02ebc - ARM: dts: stm32: Create separate pinmux for qspi cs pin
  in stm32mp15-pinctrl.dtsi
- a306d8962a24 - ARM: dts: stm32: Rename mdio0 to mdio
- 0a5ebb1f3367 - ARM: dts: stm32: Replace SAI format with dai-format DT
  property
- ccdab19738a6 - ARM: dts: stm32: add adc support to stm32mp13
- 022932ab55fd - ARM: dts: stm32: add adc pins muxing on stm32mp135f-dk
- ab2806ddad9d - ARM: dts: stm32: add dummy vdd_adc regulator on
  stm32mp135f-dk
- e46a180c060f - ARM: dts: stm32: add adc support on stm32mp135f-dk
- 9ebf215fbae1 - ARM: dts: stm32: add PWR fixed regulators on stm32mp131
- 16f4ff60519a - ARM: dts: stm32: add USBPHYC and dual USB HS PHY support
  on stm32mp131
- 4a47f0f3e936 - ARM: dts: stm32: add UBSH EHCI and OHCI support on
  stm32mp131
- 2a46bb66c47f - ARM: dts: stm32: add USB OTG HS support on stm32mp131
- 9ebf215fbae1 - ARM: dts: stm32: add fixed regulators to support usb on
  stm32mp135f-dk
- 16f4ff60519a - ARM: dts: stm32: enable USB HS phys on stm32mp135f-dk
- c4e7254cf6dc - ARM: dts: stm32: enable USB Host EHCI on stm32mp135f-dk
- 44978e135916 - ARM: dts: stm32: add pins for stm32g0 typec controller on stm32mp13
- 4f532403b1e5 - ARM: dts: stm32: enable USB OTG in dual role mode on
  stm32mp135f-dk
- e1f15571c96c - ARM: dts: stm32: add mcp23017 pinctrl entry for stm32mp13
- 6cc71374002e - ARM: dts: stm32: add mcp23017 IO expander on I2C1 on
  stm32mp135f-dk
- 7ffd2266bd32 - ARM: dts: stm32: Fix qspi pinctrl phandle for
  stm32mp15xx-dhcor-som
- 21d83512bf2b - ARM: dts: stm32: Fix qspi pinctrl phandle for
  stm32mp15xx-dhcom-som
- 732dbcf52f74 - ARM: dts: stm32: Fix qspi pinctrl phandle for
  stm32mp151a-prtt1l
- 003b7c6b24f4 - ARM: dts: stm32: remove sai kernel clock on
  stm32mp15xx-dkx
- f2b17b39bfff - ARM: dts: stm32: rename sound card on stm32mp15xx-dkx
- dee3cb759d3d - ARM: dts: stm32: Remove the pins-are-numbered property
- ae8cf3b48727 - ARM: dts: stm32: add i2s nodes on stm32mp131
- 619746a27bd0 - ARM: dts: stm32: add sai nodes on stm32mp131
- c5e05d08ef90 - ARM: dts: stm32: add spdifrx node on stm32mp131
- 0a5afd3ee0d0 - ARM: dts: stm32: add dfsdm node on stm32mp131
- bf9d876bea2e - ARM: dts: stm32: add timers support on stm32mp131
- a3183748371d - ARM: dts: stm32: add timer pins muxing for stm32mp135f-dk
- a9060c1326bc - ARM: dts: stm32: add timers support on stm32mp135f-dk
- a12154058f75 - ARM: dts: stm32: Fix User button on stm32mp135f-dk
- 2f33df889e99 - ARM: dts: stm32: Use new media bus type macros
- 366384e49551 - ARM: dts: stm32: Update part number NVMEM description on
  stm32mp131

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-06-16 11:22:07 +02:00
Clément Léger
ee8f873678 ARM: at91: don't initialize clocks if scmi clock driver is enabled
Because clock devices are initialized by the SCMI server, if
CONFIG_CLK_SCMI is defined.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
2023-06-16 12:17:12 +03:00
Patrick Delaunay
bd087f62c9 stm32mp: stm32prog: use the decimal format by default for offset parsing
Change the default base for offset parsing with simple_strtoull(),
so offset in flashlayout is coded in base 10 by default, even if string
start with '0'. The Octal encoding is not supported. The base 16
is still supported when the '0x' header is detected.

This patch solves an unexpected parsing result when the address,
provided by decimal value is starting by 0, for example 0x4400 = 00017408
is a invalid with current code.

...
P	0x04	fsbl1	Binary	mmc0	00017408	        tf-a.stm32
....

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-06-16 11:16:31 +02:00
Patrick Delaunay
09f50c75a1 stm32mp: stm32prog: fix OTP read/write error management
Avoid to ignore the OTP read/write error and transmits the error
to STM32CubeProgrammer.

Today the error is only displayed in log error:
so the user on HOST thinks the OTP operation is performed.

Reported-by: Mickael GARDET <m.gardet@overkiz.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Fixes: 75ea9e75931c ("stm32mp: stm32prog: add TEE support in stm32prog command")
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-06-16 11:16:31 +02:00
Patrick Delaunay
7b802e1acf stm32mp: bsec: add check on null size in misc ops
Add a protection in misc bsec ops for request with null size.

For example OP-TEE error occurs when get_eth_nb() return 0 in
setup_mac_address() for unknown part number because U-Boot read 0 OTPs.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-06-16 11:16:31 +02:00
Patrick Delaunay
6bdef5b767 stm32mp: add support of STM32MP15x Rev.Y
Add support of STM32MP15x Rev.Y for the Silicon revision REV_ID = 0x2003.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-06-16 11:16:31 +02:00
Marek Vasut
9af2ec18b4 ARM: stm32: Add missing header for save_boot_params
The get_stm32mp_rom_api_table() function is defined in sys_params.h ,
add the missing header to avoid compiler warning.

Fixes: dbeaca79b7 ("ARM: stm32: Factor out save_boot_params")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-06-16 11:13:55 +02:00
Marek Vasut
715e709038 ARM: stm32: Add IWDG handling into PSCI suspend code
In case the IWDG is enabled by either U-Boot or Linux, the IWDG can never
be disabled again. That includes low power states, which means that if the
IWDG is enabled, the SoC would reset itself after a while in suspend via
the IWDG. This is not desired behavior.

It is possible to enable IWDG pre-timeout IRQ which is routed into the EXTI,
and use that IRQ to wake the CPU up before the IWDG timeout is reached and
reset is triggered. This pre-timeout IRQ can be used to reload the WDT and
then suspend the CPU again every once in a while.

Implement this functionality for both IWDG1 and IWDG2 by reading out all
the unmasked IRQs, comparing the list with currently pending IRQs in GICv3:
- If any IRQ is pending and it is NOT IWDG1 or IWDG2 pre-timeout IRQ,
  wake up and let OS handle the IRQs
- If IWDG1 or IWDG2 IRQ is pending and no other IRQ is pending,
  ping the respective IWDG and suspend again

This does not seem to have any adverse impact on power consumption in suspend.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-06-16 11:09:28 +02:00
Patrick Delaunay
dac5b06512 stm32mp: stm32prog: Add support of FWU_MDATA partition type
Add support of "FWU_MDATA" partition type in flashlayout to select
the TF-A firmware update metadata partition type guid, associated to
U-Boot "system" partition type guid, FWU_MDATA_GUID introduced by
commit 2eaedc9516 ("FWU: Add FWU metadata structure and driver for
accessing metadata") and used in gpt_get_mdata_partitions() for
commit 554b38f7a5 ("FWU: Add FWU metadata access driver for GPT
partitioned block devices")

See also recommendation in FWU-PSA-A_DEN0118_1.0ALP3.pdf
  4.1.2 Metadata integration with GPT
  When embedded in a GPT, each metadata replica occupies a single
  partition with PartitionTypeGUID = metadata_uuid.
  UUID = 8a7a84a0-8387-40f6-ab41-a8b9a5a60d23

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-06-16 11:04:41 +02:00
Patrick Delaunay
3a67b61ca0 stm32mp: stm32prog: Add support of ESP partition type
Add support of "ESP" partition type in flashlayout to select
the "EFI System Partition", associated to U-Boot "system"
partition type  guid, PARTITION_SYSTEM_GUID =
C12A7328-F81F-11d2-BA4B-00A0C93EC93B.

This partition is the bootable partition for efi boot.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-06-16 11:04:41 +02:00
Patrick Delaunay
82a4a255aa stm32mp: stm32prog: Add support of ENV partition type
Add support of "ENV" partition type in flashlayout to select
the "u-boot-env" GUID, with PARTITION_U_BOOT_ENVIRONMENT =
3de21764-95bd-54bd-a5c3-4abe786f38a8, that mean a partition
holding a U-Boot environment introduced by
commit c0364ce1c6 ("doc/README.gpt: define partition type
GUID for U-Boot environment")'

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-06-16 11:04:41 +02:00
Patrick Delaunay
90f992e6a5 arm: dts: stm32: Add partitions in flash0 and nand node for stm32mp15xx-dhcom/dhcor
Add partitions subnode in flash0 for stm32mp157xx-dhcom/dhcor boards.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-06-16 11:01:16 +02:00
Patrice Chotard
5d3abc6023 stm32mp: stm32prog: Remove tee_detected from stm32prog_data struct
As stm32prog_get_tee_partitions() is no more used, remove tee_detected
boolean from stm32prog_data struct and all code using it.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-06-16 11:01:16 +02:00
Patrice Chotard
e91d3c6176 arm: dts: stm32: Add partitions in flash0 and nand node for stm32mp15xx-ev1
Add partitions subnode in flash0 and nand nodes for all stm32mp157xx-ev1
boards. Update only the file stm32mp157c-ev1-*u-boot.dtsi, included by
other files  stm32mp15*-ev1-*-u-boot.dtsi.

For SCMI variant of device tree used with stm32mp15_defconfig
add partitions needed by TF-A firmware update:
- metadata to save the TF-A information: 2 copy
- fip-a / fip-b: two FIP slots, used for system A/B (seamless) update
- the previous "fsbl" partition with 2 copy of TFA is replaced
  by 2 partitions (only one copy in each MTD partition) to simplify
  the update: no need to managed this copy on update, need to update the
  two partition (skip bad block for NAND)
The offset for ENV partition are also updated in stm32mp15_defconfig

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-06-16 11:01:16 +02:00
Patrick Delaunay
c8532a06a6 arm: dts: stm32: Align stm32mp15xx-*-scmi-u-boot.dtsi file
Update "secure" version of STM32 boards based on SCMI when RCC_TZCR.TZEN=1
stm32mp15xx-*-scmi-u-boot.dtsi with latest patches on files
stm32mp15xx-*-u-boot.dtsi.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-06-16 11:01:16 +02:00
Patrice Chotard
a142a1dd90 stm32mp: stm32prog: Remove usage of "mtdparts" function
Motivation for this patch is to remove usage of function define
in cmd/mtdparts.c interface, based on env variables mtdids and mtdparts:
mtdparts_init() and find_dev_and_part().
See commit 938db6fe5d ("cmd: mtdparts: describe as legacy")

Now, all MTD devices are populated with their partition's information
found in DT, accessible in MTD devices. Use these information to find
the wanted partitions, no more need of find_dev_and_part() usage.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-06-16 11:01:16 +02:00
Camelia Groza
c699427e20 arm: dts: ls1046afrwy: add the FMan Ethernet nodes
Describe the FMan Ethernet interfaces present on the board.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-06-15 17:58:53 +08:00
Tom Rini
7da82de916 Xilinx changes for v2023.10-rc1
global:
 - Use proper U-Boot project name
 
 Fix sparse warnings in zynqmp-clk, zynqmp handoff, board
 
 cmd:
 - Cover incorrect 0 length entries
 
 Versal NET:
 - Add bootmode logic
 - Support SPP production version
 - Add loadpdi command
 
 ZynqMP:
 - Clear pmufw node command ID handling
 - Change power domain behavior around zynqmp_pmufw_node()
 - Fix zynqmp cmd return values and pmufw command
 - Fix R5 tcm init and modes
 
 mmc:
 - Sync Versal NET emmc DT binding
 
 pcie:
 - Add support for ZynqMP PCIe root port
 
 video:
 - Add support for ZynqMP DP
 
 tools:
 - Fix debug message in relocate-rela
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Merge tag 'xilinx-for-v2023.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2023.10-rc1

global:
- Use proper U-Boot project name

Fix sparse warnings in zynqmp-clk, zynqmp handoff, board

cmd:
- Cover incorrect 0 length entries

Versal NET:
- Add bootmode logic
- Support SPP production version
- Add loadpdi command

ZynqMP:
- Clear pmufw node command ID handling
- Change power domain behavior around zynqmp_pmufw_node()
- Fix zynqmp cmd return values and pmufw command
- Fix R5 tcm init and modes

mmc:
- Sync Versal NET emmc DT binding

pcie:
- Add support for ZynqMP PCIe root port

video:
- Add support for ZynqMP DP

tools:
- Fix debug message in relocate-rela
2023-06-12 16:42:37 -04:00
Tom Rini
260d4962e0 Merge tag v2023.07-rc4 into next
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-06-12 14:55:33 -04:00
Algapally Santosh Sagar
89240bc0c4 arm64: versal: Add missing prototypes
Add missing prototypes to fix the below sparse warnings
1. warning: no previous prototype for 'set_r5_halt_mode'
[-Wmissing-prototypes]
2. warning: no previous prototype for 'set_r5_tcm_mode'
[-Wmissing-prototypes]
3. warning: no previous prototype for 'release_r5_reset'
[-Wmissing-prototypes]
4.warning: no previous prototype for 'enable_clock_r5'
[-Wmissing-prototypes]

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230609090531.31794-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-06-12 13:25:02 +02:00
Algapally Santosh Sagar
b177bb1269 arm64: versal: Add missing prototype for initialize_tcm
Add the missing prototype pointed by below sparse warning
warning: no previous prototype for 'initialize_tcm'
[-Wmissing-prototypes]

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230609090531.31794-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-06-12 13:25:02 +02:00
Venkatesh Yadav Abbarapu
a30ac34ca8 arm64: zynqmp: Fix lockstep mode cpu release functionality
For lockstep mode, cpu_release function is expecting to execute
on R5 core 0, if there is attempt to pass other than R5 core 0,
through an error saying "Lockstep mode should run on R5 core 0 only".

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20230608032152.980-3-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-06-12 13:25:02 +02:00
Michal Simek
1be82afa80 global: Use proper project name U-Boot
Use proper project name in comments, Kconfig, readmes.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Qu Wenruo <wqu@suse.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0dbdf0432405c1c38ffca55703b6737a48219e79.1684307818.git.michal.simek@amd.com
2023-06-12 13:24:31 +02:00
Michal Simek
3e95bf9b76 arm64: versal-net: Add support for SPP production version
Production version restarting platform version field from 0 that's why add
new calculation to be able to use different DT for these platforms.
Requested DT names for production silicons for IPP/SPP and EMU platform are
versal-net-ipp-rev2.0.dts and versal-net-emu-rev2.0.dts.
If platform version increase numbers revision can be even higher.
As of today platform version is 2 that's why expected is rev2.2.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/691e166b3cf2643d7edf482bda5500163eecb35a.1684311689.git.michal.simek@amd.com
2023-06-12 13:24:31 +02:00
Algapally Santosh Sagar
b4501aa028 mach-zynqmp: handoff: Add missing header
Add missing prototype to fix the sparse warning.
warning: no previous prototype for 'bl2_plat_get_bl31_params'
[-Wmissing-prototypes]

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20230519113816.22083-3-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-06-12 13:24:31 +02:00
Ashok Reddy Soma
ded539ff66 arm64: versal-net: Detect and display bootmode
Read boodmode register using versal_net_get_bootmode() in board_late_init
and prepare corresponding distro boot command sequence based on it.

versal_net_get_bootmode() will be changed to use smc calls later, but
for now directly reads the register.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230516144753.30869-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-06-12 13:24:31 +02:00
Geert Uytterhoeven
c1466c55de ARM: dts: renesas: Add compatible properties to LAN8710A Ethernet PHYs
Add compatible values to Ethernet PHY subnodes representing SMSC
LAN8710A PHYs on RZ/A1 and R-Mobile A1 boards.  This allows software to
identify the PHY model at any time, regardless of the state of the PHY
reset line.

Ported from Linux kernel commit 1c65ef1c71e473c00f2a7a1b9c140f0b4862f282 .

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/247dc2074dae149af07b6d014985ad30eb362eda.1631174218.git.geert+renesas@glider.be
---
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Michal Simek <michal.simek@amd.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
2023-06-10 13:34:06 +02:00
Jassi Brar
f809fb660b dt: fwu: developerbox: enable fwu banks and mdata regions
Specify Bank-0/1 and fwu metadata mtd regions.

Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2023-06-09 13:52:40 -04:00
Valentine Barshak
ed2f65f010 ARM: renesas: Add R8A77980 V3HSK board and CPLD code
Add board code for the R8A77980 V3HSK board.
Add CPLD sysreset driver to the R-Car V3H SK board.
Extracted from a larger patch by Valentine Barshak.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync configs and board code with V3H Condor, squash CPLD driver in]
2023-06-08 22:26:52 +02:00
Valentine Barshak
bd13df8b5d ARM: dts: renesas: Add R8A77980 V3HSK DTs
Import R8A77980 V3HSK DTs from Linux 6.1.31,
commit d2869ace6eeb ("Linux 6.1.31").
Extracted from a larger patch by Valentine Barshak.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Sync with 6.1.31
2023-06-08 22:26:52 +02:00
Valentine Barshak
5f4e26964c ARM: renesas: Add R8A77970 V3MSK board and CPLD code
Add board code for the R8A77970 V3MSK board.
Add CPLD sysreset driver to the R-Car V3M SK board.
Extracted from a larger patch by Valentine Barshak.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync configs and board code with V3M Eagle, squash CPLD driver in]
2023-06-08 22:26:52 +02:00
Valentine Barshak
f2a21a8c24 ARM: dts: renesas: Add R8A77970 V3MSK DTs
Import R8A77970 V3MSK DTs from Linux 6.1.31,
commit d2869ace6eeb ("Linux 6.1.31").
Extracted from a larger patch by Valentine Barshak.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Sync with 6.1.31
2023-06-08 22:26:52 +02:00
Hai Pham
13c8a0717d ARM: rmobile: Identify R-Car D3 R8A77995 r1.1 SoC
Add support to identify R8A77995 r1.1 SoC.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
[Marek: Slight update to commit message, spell out the SoC model]
2023-06-08 22:22:38 +02:00
Hiroyuki Yokoyama
08260efdaf ARM: rmobile: Identify R-Car M3-W R8A7796 r1.1/1.2 SoC
r8a7796 cpu revision v1.2 has the same information as revision v1.1.
This patch fixes revision display at startup to "rev 1.1/1.2".

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
[Marek: Slight update to commit message, spell out the SoC model]
2023-06-08 22:22:38 +02:00
Masahisa Kojima
cccea18813 efi_loader: add the number of image entries in efi_capsule_update_info
The number of image array entries global variable is required
to support EFI capsule update. This information is exposed as a
num_image_type_guids variable, but this information
should be included in the efi_capsule_update_info structure.

This commit adds the num_images member in the
efi_capsule_update_info structure. All board files supporting
EFI capsule update are updated.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-06-08 09:20:36 +02:00
Sam Edwards
9bc6f1a4d0 sunxi: Fix typo in include guard
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-06-07 22:45:02 +01:00
Andre Przywara
57285737cb sunxi: dts: arm/arm64: update devicetree files from Linux-v6.4-rc2
Sync the devicetree files from the official Linux kernel tree, v6.4-rc2.
This is covering both 64-bit and 32-bit Allwinner SoCs with Arm Ltd.
cores, we skip the new RISC-V bits for now, as sunxi RISC-V support
is still work in progress.

Among smaller cosmetic changes, this adds a SATA regulator node which we
need in U-Boot to get rid of hard-coded GPIOs.
Also this updates the Allwinner F1C100s DTs, enabling USB support, and
also adds the DTs for two new boards.

As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-06-07 22:44:40 +01:00
Nishanth Menon
fb3474bef0 arm: mach-k3: am625_init: Add Erratum WA for RTC startup
In the first silicon revision of the am62x family of SoCs, the hardware
wakeup event cannot be used if software is unable to unlock the RTC
device within one second after boot. To work around this limitation
unlock RTC as soon as possible in the boot flow to maximize our chance
of linux being able to use this device.

Add the erratum i2327 workaround to initialize the RTC.

Signed-off-by: Nishanth Menon <nm@ti.com>
[bb@ti.com: rebased from 2021.01 and expanded commit and code messages]
Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-06-01 12:40:16 -04:00
Kamlesh Gurudasani
0688ff3ae2 arm: mach-k3: arm64-mmu: do not map ATF and OPTEE regions in A53 MMU
ATF and OPTEE regions may be firewalled from non-secure entities.
If we still map them for non-secure A53, speculative access may happen,
which will not cause any faults and related error response will be ignored,
but it's better to not to map those regions for non-secure A53 as there
will be no actual access at all.

Create separate table as ATF region is at different locations for am64
and am62/am62a.

Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
2023-06-01 12:40:16 -04:00
Bhavya Kapoor
414cad08cb arm: mach-k3: j7200: clk-data.c: Add main_uart1 clock data
Add main_uart1 clocks in clk-data.c for J7200. Now,
main_uart1 clocks will be set up while booting the J7200 SoC.

Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
2023-06-01 12:40:16 -04:00
Bhavya Kapoor
f8504792e8 arm: mach-k3: j7200: dev-data.c: Add main_uart1 device data
Add device data for main_uart1 in dev-data.c for J7200. Now,
main_uart1 will be powered on while booting the J7200 SoC.

Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
2023-06-01 12:40:16 -04:00
Udit Kumar
5019170970 arch: arm: mach-k3: j721e: add support for UDA FS
When selecting UDA partition for booting. MMC read
mode was selected as RAW.

Due to growing/changing size of u-boot and tispl
images.
It will be better change to FS in case of UDA FS instead of
adjusting offsets with new change.

Signed-off-by: Udit Kumar <u-kumar1@ti.com>
2023-06-01 12:32:04 -04:00
Bhavya Kapoor
c9fc704488 arm: mach-k3: j721s2: clk-data.c: Add main_uart5 clock data
Add main_uart5 clocks in clk-data.c for J721S2. Now,
main_uart5 clocks will be set up while booting the J721S2 SoC.

Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2023-06-01 12:32:03 -04:00
Bhavya Kapoor
aa77588187 arm: mach-k3: j721s2: dev-data.c: Add main_uart5 device data
Add device data for main_uart5 in dev-data.c for J721S2. Now,
main_uart5 will be powered on while booting the J721S2 SoC.

Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2023-06-01 12:32:03 -04:00
Bhavya Kapoor
09b5d4641c arm: mach-k3: j721e: clk-data.c: Add main_uart2 clock data
Add main_uart2 clocks in clk-data.c for J721E. Now,
main_uart2 clocks will be set up while booting the J721E SoC.

Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
2023-06-01 12:32:03 -04:00
Bhavya Kapoor
f59dbe14a4 arm: mach-k3: j721e: dev-data.c: Add main_uart2 device data
Add device data for main_uart2 in dev-data.c for J721E. Now,
main_uart2 will be powered on while booting the J721E SoC.

Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
2023-06-01 12:32:03 -04:00
Manorit Chawdhry
8bfce2f998 arm: mach-k3: common: reorder removal of firewalls
K3 devices have some firewalls set up by ROM that we usually remove so
that the development is easy in HS devices.

While removing the firewalls disabling a background region before
disabling the foreground regions keeps the firewall in a state where all
the transactions will be blacklisted until all the regions are disabled.
This causes a race for some other entity trying to access that memory
region before all the firewalls are disabled and causes an exception.

Since there is no guarantee on where the background regions lie based on
ROM configurations or no guarantee if the background regions will allow
all transactions across the memory spaces, iterate the loop twice removing
the foregrounds first and then backgrounds.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-06-01 12:32:03 -04:00
Manorit Chawdhry
2a7ab9982c Revert "arm: mach-k3: common: don't reconfigure background firewalls"
This reverts commit b8ebf24e7f.

This patch seems to be fundamentally wrong and requires a different way
on how the background firewalls should be configured so revert the patch

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-06-01 12:32:03 -04:00
Leo Yan
4787c764f9 arm64: Remove duplicated symbols
When build U-boot with clang with using commands:

  $ make HOSTCC=clang xenguest_arm64_defconfig
  $ make HOSTCC=clang CROSS_COMPILE=aarch64-linux-gnu- \
		CC="clang -target aarch64-linux-gnueabi" -j8

The compiler reports error:

  /tmp/start-acdf31.s:330:1: error: symbol '_start' is already defined
  _start:
  ^

Because the symbol '_start' has been defined twice, one is defined in
arch/arm/cpu/armv8/start.S, another is defined in the header
boot0-linux-kernel-header.h.

To fix building failure, this patch removes the symbol '_start' from
boot0-linux-kernel-header.h.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
2023-06-01 12:32:03 -04:00
Sam Edwards
719120392f arm: set alignment properly for asm funcs
ARM requires a 4-byte alignment on all ARM code (though this
requirement is relaxed to 2-byte for some THUMB code) and we
should be explicit about that here.

GAS has its own fix for this[1] that forces proper alignment
on any section containing assembled instructions, but this is
not universal: Clang's and other gaslike assemblers lack this
implicit alignment. Whether or not this is considered a bug in
those assemblers, it is better to ask directly for what we want.

[1]: https://sourceware.org/bugzilla/show_bug.cgi?id=12931

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
2023-05-31 17:23:01 -04:00
Jens Wiklander
c8216147a5 arm: use asm-generic/unaligned.h
Arm duplicates the content of asm-generic/unaligned.h, so use that file
directly instead.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-05-31 14:05:34 -04:00
Tom Rini
f1671205fa include: Remove unused header files
As part of various code clean-ups we have on occasion missed removing
unused header files.  None of these files are referenced anywhere else
at this point.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-05-31 12:31:47 -04:00
Andre Przywara
30cb657483 arm: uniphier: fix header inclusion guard
It seems like the header inclusion guard for some Uniphier DDR PHY
header was misspelled.

Make the preprocessor symbol for the #ifndef and #define lines the
same, so that the double inclusion protection works as expected.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-05-31 10:11:46 -04:00
Andre Przywara
4ee992f7cf imx: fix header inclusion guards
It seems like the header inclusion guards for some IMX related headers
were misspelled or got out of sync.

Make the preprocessor symbols for the #ifndef and #define lines the
same, so that the double inclusion protection works as expected.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-05-31 10:11:46 -04:00
Tom Rini
41e289bb1f arm: Remove ti816x_evm board and ti816x SoC support
This platform is currently unmaintained and untested, so remove it.
Further, as it is the only TI816X SoC example, remove related files as
well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-05-31 10:11:46 -04:00
Mark Kettenis
4a97874d35 arm: apple: Add initial Apple M2 Pro/Max support
Apple's M2 Pro/Max SoC are somewhat similar to the M1 Pro/Max but
need a tweaked memory map.  USB, NVMe, UART and WDT are working
with the existing drivers.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2023-05-30 15:13:44 -04:00
Manorit Chawdhry
bd6a247593 arm: mach-k3: security: separate out validating binary logic
K3 GP devices allows booting the secure binaries on them by bypassing
the x509 header on them.

ATF and OPTEE firewalling required the rproc_load to be called before
authentication. This change caused the failure for GP devices that
strips off the headers. The boot vector had been set before the headers
were stripped off causing the runtime stripping to fail and stripping
becoming in-effective.

Separate out the secure binary check on GP/HS devices so that the
boot_vector could be stripped before calling rproc_load. This allows
keeping the authentication later when the cluster is on along with
allowing the stripping of the binaries in case of gp devices.

Fixes: 1e00e9be62 ("arm: mach-k3: common: re-locate authentication for atf/optee")

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-30 15:13:44 -04:00
Dave Gerlach
895b8b6768 arm: mach-k3: Increase SYSFW max image size
When booting with HS silicon, the system firmware image is 278270, which
is slightly larger than currently allocated amount.

This can cause unexpected behavior if this overlap interferes with other
things in memory, so increase this with a slightly margin added as well
to avoid any boot issues that can appear after system firmware gets
loaded.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
2023-05-30 15:13:44 -04:00
Manorit Chawdhry
6cfdf8270e Kconfig: j721e: Change K3_MCU_SCRATCHPAD_BASE to non firewalled region
In non-combined boot flow for K3, all the firewalls are locked by default
until sysfw comes up. Rom configures some of the firewall for its usage
along with the SRAM for R5 but the PSRAM region is still locked.

The K3 MCU Scratchpad for j721e was set to a PSRAM region triggering the
firewall exception before sysfw came up. The exception started happening
after adding multi dtb support that accesses the scratchpad for reading
EEPROM contents.

The commit changes R5 MCU scratchpad for j721e to an SRAM region.

Old Map:
┌─────────────────────────────────────┐ 0x41c00000
│                 SPL                 │
├─────────────────────────────────────┤ 0x41c40000 (approx)
│                STACK                │
├─────────────────────────────────────┤ 0x41c85b20
│             Global data             │
│  sizeof(struct global_data) = 0xd8  │
├─────────────────────────────────────┤ gd->malloc_base = 0x41c85bfc
│                HEAP                 │
│  CONFIG_SYS_MALLOC_F_LEN = 0x70000  │
├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR
│               SPL BSS               │ (0x41cf5bfc)
│  CONFIG_SPL_BSS_MAX_SIZE = 0xA000   │
└─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
			                (0x41cffbfc)

New Map:
┌─────────────────────────────────────┐ 0x41c00000
│                 SPL                 │
├─────────────────────────────────────┤ 0x41c40000 (approx)
│                EMPTY                │
├─────────────────────────────────────┤ 0x41c81920
│                STACK                │
│ SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 │
├─────────────────────────────────────┤ 0x41c85920
│             Global data             │
│  sizeof(struct global_data) = 0xd8  │
├─────────────────────────────────────┤ gd->malloc_base = 0x41c859f0
│                HEAP                 │
│  CONFIG_SYS_MALLOC_F_LEN = 0x70000  │
├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR
│               SPL BSS               │ (0x41cf59f0)
│  CONFIG_SPL_BSS_MAX_SIZE = 0xA000   │
├─────────────────────────────────────┤ 0x41cff9fc
│         NEW MCU SCRATCHPAD          │
│  SYS_K3_MCU_SCRATCHPAD_SIZE = 0x200 │
└─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
			                (0x41cffbfc)

Fixes: ab977c8b91 ("configs: j721s2_evm_r5: Enable support for building multiple dtbs into FIT")

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
[n-francis@ti.com: SRAM allocation addressing diagram]
Signed-off-by: Neha Francis <n-francis@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
2023-05-30 15:13:43 -04:00
Andrew Davis
c0d00bd120 arm: k3: config.mk: Add missing dependencies on tispl.bin HS
When building for secure devices using non-buildman based image generation
the signed tispl.bin file is called tispl.bin_HS. Also build the unsigned
tispl.bin file as expected.

Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-30 15:13:43 -04:00
Tom Rini
6dcee70692 u-boot-imx-20230525
-------------------
 
 - i.MX93 series
 - Fixes
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16412
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Merge tag 'u-boot-imx-20230525' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20230525
-------------------

- i.MX93 series
- Fixes

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16412
2023-05-25 14:27:39 -04:00
Ye Li
dace5e9fdc imx9: Calculate DDR size from DDRC setting
To avoid using static setting for ECC enabled DDR size, switch
to calculate DDR size from DDRC setting

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:41 +02:00
Jacky Bai
8e81e679db ddr: imx93: update the ddr init to support mult setpoints
Update the DDR init flow for multi-setpoint support on i.MX93. A new
fsp_cfg struct need to be added in the timing file to store the diff
part of the DDRC and DRAM MR register for each setpoint.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:41 +02:00
Jacky Bai
37eb821e2e ddr: imx93: Add 625M bypass clock support
Add 625M bypass clock that may be used DRAM 625M
bypass mode support.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:41 +02:00
Ye Li
662f05fcb6 ddr: imx9: Add workaround for DDRPHY rank-to-rank errata
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap
specification does not include the Critical Delay Difference (CDD) to
properly define the required rank-to-rank read command spacing after
executing PHY training firmware.

Following the errata workaround, at the end of data training, we get
all CDD values through the MessageBlock, then re-configure the DDRC
timing of WWT/WRT/RRT/RWT with comparing MAX CDD values.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:41 +02:00
Peng Fan
4699ffb202 arm: dts: imx93: add tmu
Add tmu nodes and thermal zone

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:41 +02:00
Peng Fan
596b9c4e1b arm: dts: imx93: sync device tree with Linux
Sync device tree with next-20230426

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:41 +02:00
Ye Li
a702ae7a01 imx9: allow to bootaux Mcore with input address
Currently bootaux only supports to boot M33 core from TCM. Since ATF
has changed to use x2 parameter for M33 image address, update the
bootaux command to use input address, so we can support boot from
any possilbe address like TCM, DDR, Flexspi NOR.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:41 +02:00
Peng Fan
8e9c0a14f9 imx9: use i.MX generic rom api function
There is no need to save gd with using the generic rom api function, so
simplify code.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:41 +02:00
Peng Fan
57bf3c40fe imx9: correct coding style
The end brace should be in a new line

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:41 +02:00
Peng Fan
58da865e27 imx9: add i.MX93 variants support
According to datasheet, iMX93 has fused parts with CORE1 or NPU or
both disabled. So update code to support it, the kernel device tree
runtime update will be added in future patches.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:41 +02:00
Peng Fan
4a5c5d56f5 imx9: clock: config arm alt root to 500mhz
Config the A55 alt root clock to 500MHz(LD mode frequency)
by default. Normally, this clock root is only used as an
intermediate clock soure for A55 core/dsu when change the
ARM PLL frequency.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:41 +02:00
Peng Fan
3c5dcec791 imx9: clock: add CONFIG_IMX9_LOW_DRIVE_MODE support
Add CONFIG_IMX9_LOW_DRIVE_MODE in imx9 clk, later we will
add board support

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:40 +02:00
Peng Fan
59ecc85bcc imx9: clock: clear HW_CTRL_SEL
The HW_CTRL_SEL should be cleared when configuring PLL to avoid
potential glitch

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:40 +02:00
Peng Fan
0079893920 imx9: Get market segment and speed grading
Get the chip's market segment and speed grading from fuse and print
them in boot log as other i.MX series.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:40 +02:00
Peng Fan
5f2ecac548 imx9: soc: support reset cause
Support print reset cause. Since SRSR is not accessible from non-secure
world, so first save it to grp0, then read it in non-secure world.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:40 +02:00
Ye Li
d0724433b5 imx9: Change hard coded MAC to read from fuse
The MAC addresses are hard coded for bring up. Change it to support
reading from fuse.

Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:40 +02:00
Peng Fan
3db03cbd4c imx9: cut off OPTEE memory region from U-Boot
OPTEE memory region is set secure access only in ATF with configuration
to TRDC, and need to remove it from U-Boot, otherwise U-Boot and Kernel
may crash when accessing the memory

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:40 +02:00
Peng Fan
5d09fcf24d imx9: simplify clk settings
Simplify the clk root settings with an array

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:40 +02:00
Peng Fan
532e73fdda imx9: correct getting LPI2C clk
LPI2C_CLK_ROOT should be used instead of LPUART_CLK_ROOT for i2c

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:40 +02:00
Peng Fan
5f2953eb6b imx9: use parameter freq when set_arm_clk
The freq parameter was ignored, should use it when configuring ARM PLL

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:40 +02:00
Peng Fan
a6b36e9970 imx9: add more PLL settings
Add more PLL settings for A55 and Display

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:40 +02:00
Peng Fan
69326a7f20 imx9: configure M33 systick to 24M
The M33 systick should be 24M per reference mannual, so correct it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 16:54:40 +02:00
Peng Fan
99ac6c769f imx: move imx8 sci header file to include/firmware/imx
Move imx8 sci header file to include/firmware/imx, then we could
use build macro to reuse some i.MX8 drivers for i.MX9, such as
drivers/cpu/imx8_cpu.c.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
2023-05-21 16:54:32 +02:00
Peng Fan
be0ad00409 imx: spl_imx_romapi: typo fix
Unknow->Unknown

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 13:48:52 +02:00
Peng Fan
6490c1271a imx8ulp: build ahab
The ahab was missed to be compiled, so add it back.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 13:48:52 +02:00
Fabio Estevam
0aea5dda29 ARM: dts: imx7d-sdb-u-boot: Fix usdhc1 UHS operation
Commit 1a7904fdfa ("mmc: fsl_esdhc_imx: Use esdhc_soc_data
flags to set host caps") exposed the following SD card error:

U-Boot 2023.04-00652-g487e42f7bc5e (Apr 05 2023 - 22:14:21 -0300)

CPU:   Freescale i.MX7D rev1.0 1000 MHz (running at 792 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 35C
Reset cause: POR
Model: Freescale i.MX7 SabreSD Board
Board: i.MX7D SABRESD in non-secure mode
DRAM:  1 GiB
Core:  100 devices, 19 uclasses, devicetree: separate
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... Card did not respond to voltage
select! : -110
*** Warning - No block device, using default environment

The reason of the problem, as explained by Ye Li:

"When UHS is enabled in defconfig, the usdhc1 node in imx7d-sdb.dts does
not configure pad for VSELECT, also the data pad should be set to
100Mhz/200Mhz pin states."

Apply these changes into u-boot.dtsi for now. When these changes
reach the Linux mainline imx7d-sdb, they can be dropped from u-boot.dtsi.

This fixes UHS mode on the imx7d-sdb board.

Suggested-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 13:48:52 +02:00
Marek Vasut
eb1e370a9b thermal: imx_tmu: Move architecture code into driver
Stop polluting the architecture directory with driver specific code,
move it into driver where it should be. Split the code slightly so
the MX8MM/MX8MN fuse readout and programming and MX8MP fuse readout
and programming are in their separate functions, and called in case
of matching SoC.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-05-21 13:48:52 +02:00
Fedor Ross
b1d20ae5a6 ARM: imx: Fix parsing of ROM log event IDs on iMX8M
It seems like the ROM log events for the iMX8M are not fully covered by
AN12853 i.MX ROMs Log Events, Rev. 0, May 2020. On iMX8M the ROM event
ID 0x82 seems to use parameter0 which stops the parsing because the end
of list is detected too early.

This patch adds ROM event ID 0x82 and skips the next word if ID 0x82 is
parsed.

Fixes: a5ee05cf71 ("ARM: imx: Pick correct eMMC boot partition from ROM log")

Signed-off-by: Fedor Ross <fedor.ross@ifm.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-05-21 13:48:52 +02:00
Jonas Karlman
fd6e425be2 rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash
Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 5 Model B.

Similar to RK3568 the BootRom in RK3588 can read all data and look for
idbloader at 0x8000, same as on SD and eMMC.

Use the rksd format and modify the mkimage offset to generate a bootable
u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The
FIT image is loaded from 0x60000.

  => sf probe
  SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB

  => load mmc 1:1 10000000 u-boot-rockchip-spi.bin
  1492992 bytes read in 129 ms (11 MiB/s)

  => sf update $fileaddr 0 $filesize
  device 0 offset 0x0, size 0x16c800
  1300480 bytes written, 192512 bytes skipped in 11.103s, speed 137694 B/s

The BROM_BOOTSOURCE_ID value read back when booting from SPI flash does
not match the expected value of 3 (SPINOR) used by other SoCs. Instead a
value of 6 is read back, add a new enum value to handle this new
bootsource id.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-19 08:50:44 +08:00
Jonas Karlman
61ff869fd2 rockchip: rk3588-rock-5b: Add bootph prop to pinctrl for uart2 and sdhci
Enable pinctrl for sdhci in SPL to support loading of FIT image from SD
and eMMC storage when booting from SPI NOR flash.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:05 +08:00
Jonas Karlman
153c87be48 rockchip: rk3588: Select DM_RESET and DM_REGULATOR_FIXED in arch Kconfig
Like other Rockchip SoCs, DM_RESET and DM_REGULATOR_FIXED is useful
across RK3588 platform. Select them from arch Kconfig.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:05 +08:00
Jonas Karlman
64f79f88a7 rockchip: rk3568-rock-3a: Enable boot from SPI NOR flash
Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 3 Model A.

Unlike prior generation SoCs the BootRom in RK3568 can read all data and
look for idbloader at 0x8000, same as on SD and eMMC.

Use the rksd format and modify the mkimage offset to generate a bootable
u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The
FIT image is loaded from 0x60000.

  => sf probe
  SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB

  => load mmc 1:1 10000000 u-boot-rockchip-spi.bin
  1384448 bytes read in 119 ms (11.1 MiB/s)

  => sf update $fileaddr 0 $filesize
  device 0 offset 0x0, size 0x152000
  1179648 bytes written, 204800 bytes skipped in 9.901s, speed 143185 B/s

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:05 +08:00
Jonas Karlman
674803fe86 rockchip: rk3568-rock-3a: Use pinctrl for sdmmc and sdhci in SPL
Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT
image from SD and eMMC storage when booting from SPI NOR flash.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Jonas Karlman
41cb87be06 rockchip: rk3566-radxa-cm3-io: Use pinctrl for sdmmc and sdhci in SPL
Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT
image from SD and eMMC storage when booting from SPI NOR flash.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Jonas Karlman
1bf49d5a4a rockchip: rk3566-radxa-cm3-io: Update defconfig
Update defconfig for rk3566-radxa-cm3-io with new defaults. Also add
missing supported mmc modes to sdhci node.

Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.

Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
to 0x40000, use the space in between as SPL_MAX_SIZE.

Add config option to include useful gpio cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.

Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
U-Boot proper will read and configure assigned-clock props.

Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Jonas Karlman
dc27b4a1af rockchip: rk356x-u-boot: Add xin24m clock node to SPL
Add bootph-all prop to xin24m clock node, it is referenced by cru node.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Christopher Obbard
bfbef68ae1 ARM: dts: rockchip: rock5b: enable pcie2x1l2 and associated combphy
Enable the PCIe 2x1l 2 device and associated combphy.
On this bus, the Rock5B has an Ethernet transceiver connected.

Signed-off-by: Christopher Obbard <chris.obbard@collabora.com>
[eugen.hristev@collabora.com: minor tweaks]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
[jonas@kwiboo.se: add PCIe pins]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Joseph Chen
ec8242cceb ARM: dts: rockchip: rk3588s-u-boot: add pcie2x1l2 with PHY
Add the node for PCIe 2x1l 2 device together with the corresponding
combphy.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
[eugen.hristev@collabora.com: moved to -u-boot.dtsi, minor
adaptations]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
[jonas@kwiboo.se: adapt to kernel node]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Jonas Karlman
6e2b8344d6 rockchip: rock-pi-4: Use SDMA to boost eMMC performance
Enable the use of SDMA mode to boost eMMC performance on ROCK Pi 4.
Also add missing flags to indicate the supported MMC modes.

Using mmc read command to read 32 MiB data shows following improvement:

  => time mmc read 10000000 2000 10000

Before: time: 3.178 seconds
After: time: 0.402 seconds

This also enables CONFIG_SPL_FIT_SIGNATURE option to help discover
any possible future issue with loading TF-A into DRAM/SRAM.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:44:04 +08:00
Jonas Karlman
cf777572ca rockchip: rockpro64: Use SDMA to boost eMMC performance
Enable the use of SDMA mode to boost eMMC performance on RockPro64.
Also add missing flags to indicate the supported MMC modes.

Using mmc read command to read 32 MiB data shows following improvement:

  => time mmc read 10000000 2000 10000

Before: time: 3.178 seconds
After: time: 0.402 seconds

This also enables CONFIG_SPL_FIT_SIGNATURE option to help discover
any possible future issue with loading TF-A into DRAM/SRAM.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-18 08:34:45 +08:00
Jonas Karlman
3b804b370d mmc: rockchip_sdhci: Disable DMA mode using a device tree property
Loading part of TF-A into SRAM from eMMC using DMA fails on RK3399
similar to other Rockchip SoCs. Checksum validation fails with:

  ## Checking hash(es) for Image atf-2 ... sha256 error!
  Bad hash value for 'hash' hash node in 'atf-2' image node
  spl_load_simple_fit: can't load image loadables index 1 (ret = -1)
  mmc_load_image_raw_sector: mmc block read error
  SPL: failed to boot from all boot devices
  ### ERROR ### Please RESET the board ###

Add a device tree property, u-boot,spl-fifo-mode, to control when the
rockchip_sdhci driver should disable the use of DMA and fallback on PIO
mode. Same device tree property is used by the rockchip_dw_mmc driver.

In commit 2cc6cde647 ("mmc: rockchip_sdhci: Limit number of blocks
read in a single command") the DMA mode was disabled using a CONFIG
option on RK3588. Revert that and instead disable DMA using the device
tree property for all RK3588 boards, also apply similar workaround for
all RK3399 boards.

Fixes: 2cc6cde647 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Quentin Schulz <foss+uboot@0leil.net> # RK3399 Puma, RK3588 Tiger
2023-05-18 08:34:45 +08:00
Eugen Hristev
bb52f1c604 reset: rockchip: implement rk3588 lookup table
The current DT bindings for the rk3588 clock use a different ID than the
one that is supposed to be written to the hardware registers.
Thus, we cannot use directly the id provided in the phandle, but rather
use a lookup table to correctly setup the hardware.

This approach has been implemented already in Linux, by commit :
f1c506d152ff ("clk: rockchip: add clock controller for the RK3588")

Hence, implement a similar approach using the lookup table, and adapt
the existing reset driver to work with SoCs using lookup table.
The file rst-rk3588.c has been copied as much as possible from Linux.

Adapt the clk rk3588 driver as well to bind the reset driver with the
lookup table.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17 17:36:18 +08:00
Eugen Hristev
cec4f82f11 ARM: dts: rk3588-rock-5b-u-boot: add bootph-all to pinctrl for sdmmc
To be able to initialize the pinctrl correctly at SPL level and read
u-boot proper from SD-Card, the pinctrl must be initialized.

Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17 17:36:18 +08:00
Eugen Hristev
9ceef3d9a7 ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB 2.0 host
Add USB 2.0 host nodes and PHYs.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Co-developed-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-17 09:53:32 +08:00
Tom Rini
c21fc9e152 Xilinx changes for v2023.07-rc3
.mailmap
 - Fix Xilinx IDs
 
 ZynqMP:
 - Fix R5 split boot mode
 - DT fixes - sync with Linux
 
 Xilinx:
 - Enable virtio and RNG support
 - Enable ADI ethernet phy
 
 SPI/Zynq:
 - Fix dummy byte calculation
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Merge tag 'xilinx-for-v2023.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2023.07-rc3

.mailmap
- Fix Xilinx IDs

ZynqMP:
- Fix R5 split boot mode
- DT fixes - sync with Linux

Xilinx:
- Enable virtio and RNG support
- Enable ADI ethernet phy

SPI/Zynq:
- Fix dummy byte calculation
2023-05-16 09:10:57 -04:00
Michal Simek
b250bd6139 arm64: zynqmp: Fix User MTD partition size
The commit c8630167e0 ("arm64: zynqmp: Add mtd partition for secure OS
storage area") didn't update User partition size that's why size was beyond
actual device size.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0a56405553b87a75e066cd71697cafe7c1c97eef.1681309812.git.michal.simek@amd.com
2023-05-15 09:33:57 +02:00
Ashok Reddy Soma
66e8b8128b arm64: zynqmp: Fix issue of apps executing from R5 core 1
In current implementation, applications can execute only on R5 core 0.
The boot address for R5 core 1 is not supplied. Pass TCM address for
R5 core 1 based on the argument to fix the issue.

Remove incomplete comment.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/da865717d26648ab7a84345ca8749712efdddee5.1680699999.git.michal.simek@amd.com
2023-05-15 09:33:57 +02:00
Michal Simek
9b4d52b2e1 ARM: zynq: Sync Microzed board with Linux kernel
Fix model name, node locations and also add pinctrl description for usb.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3295fde73db13a712b65f4967eb5f39ced895ad4.1679988091.git.michal.simek@amd.com
2023-05-15 09:33:57 +02:00
Michal Simek
0da6d5a9e2 ARM: zynq: Switch from earlyprintk to earlycon
Switch to earlycon which is preffered over earlyprintk.
It is also sync with Linux kernel (zynq-microzed).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d280fa18068f80412cf12c235c5245651e7062e2.1679987839.git.michal.simek@amd.com
2023-05-15 09:33:57 +02:00
Neal Frager
d58acf644f arch: arm: zynqmp: mp.c: tcminit halt both cores in split mode
The "zynqmp tcminit split" command should halt both cores and not just RPU1
when configuring the TCM memory for split mode.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Link: https://lore.kernel.org/r/20230323082506.31576-1-neal.frager@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-05-15 09:32:49 +02:00
Ralph Siemsen
e87c869db3 board: schneider: add RZN1 board support
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.

The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13 04:01:30 +02:00
Ralph Siemsen
2156327846 ARM: rmobile: Add support for Renesas RZ/N1 SoC
The RZ/N1 is a family of SoC devices from Renesas, featuring:

* ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3
* Integrated SRAM up to 6MB
* Integrated gigabit ethernet switch
* Optional DDR2/3 controller
* I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD

Add basic support for this family, modeled on the existing RZA1.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13 04:01:30 +02:00
Ralph Siemsen
4647a84b6c ARM: dts: add devicetree for Renesas RZ/N1 SoC
This is taken directly from Linux kernel 6.3
(commit 457391b0380335d5e9a5babdec90ac53928b23b4)

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13 04:01:30 +02:00
Ralph Siemsen
54232a7057 ARM: armv7: add non-SPL enable for Cortex SMPEN
Commit 2564fce7ee ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13 04:01:30 +02:00
Simon Glass
55171aedda dm: Emit the arch_cpu_init_dm() even only before relocation
The original function was only called once, before relocation. The new
one is called again after relocation. This was not the intent of the
original call. Fix this by renaming and updating the calling logic.

With this, chromebook_link64 makes it through SPL.

Fixes: 7fe32b3442 ("event: Convert arch_cpu_init_dm() to use events")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11 10:25:29 +08:00
Troy Kisky
d975da6363 arm: mach-imx: use CONFIG_$(SPL_)SATA instead of CONFIG_SATA
This avoid an error with enable_sata_clock when
defined(CONFIG_SATA) is changed to CONFIG_IS_ENABLED(SATA).

Signed-off-by: Troy Kisky <troykiskyboundary@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-10 16:45:42 -04:00
John Keeping
35c275065c rockchip: handle peripheral as well as otg dr_mode
The OTG port is identified by inspecting the "dr_mode" property which is
expected to be "otg" for this port.  But it will work just as well as a
device controller when dr_mode is set to "peripheral", which may be
required if the mode detection pin is not set up correctly and the
device controller needs to be programmed to override this.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 22:50:01 +08:00
John Keeping
51c54080ff rockchip: use standard dr_mode parsing function
Instead of duplicating the string values here, use usb_get_dr_mode() to
handle the property lookup and converting the values to an enum.

This is implemented with a switch in preparation for the next patch
which adds extra handling for peripheral mode.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 22:50:01 +08:00
FUKAUMI Naoki
afb4f55565 arm: dts: rockchip: rock-3a: drop u-boot,spl-boot-order
use common one defined in rk356x-u-boot.dtsi.

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 22:50:01 +08:00
FUKAUMI Naoki
74f162a1ea arm: dts: rk356x: Makefile: sort
sort alphanumerically.

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 22:50:01 +08:00
FUKAUMI Naoki
71a95e2efd arm: dts: rockchip: add Radxa ROCK 4C+
Linux commit 246450344dad arm64: dts: rockchip: rk3399: Radxa ROCK 4C+

Add support for Radxa ROCK 4C+ SBC.

Key differences of 4C+ compared to previous ROCK Pi 4.
- Rockchip RK3399-T SoC
- DP from 4C replaced with micro HDMI 2K@60fps
- 4-lane MIPI DSI with 1920*1080
- RK817 Audio codec

Also, an official naming convention from Radxa mention to remove
Pi from board name, so this 4C+ is named as Radxa ROCK 4C+ not
Radxa ROCK Pi 4C+.

Signed-off-by: Stephen Chen <stephen@radxa.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 22:50:01 +08:00
FUKAUMI Naoki
d0e62eeda8 arm: dts: rockchip: rock-pi-4: sync with Linux 6.3
sync dts{,i} files for Radxa ROCK Pi 4 series with Linux 6.3.

because rk3399-rock-pi-4a.dts is enough for ROCK Pi 4A/B/A+/B+ and ROCK
4SE, delete dts{,i} for ROCK Pi 4B.

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 20:30:12 +08:00
Tianling Shen
7000a60947 rockchip: rk3328: Add support for FriendlyARM NanoPi R2C
The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC
chip changed from rtl8211e to yt8521s, and otherwise identical to R2S.

The device tree is taken from the kernel linux-next branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=004589ff9df5b75672a78b6c3c4cba93202b14c9

Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09 18:58:25 +08:00
Chris Morgan
6cf6fe2537 board: rockchip: add Anbernic RGXX3 Series Devices
The Anbernic RGxx3 is a "pseudo-device" that encompasses the following
devices:

 - Anbernic RG353M
 - Anbernic RG353P
 - Anbernic RG353V
 - Anbernic RG353VS
 - Anbernic RG503

The rk3566-anbernic-rgxx3.dtsi is synced with upstream Linux, but
rk3566-anbernic-rgxx3.dts is a U-Boot specific devicetree that
is used for all RGxx3 devices.

Via the board.c file, the bootloader automatically sets the correct
fdtfile, board, and board_name environment variables so that the
correct devicetree can be passed to Linux. It is also possible to
simply hard-code a single devicetree in the boot.scr file and use
that to load Linux as well.

The common specifications for each device are:

 - Rockchip RK3566 SoC
 - 2 external SDMMC slots
 - 1 USB-C host port, 1 USB-C peripheral port
 - 1 mini-HDMI output
 - MIPI-DSI based display panel
 - ADC controlled joysticks with a GPIO mux
 - GPIO buttons
 - A PWM controlled vibrator
 - An ADC controlled button

All of the common features are defined in the devicetree synced from
upstream Linux.

TODO: DSI panel auto-detection for the RG353 devices (requires porting
of DSI controller driver and DSI-DPHY driver to send DSI commands to
the panel).

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-06 17:45:05 +08:00
Johan Jonker
55cd74d691 arm: stm32mp: spl: fix function with fdt_addr_t input
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so fix ofnode_get_addr_size function with fdt_addr_t input to
be able to handle both sizes for stm32mp SoC in spl.c file.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
84404d8165 drivers: fix debug string with fdt_addr_t input
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so fix some
debug strings with fdt_addr_t to be able to handle both sizes.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
a12a73b664 drivers: use dev_read_addr_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Johan Jonker
66a1d38c98 rockchip: rk3288: syscon_rk3288: store syscon platdata in regmap
The Rockchip SoC rk3288 has 2 types of device trees floating around.
A 64bit reg size when synced from Linux and a 32bit for U-boot.
A pre-probe function in the syscon class driver assumes only 32bit.
For other odd reg structures the regmap must be defined in the individual
syscon driver. Store rk3288 platdata in a regmap before pre-probe
during bind.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2023-05-06 17:28:18 +08:00
Tom Rini
eb59ece520 Merge tag 'fsl-qoirq-2023-5-5' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
fsl-ls1088a device tree update
enable DM_SERIAL for ten64
check for crypto node first in fdt_fixup_remove_jr
2023-05-05 09:33:29 -04:00
Mathew McBride
fb9df2c7c5 arm: dts: ten64: fix header typo and update copyright
Somehow, I managed to typo our company name in the U-Boot
and Linux kernel submissions.

Fix this and update the copyright year at the same time.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:04 +08:00
Mathew McBride
7219c22e7f arm: dts: ten64: syncronise device tree with Linux
This synchronises the Linux device tree with U-Boot
(cp linux/..../fsl-ls1088a-ten64.dts uboot/..../fsl-ls1088a-ten64.dts),
as of Linux v6.2-rc5.

Missing from the U-Boot copy previously was the
Ethernet PCS definitions (required for linking with PHY in
Linux but not used by U-Boot) and various upstream
fixes and formatting changes.

The board microcontroller (which doesn't have a Linux driver)
has been moved to the -u-boot.dtsi, as well as the
spi0 quadspi alias (used by U-boot 'sf' but not valid for Linux).

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:04 +08:00
Mathew McBride
51b9254e02 arm: dts: fsl-ls1088a: copy all missing bindings from Linux
This is effectively:

cp linux/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi \
   u-boot/arch/arm/dts/fsl-ls1088a.dtsi

Tested working with Ten64 board (LS1088A) booting openSUSE Tumbleweed.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:04 +08:00
Mathew McBride
fd4f7b0158 arm: dts: fsl-ls1088a: move and sync existing bindings to be under /soc
Our [U-Boot] copy of fsl-ls1088a.dtsi had all the hardware under
the top level, until the DM_SERIAL implementation recently.

In this commit, remove any remaining devices (that were in U-Boot,
but not touched by previous patches in this series) to be under /soc,
updating to their upstream (Linux) bindings.

The bindings have been copied closest to their relative positions
in the Linux version, so the eventual result is that the U-Boot
and Linux fsl-ls1088a.dtsi will be identical.

The next commit will add the hardware bindings that were not
in U-Boot.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:04 +08:00
Mathew McBride
1574500139 arm: dts: fsl-ls1088a: syncronise fsl-mc definition with Linux
This moves the fsl-mc device tree definition under the /soc
node, as well as adding interrupt and IOMMU definitions that
were not in U-Boot before.

There are slight differences between the two bindings
as we add a "simple-mfd" compatible to function
under U-Boot's driver model.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:04 +08:00
Mathew McBride
ad558eff32 arm: dts: fsl-ls1088a: syncronise MDIO+PCS U-Boot definitions with Linux
Synchronise the MDIO controller definitions with Linux, so
the controllers will be usable when passing U-Boot's
control FDT to Linux.

This also adds the PCS (internal controller) definitions
which are not used by U-Boot.

Caveat: The kernel definition uses "fsl,fman-memac-mdio",
as with other members of the Layerscape family, but
U-Boot uses a different driver for the DPAA2
Family devices (LS1088/LS2088/LX2160). So
we use "fsl,ls-mdio" as the first compatible string
for these devices.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:04 +08:00
Mathew McBride
10ff7e6b04 arm: dts: fsl-ls1088a: sync usb controller nodes with Linux
Synchronise the USB device tree definition with Linux, allowing
the U-Boot control FDT to be used to boot a Linux system with
working USB.

An extra compatible string, "fsl,layerscape-dwc3" is needed
for special handling in U-Boot, so has been added to the
-u-boot.dtsi file. It might be better to add this to the
Linux source bindings.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:04 +08:00
Mathew McBride
38976a0666 arm: dts: fsl-ls1088a: move I2C nodes under "soc" and syncronize with Linux
U-Boot's definition for the I2C controllers did not contain any
clock information. This resulted in the I2C not functioning when
the U-Boot control FDT was passed to Linux.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:03 +08:00
Mathew McBride
e8ab9840b5 arm: dts: fsl-ls1088a: move GPIO controller under "soc" per Linux
Move the GPIO controller definitions under the "soc" and in
the same relative position as the Linux kernel fsl-ls1088a.dtsi.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:03 +08:00
Mathew McBride
2d6fce16c6 arm: dts: fsl-ls1088a: import CPU definition from Linux kernel
This is required for Linux to boot using the same FDT as
U-Boot (such as passing the control FDT to bootefi).

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:03 +08:00
Mathew McBride
843f60b4e8 arm: dts: fsl-ls1088a: match Linux FDT by disabling PCIe by default
The Linux kernel fsl-ls1088a.dtsi disables (status="disabled")
all PCIe controllers by default, with the bootloader (i.e U-Boot)
enabling the appropriate controllers (specified by the board
reset control word/RCW) by FDT fixup.

However, U-Boot needs these controllers to be enabled
to be usable, which we can add in the u-boot only dtsi.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:03 +08:00
Mathew McBride
f365e3cc91 arm: dts: fsl-ls1088a: sync PCIe controller definition with Linux
This moves the PCIe controller definitions under /soc and adopts
the same bindings (fsl,ls1088a-pcie) as Linux. Previously,
the format was different between the two versions.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:03 +08:00
Mathew McBride
c2509a36d3 arm: dts: fsl-ls1088a: import and sync full SMMU nodes with Linux
To synchronise the device tree in U-Boot with Linux, the GIC
(Interrupt Controller) and SMMU/IOMMU nodes need to be synchronised
before changing any dependent components like PCIe and DPAA2/fsl-mc.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:03 +08:00
Mathew McBride
d8a8b63397 arm: dts: fsl-ls1088a: move memory node into U-Boot specific file
The top-level "memory" node does not exist in the Linux
version of the fsl-ls1088a.dtsi file. Move it to the U-Boot
"tweak" file, so we can have an identical copy of
fsl-ls1088a.dtsi between the projects in the end.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:03 +08:00
Mathew McBride
2591487865 arm: dts: fsl-ls1088a: move u-boot bootph tags into u-boot only files
This moves the bootph-all tags that were added in commit a593c1fec5
("arch: arm: dts: fsl-ls1088a.dtsi: tag serial nodes with bootph-all")
into a u-boot only include.

Due to the way the U-Boot device tree "tweak" system is setup[1],
we need to have a per-board <boardname>-u-boot.dtsi, which will
include the "fsl-ls1088a-u-boot.dtsi" tweaks.

By doing so, future updates to fsl-ls1088a.dtsi from upstream
(Linux kernel) can just be copied directly into the U-Boot tree,
without worrying about any extra data local to U-Boot.

Signed-off-by: Mathew McBride <matt@traverse.com.au>

[1] - https://u-boot.readthedocs.io/en/latest/develop/devicetree/control.html#adding-tweaks-for-u-boot
The CONFIG_SYS_SOC, CONFIG_SYS_CPU and CONFIG_SYS_VENDOR
values are the same for the entire Layerscape family,
meaning there is no ability to create a LS1088A only
file here. But we will be adding per-board tweaks
later in any case.
Reviewed-by: Peng Fan <peng.fan@nxp.com>

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:03 +08:00
Mathew McBride
8586a93868 armv8: fsl-layerscape: check for crypto node first in fdt_fixup_remove_jr
This a problem I found while updating the U-Boot fsl-ls1088a.dtsi
to match the Linux version.

fdt_fixup_remove_jr did not check whether there was a "crypto"
alias in the device tree before calling more fdt_* functions,
which resulted in a crash.

Fixes: a797f274
("ARMv8/sec_firmware : Update chosen/kaslr-seed with random number")

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-05 09:46:03 +08:00
Neha Malcom Francis
1e666512fb arm: dts: k3-j7200: ddr: Update to 0.6 version of DDR config tool
Update the DDR settings to those generated using 0.6 version of
Jacinto 7 DDRSS Register Configuration tool.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2023-05-04 19:51:59 -04:00
Neha Malcom Francis
b99d710fe0 arm: dts: k3-j721e: ddr: Update to 0.9.1 version of DDR config tool
Update the DDR settings to those generated using 0.9.1 version of
Jacinto 7 DDRSS Register Configuration tool.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2023-05-04 19:51:59 -04:00
Manorit Chawdhry
30a7ee87fd Kconfig: j721s2: Change K3_MCU_SCRATCHPAD_BASE to non firewalled region
On K3 HS-SE devices all the firewalls are locked by default
until sysfw comes up. Rom configures some of the firewall for its usage
along with the SRAM for R5 but the PSRAM region is still locked.

The K3 MCU Scratchpad for j721s2 was set to a PSRAM region triggering the
firewall exception before sysfw came up. The exception started happening
after adding multi dtb support that accesses the scratchpad for reading
EEPROM contents.

Old map:
┌─────────────────────────────────────┐ 0x41c00000
│                 SPL                 │
├─────────────────────────────────────┤ 0x41c61f20 (approx)
│                STACK                │
├─────────────────────────────────────┤ 0x41c65f20
│             Global data             │
│  sizeof(struct global_data) = 0xd8  │
├─────────────────────────────────────┤ gd->malloc_base = 0x41c66000
│                HEAP                 │
│  CONFIG_SYS_MALLOC_F_LEN = 0x10000  │
├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR
│               SPL BSS               │ (0x41c76000)
│  CONFIG_SPL_BSS_MAX_SIZE = 0xA000   │
├─────────────────────────────────────┤ (0x41c80000)
│               DM DATA               │
├─────────────────────────────────────┤ (0x41c84130) (approx)
│                EMPTY                │
└─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
				        (0x41cffbfc)

New map:
┌─────────────────────────────────────┐ 0x41c00000
│                 SPL                 │
├─────────────────────────────────────┤ 0x41c61f20 (approx)
│                STACK                │
├─────────────────────────────────────┤ 0x41c65f20
│             Global data             │
│  sizeof(struct global_data) = 0xd8  │
├─────────────────────────────────────┤ gd->malloc_base = 0x41c66000
│                HEAP                 │
│  CONFIG_SYS_MALLOC_F_LEN = 0x10000  │
├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR
│               SPL BSS               │ (0x41c76000)
│  CONFIG_SPL_BSS_MAX_SIZE = 0xA000   │
├─────────────────────────────────────┤ (0x41c80000)
│               DM DATA               │
├─────────────────────────────────────┤ (0x41c84130) (approx)
│                EMPTY                │
├─────────────────────────────────────┤ SYS_K3_MCU_SCRATCHPAD_BASE
│              SCRATCHPAD             │ (0x41cff9fc)
│ SYS_K3_MCU_SCRATCHPAD_SIZE = 0x200  │
└─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
				        (0x41cffbfc)

Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-04 13:06:22 -04:00
Jan Kiszka
fca76cda28 arm: dts: iot2050: Include u-boot specific bits implicitly
Create *-u-boot.dtsi files for each target dtb of the IOT2050 series so
that we can drop the #include deviations from upstream dts[i] files
here.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2023-05-04 13:03:54 -04:00
Tom Rini
2440719d25 u-boot-imx-20230503
-------------------
 
 - Fixes for : pico-imx6ul, smegw01
 - new boards: DMSSE20, Reform 2
 - fix: get_boot_device, PLL video rate
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16211
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Merge tag 'u-boot-imx-20230503' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20230503
-------------------

- Fixes for : pico-imx6ul, smegw01
- new boards: DMSSE20, Reform 2
- fix: get_boot_device, PLL video rate

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16211
2023-05-03 13:15:12 -04:00
Dzmitry Sankouski
a2612d7c55 starqltechn: use button keyboard driver
Button keyboard driver used to navigate bootmenu entries.

Add gpio buttons, button keyboard driver.
Add gpio keys dts bindings.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-03 09:05:24 -04:00
Yang Xiwen
33f19038cc arm: histb: hi3798mv200: add initial support for Hi3798MV200 HC2910-2AGHD05 board
A board with Hi3798MV200 SoC and various peripherals. Details are in the
board README.md.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
2023-05-03 09:05:24 -04:00
Yang Xiwen
e90711f0e9 arm: add support for Hisilicon HiSTB family SoCs
First supported chip is hi3798mv200 (which is similar to Hi3798cv200
used by poplar).

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
2023-05-03 09:05:24 -04:00
Tom Rini
7a3ee61f55 arm: Remove omap5_uevm board
This platform is unsupported by TI and was never widely distributed.  As
this is untested for a long while and missing some DM conversions,
remove it and related device tree files.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-05-03 09:05:24 -04:00
Nitin Yadav
4d03f476a7 arm: mach-k3: Workaround errata ID i2331
Errata doc: https://www.ti.com/lit/pdf/sprz457
Errata ID i2331 CPSW: Device lockup when reading CPSW registers

Details: A device lockup can occur during the second read of any CPSW
subsystem register after any MAIN domain power on reset (POR). A MAIN
domain POR occurs using the hardware MCU_PORz signal, or via software
using CTRLMMR_RST_CTRL.SW_MAIN_POR or CTRLMMR_MCU_RST_CTRL.SW_MAIN_POR.
After these resets, the processor and internal bus structures may get
into a state which is only recoverable with full device reset using
MCU_PORz.
Due to this errata, Ethernet boot should not be used on this device.

Workaround(s): To avoid the lockup, a warm reset should be issued after
a MAIN domain POR and before any access to the CPSW registers. The warm
reset realigns internal clocks and prevents the lockup from happening.
Workaround above errata by calling do_reset() in case of cold boot in
order to trigger warm reset. This needs enabling SYSRESET driver in R5
SPL to enable TI SCI reset driver.

Signed-off-by: Nitin Yadav <n-yadav@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2023-05-03 09:05:24 -04:00
Daniel Golle
d7bb109900 board: mediatek: add Bananapi-R3 devicetree
Add board specific devicetree for Bananapi R3 SBC.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2023-05-03 09:05:24 -04:00
Aradhya Bhatia
28e5e95bf8 arm: mach-k3: am62a7: Enable QoS for DSS
Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to 8.

The C7x and VPAC have been overwhelming the DSS's access to the DDR
(when it was accessing via the Non Real-Time (NRT) Queue), primarily
because their functional frequencies, and hence DDR accesses, were
significantly higher than that of DSS. This led the display to flicker
when certain edgeAI models were being run.

With the DSS traffic serviced from the RT queue, the flickering issue
has been found to be mitigated.

The am62a qos files are auto generated from the k3 resource partitioning
tool.

Section-3.1.12, "QoS Programming Guide", in the AM62A TRM[1], provides
more information about the QoS, and section-14.1, "System Interconnect
Registers", provides the register descriptions.

[1] AM62A Tech Ref Manual: https://www.ti.com/lit/pdf/spruj16

Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
2023-05-03 09:05:24 -04:00
Manorit Chawdhry
4b6e3d39cf arm: mach-k3: j7200: Fix firewall warnings at boot time
J721E and J7200 have same file j721e_init.c which had the firewall
configs for J721E being applied on J7200 causing the warnings. Split the
firewalls for both the boards to remove those warnings.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-03 09:05:24 -04:00
Manorit Chawdhry
b8ebf24e7f arm: mach-k3: common: don't reconfigure background firewalls
K3 devices have some firewalls set up by ROM that we usually remove so
that the development is easy in HS devices.

While removing the firewalls disabling a background region before
disabling the foreground regions keeps the firewall in a state where all
the transactions will be blacklisted until all the regions are disabled.
This causes a race for some other entity trying to access that memory
region before all the firewalls are disabled and causes an exception.

Since the background regions configured by ROM are in such a manner
that they allow all transactions, don't touch the background regions at
all.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
2023-05-02 14:24:36 -04:00
Vignesh Raghavendra
fdb051ba3f arm: mach-k3: common: Default to non fitImage boot on HS-FS
Allow non fitImage bootflow on Field Securable (HS-FS) devices in
addition to GP, force fitImage boot only on Security enforced (HS-SE)
devices where signed images are necessary to maintain chain of trust.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
2023-05-02 14:23:59 -04:00
Vladimir Zapolskiy
0e889a7c1b arm: dts: msm: add GENI SE QUP device tree node
On modern Qualcomm platforms including SDM845 a GENI SE QUP IP
description is supposed to be found in board device tree nodes,
the version of the IP is used by the GENI UART driver to properly
set an oversampling divider value, which impacts UART baudrate.

The change touches dragonboard845c and starqltechn board device
tree source files, a device tree node label to "debug" UART is
renamed to 'uart9' according to the naming found in Linux.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
2023-05-02 14:23:59 -04:00
Konrad Dybcio
aa539d89e1 serial: msm-geni: Use upstream Linux bindings
The name "se" is used in upstream Linux device trees and has been for
ages, long before this U-Boot-ism was introduced. Same goes for the
existing compatible. Get rid of that.

[vzapolskiy: removed a ready change in the driver]
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
2023-05-02 14:23:58 -04:00
Linus Walleij
6f63c296fe board: Add new Broadcom Northstar board
This adds a simple Northstar "BRCMNS" board to be used with
the BCM4708x and BCM5301x chips.

The main intention is to use this with the D-Link DIR-890L
and DIR-885L routers for loading the kernel into RAM from
NAND memory using the BCH-1 ECC and using the separately
submitted SEAMA load command, so we are currently not adding
support for things such as networking.

The DTS file is a multiplatform NorthStar board, designed to
be usable with several NorthStar designs by avoiding any
particulars not related to the operation of U-Boot.

If other board need other ECC for example, they need to
create a separate DTS file and augment the code, but I don't
know if any other users will turn up.

Cc: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-05-02 14:23:58 -04:00
Linus Walleij
d3d9cd8ee1 arm: Add support for the Broadcom Northstar SoCs
The original Northstar is an ARM SoC series that comprise
BCM4709x and BCM5301x and uses a dual-core Cortex A9, the
global timer and a few other things.

This series should not be confused with North Star Plus
(NSP) which is partly supported by U-Boot already.

The SoC is well supported by the Linux kernel and OpenWrt
as it is used in many routers.

Since we currently don't need any chip-specific quirks
and can get the system up from just the device tree, a
mach-* directory doesn't even need to be added, just
some small Kconfig fragments.

Cc: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-05-02 14:23:58 -04:00
Linus Walleij
8a5122bfd3 arm: dts: Import device tree for Broadcom Northstar
This brings in the main SoC device tree used by the
Broadcom Northstar chipset, i.e. BCM4709x and BCM5301x.
This is taken from the v6.3 Linux kernel.

Cc: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-05-02 14:23:58 -04:00
Hugo Villeneuve
feb710b381 arm: imx8m: remove unused and obsolete board_fix_fdt() in SOC context
It doesn't seem appropriate for arch/SOC to use a board-level
functionality (CONFIG_OF_BOARD_FIXUP), because this prevents boards
that need to do FDT fixup from using that feature.

Also, this code is completely dead and useless (from comments by
Rasmus Villemoes on the mailing list):

  - No in-tree imx8m-based board seems to set CONFIG_OF_BOARD_FIXUP
  - The nodes which that function wants to disable don't even exist in
    the U-Boot copy of imx8mp.dtsi.

This code was introduced in commit 35bb60787b. It seems to be some
random import of code from downstream NXP U-Boot, with a commit
message that makes no sense in upstream context.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-05-02 10:57:32 +02:00
Tim Harvey
a48a824dba imx: fix get_boot_device() for imx8
commit 787f04bb6a ("imx: add USB2_BOOT type") broke get_boot_device()
for IMX8 which affects booting from SDP due to boot_instance being
non-zero.

Fix this by only using boot_instance for imx8ulp and imx9.

Fixes: 787f04bb6a ("imx: add USB2_BOOT type")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-05-02 10:57:32 +02:00
Dario Binacchi
1490292a07 imx6: clock: print real pixel clock rate
Add debug messages to print the real pixel clock rate, which may not be
the requested one.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-05-02 10:57:32 +02:00
Dario Binacchi
82863a99c0 imx6: clock: add support to get LCD pixel clock rate
Add the get_lcd_clk() function to get the LCD pixel clock rate.

The patch has been tested on imx6ul platform.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-05-02 10:57:32 +02:00
Dario Binacchi
41d7a7da80 imx6: clock: improve calculations to get the PLL video rate
During some tests to check the pixel clock rate in the transition from
U-Boot to the Linux kernel, I noticed that with the same configuration
of the registers the debug messages reported different rates.

The same Linux kernel calculations are now used to get the PLL video
rate.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-05-02 10:57:32 +02:00
Oliver Graute
3bc6257e80 imx: support i.MX8QM DMSSE20 a1 board
Add i.MX8QM DMSSE20 a1 board support

U-Boot 2023.04-00030-g7be2f547b2 (Apr 21 2023 - 11:11:43 +0200)

Model: Advantech iMX8QM DMSSE20
Board: DMS-SE20A1 8GB
Build: SCFW 549b1e18, SECO-FW c9de51c0, ATF 5782363
Boot:  USB
DRAM:  8 GiB
Core:  100 devices, 19 uclasses, devicetree: separate
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:    serial@5a060000
Out:   serial@5a060000
Err:   serial@5a060000
Net:   eth0: ethernet@5b040000
Warning: ethernet@5b050000 (eth1) using random MAC address - 32:05:0c:f9:5e:10
, eth1: ethernet@5b050000
Hit any key to stop autoboot:  0

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
2023-05-02 10:57:32 +02:00
Heinrich Schuchardt
76ce66408d imx8mn: buffer overflow in low_drive_gpu_freq()
Avoid a buffer overflow if assigned-clock-rates has less than two elements.

Fixes: 98bcdf1635 ("imx8mn: Add low drive mode support for DDR4/LPDDR4 EVK")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-05-02 10:57:32 +02:00
Patrick Wildt
ebe2e0c309 board: mntre: imx8mq: Add MNT Reform 2 board support
The MNT Reform 2 is a modular DIY laptop.  In its initial version it
is based on the BoundaryDevices i.MX8MQ SoM.  Some parts have been
lifted from BoundaryDevices official U-Boot downstream project.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Signed-off-by: Stefano Babic <sbabic@denx.de>
2023-05-02 10:57:22 +02:00
Samuel Holland
09cbd3858f gpio: axp/sunxi: Remove virtual VBUS detection GPIO
Now that this functionality is modeled using the device tree and
regulator uclass, the named GPIO is not referenced anywhere. Remove it.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-28 01:30:24 +01:00
Samuel Holland
9a4aa31ad5 sunxi: binman: Fix U-Boot offset when SPL is not 32 KiB
On sunxi boards, SPL looks for U-Boot at a 32 KiB offset, unless SPL is
larger than 32 KiB, in which case U-Boot immediately follows SPL. See
the logic in spl_mmc_get_uboot_raw_sector() and spl_spi_load_image().

In two cases, the existing binman description mismatches the SPL code.
For 64-bit boards, binman would place U-Boot immediately following SPL,
even if SPL is smaller than 32 KiB. This can happen when SPL MMC support
is disabled (i.e. when booting from SPI flash).

In contrast, for 32-bit boards, binman would place U-Boot at 32 KiB,
even if SPL is larger than that. This happens because the 'offset'
property does not consider the size of previous entries.

Fix both issues by setting a minimum size for the SPL entry, which
exactly matches the logic in the SPL code. Unfortunately, this size must
be provided as a magic number, since none of the relevant config symbols
(SPL_PAD_TO, SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, and SYS_SPI_U_BOOT_OFFS)
are guaranteed to be defined in all cases.

Fixes: cfa3db602c ("sunxi: Convert 64-bit boards to use binman")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-28 01:06:57 +01:00
Abdellatif El Khlifi
da458bcae5 corstone1000: add NVM XIP QSPI device tree node
add QSPI flash device node for block storage access

Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
2023-04-27 17:01:15 -04:00
Simon Glass
7755dc58af rockchip: Move to standard boot
Drop the distro-boot scripts and use standard boot instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Jonas Karlman <jonas@kwiboo.se>
2023-04-26 08:43:05 -04:00
Pali Rohár
7add47959e arm: omap3: Directly use SMC #1 in lowlevel_init.S
Since commit de39dc7162 ("arm: armv7-a: Compile and tune for armv7-a
instead of armv5") is used -march=armv7-a option for Omap3 platforms.

With directive ".arch_extension sec" it is possible for -march=armv7-a to
directly use ARM SMC instruction.

So enable ".arch_extension sec" in Omap3 lowlevel_init.S and replace hand
assembled ".word 0xe1600071" by "SMC #1".

Since commit 51d0638650 ("arm: omap-common: add secure smc entry") same
pattern is already used in arch/arm/cpu/armv7/omap-common/lowlevel_init.S.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-04-25 15:31:28 -04:00
Michal Simek
44cd761ad6 xen: Fix Kconfig dependencies
XEN config can be enabled by other platforms (even it doesn't need to make
sense) that's why fix dependencies. XEN (xenbus.c) requires sscanf (also
pvblock needs it). And PVBLOCK is inside drivers/xen folder which requires
XEN to be enabled.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-04-25 15:31:28 -04:00
Tom Rini
b5fc9f99d0 armv7: Use isb/dsb directly in start.S
Toolchains which do not directly support using "isb" and "dsb" directly
are no longer functionally supported in U-Boot. Furthermore, clang has
for a long time warned about using the alternate form that we were.
Update the code.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-25 15:31:27 -04:00
Tom Rini
a27c8ea7f7 arm: Centralize fixed register logic
When building for ARM64, we need to pass -ffixed-x18 and otherwise pass
-ffixed-r9. Rather than having this logic in two places, we can do this
once in arch/arm/config.mk. Further, while gcc will ignore being passed
both -ffixed-r9 and -ffixed-x18 and simply use -ffixed-x18, clang will
note that -ffixed-r9 is not used. Remove this duplication to also remove
the warning.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-25 15:31:27 -04:00
Tom Rini
c2e5eea38a arm: Only support ARM64_CRC32 when using GCC
Today, only gcc has __builtin_aarch64_crc32b (clang-16 does not, for
example). Make this option depend on CC_IS_GCC.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-25 15:31:27 -04:00
Pavel Skripkin
de0095b400 arm64: interrupts: print FAR_ELx on sync exceptions
Default synchronous exceptions handler prints only esr and register
dump. Sometimes it requiers to see an address which caused exceptions
to understand what's going on

ARM ARM in section D13.2.41 states that FAR_EL2 will contain meanfull
value in case of ESR.EC holds 0x20, 0x21, 0x24, 0x25, 0x22, 0x34 or
0x35. Same applies for EL1.

This patch adds function whivh determine current EL, gets correct FAR
register and prints it on panic.

Signed-off-by: Pavel Skripkin <paskripkin@gmail.com>
2023-04-25 15:31:27 -04:00
Jayesh Choudhary
2e43ba7805 arch: mach-k3: j721s2_init: Disable the firewalls
Some firewalls enabled by ROM are still left on. So some
address space is inaccessible to the bootloader. For example,
in OSPI boot mode we get an exception and the system hangs.
Therefore, disable all the firewalls left on by the ROM.

Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-25 15:31:27 -04:00
meitao
c1da6fdb5c armv8: enable HAFDBS for other ELx when FEAT_HAFDBS is present
u-boot could be run at EL1/EL2/EL3. so we set it as same as EL1 does.
otherwise it will hang when enable mmu, that is what we encounter
in our SOC.

Signed-off-by: meitao <meitaogao@asrmicro.com>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: 3bf38943ae
2023-04-25 15:31:27 -04:00
Marc Zyngier
836b8d4b20 arm64: Use level-2 for largest block mappings when FEAT_HAFDBS is present
In order to make invalidation by VA more efficient, set the largest
block mapping to 2MB, mapping it onto level-2. This has no material
impact on u-boot's runtime performance, and allows a huge speedup
when cleaning the cache.

Signed-off-by: Marc Zyngier <maz@kernel.org>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: 417a73581a
2023-04-25 15:31:27 -04:00
Marc Zyngier
6cdf6b7a34 arm64: Use FEAT_HAFDBS to track dirty pages when available
Some recent arm64 cores have a facility that allows the page
table walker to track the dirty state of a page. This makes it
really efficient to perform CMOs by VA as we only need to look
at dirty pages.

Signed-off-by: Marc Zyngier <maz@kernel.org>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: 3c433724e6
2023-04-25 15:31:27 -04:00
Christian Gmeiner
c0c56f64b3 arm: mach-k3: am642: move do_dt_magic() after sysfw loading
Makes it possible to use e.g mcu_spi0 for custom board detection.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2023-04-24 13:18:49 -04:00
Manorit Chawdhry
1e00e9be62 arm: mach-k3: common: re-locate authentication for atf/optee
For setting up the master firewalls present in the K3 SoCs, the arm64
clusters need to be powered on.

Re-locates the code for atf/optee authentication.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-24 13:18:48 -04:00
Manorit Chawdhry
53f02be32e arm: dts: k3-am625-r5-sk: add a53 cluster power
adds a53 cluster to control from the rproc driver

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-24 13:18:48 -04:00
Manorit Chawdhry
9a36735b0f arm: dts: k3-am62a7-r5-sk: add a53 cluster power domain node
adds a53 cluster to control from the rproc driver

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-24 13:18:48 -04:00
Manorit Chawdhry
3922cf6295 arm: dts: k3-am642-r5: add a53 cluster power domain node
adds a53 cluster to control from the rproc driver

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-24 13:18:48 -04:00
Manorit Chawdhry
7fe7920c5e arm: dts: k3-am642-r5-sk: add a53 cluster power domain node
adds a53 cluster to control from the rproc driver

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-24 13:18:48 -04:00
Manorit Chawdhry
dcdcbde2bb arm: dts: k3-j7200-r5: add a72 cluster power domain node
adds a72 cluster to control from the rproc driver

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-24 13:18:48 -04:00
Manorit Chawdhry
bdbd668853 arm: dts: k3-j721e-r5: add a72 cluster power domain node
adds a72 cluster to control from the rproc driver

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-24 13:18:48 -04:00
Manorit Chawdhry
ab3df39ffa arm: dts: k3-j721e-r5-sk: add a72 cluster power domain node
adds a72 cluster to control from the rproc driver

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-24 13:18:48 -04:00
Manorit Chawdhry
d363013e87 arm: dts: k3-j721s2-r5: add a72 cluster power domain node
adds a72 cluster to control from the rproc driver

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-04-24 13:18:48 -04:00
Andrew Davis
f392860c2e arm: mach-k3: Remove empty sys_proto.h include
This header file is now empty, remove it.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24 13:18:48 -04:00
Andrew Davis
29627e81c6 arm: mach-k3: Move J721s2 SPL init functions to mach-k3
This matches AM64 and J721e and removes the need to forward
declare k3_spl_init(), k3_mem_init(), and check_rom_loaded_sysfw()
in sys_proto.h.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24 13:18:48 -04:00
Andrew Davis
ef538cc26e arm: mach-k3: Move sdelay() and wait_on_value() declaration
These probably should be in some system wide header given their use.
Until then move them out of K3 sys_proto.h so we can finish cleaning
that header out.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24 13:18:48 -04:00
Andrew Davis
ee12d64f2d arm: mach-k3: Remove unused fdt_disable_node()
This function is not used currently; remove it.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24 13:18:48 -04:00
Andrew Davis
e25fe5b275 arm: mach-k3: Add weak do_board_detect() to common file
This matches how it was done for pre-K3 TI platforms and it allows
us to move the forward declaration out of sys_proto.h.

It also removes the need for K3_BOARD_DETECT as one is free to simply
override the weak function in their board files as needed.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24 13:18:48 -04:00
Andrew Davis
f5e4944608 arm: mach-k3: Move sysfw-loader.h out of mach includes
This header is only used locally by K3 init files, no need to have it
up with the global mach includes. Move into local includes.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24 13:18:48 -04:00
Andrew Davis
2aee173ba0 arm: mach-k3: Make release_resources_for_core_shutdown() common
This function is the same for each device when it needs to shutdown
the R5 core. Move this to the common section and move the remaining
device specific ID list to the device hardware include.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24 13:18:48 -04:00
Andrew Davis
ca0973741d arm: mach-k3: Move J721e SoC detection out of common section
This belongs in the J721e specific file as it is the only place
this is used. Any board level users should use the SOC driver.

While here, move the J721e and J7200 SoC IDs out of sys_proto.h
and into hardware.h. Use a macro borrowed from Rockchip and add
the rest of the SoC IDs for completeness and later use.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
30e96a2401 arm: mach-k3: Move MSMC fixup to SoC level
The MSMC fixup is something we do based on SoC, not based on the board.
So this fixup does not belong in the board files. Move this to the
mach-k3 common file so that it does not have to be done in each board
that uses these SoCs.

We use ft_system_setup() here instead of ft_board_setup() since it is no
longer board level. Enable OF_SYSTEM_SETUP in the configurations that use
this to keep functionality the same.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
5cf850c162 Revert "arm: dts: dra7*/am57xx-idk-evm-u-boot: Add ipu early boot DT changes"
This reverts commit 5717294230. This
does not exist in upstream kernel.org and breaks boot on DRA7-EVMs.
Drop the same.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
db5a3bda50 arm: dts: keystone: Non-functional changes sync with v6.3-rc6
This is a collection of all the whitespace, renames, comment, and other
changes that should not change the DT functionality from Linux v6.3-rc6.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
a39f2a54dd arm: dts: omap: Non-functional changes sync with v6.3-rc6
This is a collection of all the whitespace, renames, comment, and other
changes that should not change the DT functionality from Linux v6.3-rc6.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
1fb69a07bc arm: dts: dm8x: Non-functional changes sync with v6.3-rc6
This is a collection of all the whitespace, renames, comment, and other
changes that should not change the DT functionality from Linux v6.3-rc6.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
f8ae3e605b arm: dts: dra7x: Non-functional changes sync with v6.3-rc6
This is a collection of all the whitespace, renames, comment, and other
changes that should not change the DT functionality from Linux v6.3-rc6.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
211b3d7263 arm: dts: am3x: Non-functional changes sync with v6.3-rc6
This is a collection of all the whitespace, renames, comment, and other
changes that should not change the DT functionality from Linux v6.3-rc6.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
1dfb028e04 arm: dts: am437x: Update to IOPAD to sync with v6.3-rc6
Several DTS files have been updated in the Linux kernel with a new
IOPAD macro. Sync for the same here.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
2657c52e08 arm: dts: am3x: Update IOPAD to PADCONF to sync with v6.3-rc6
Several DTS files have been updated in the Linux kernel with a new
PADCONF macro replacing the IOPAD version. Sync for the same here.

Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
25abf73466 arm: dts: keystone: Update devicetree header comments to sync with v6.3-rc6
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:47 -04:00
Andrew Davis
5a6df00831 arm: dts: omap5x: Update devicetree header comments to sync with v6.3-rc6
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:46 -04:00
Andrew Davis
590f1d995a arm: dts: omap4x: Update devicetree header comments to sync with v6.3-rc6
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:46 -04:00
Andrew Davis
1346dc573b arm: dts: omap3x: Update devicetree header comments to sync with v6.3-rc6
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:46 -04:00
Andrew Davis
854d489e24 arm: dts: dra7x: Update devicetree header comments to sync with v6.3-rc6
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:46 -04:00
Andrew Davis
54efeef170 arm: dts: dm8x: Update devicetree header comments to sync with v6.3-rc6
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:46 -04:00
Andrew Davis
51b21c7985 arm: dts: am57x: Update devicetree header comments to sync with v6.3-rc6
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:46 -04:00
Andrew Davis
ad841299e7 arm: dts: am43x: Update devicetree header comments to sync with v6.3-rc6
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:46 -04:00
Andrew Davis
d30b2bf3b3 arm: dts: am3x: Update devicetree header comments to sync with v6.3-rc6
Signed-off-by: Andrew Davis <afd@ti.com>
2023-04-24 13:18:46 -04:00
Tom Rini
328fdeb9c9 Merge tag 'u-boot-rockchip-20230421' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add rk3588 evb support;
- Update pinctrl for rk3568 and rk3588;
- Update rk3288 dts;
- Update mmc support for rk3568 and rk3588;
- Add rng support for rk3588;
- Add DSI support for rk3568;
- Some other misc fixes in dts, config, driver;
2023-04-23 12:15:56 -04:00
Tom Rini
f2db24556f configs:
_ Add usb_pgood_delay for ST boards
 _ increase malloc size for pre-reloc for stm32mp15
 _ Set CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2s for stm32mp15
 
 dts:
 _ Add QSPI support on STM32MP13x SoC family
 _ Add FMC support on STM32MP13x SoC family
 
 drivers/machine:
 _ pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing()
 _ spi: stm32_qspi: Remove useless struct stm32_qspi_flash
 _ rawnand: stm32_fmc2: remove unsupported EDO mode
 _ stm32mp: fix various array bounds checks
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Merge tag 'u-boot-stm32-20230419' of https://source.denx.de/u-boot/custodians/u-boot-stm

configs:
_ Add usb_pgood_delay for ST boards
_ increase malloc size for pre-reloc for stm32mp15
_ Set CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2s for stm32mp15

dts:
_ Add QSPI support on STM32MP13x SoC family
_ Add FMC support on STM32MP13x SoC family

drivers/machine:
_ pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing()
_ spi: stm32_qspi: Remove useless struct stm32_qspi_flash
_ rawnand: stm32_fmc2: remove unsupported EDO mode
_ stm32mp: fix various array bounds checks
2023-04-22 18:30:56 -04:00
FUKAUMI Naoki
7911f409ff arm: dts: rockchip: radxa-cm3-io, rock-3a: enable regulators for usb
enable regulators for usb host function

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 16:09:29 +08:00
Jonas Karlman
b564aa2740 rockchip: rk3588-rock-5b: Include eMMC node in SPL dtb
Add sdhci node to SPL and u-boot,spl-boot-order. Also add more supported
mmc modes and pinctrl.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:55:29 +08:00
Jonas Karlman
72b05764c3 rockchip: rk3568-rock-3a: Enable support for more eMMC modes
Add supported mmc modes to rk3568-rock-3a device tree.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:55:29 +08:00
Chris Morgan
f89167bb74 ARM: dts: rockchip: rk3588s-u-boot: Add rng node
Add a node for the trng found on RK3588 SoCs.

Changes in V3:
 - Added Reviewed-By tag.

Changes in V2:
 - None

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
2023-04-21 15:16:01 +08:00
Jonas Karlman
58c23015c9 rockchip: rk3588: Sync sdmmc node from linux-next
Sync the sdmmc node from linux-next, include required nodes in SPL and
imply Kconfig options required for functional sdmmc clk in SPL and
U-Boot proper.

This make it possible for both SPL and U-Boot proper to configure sdmmc
clocks. In SPL, before TF-A is loaded, scru regs is configured, in
U-Boot proper a SCMI message is sent to TF-A.

Fixes: 95c8656b72 ("ARM: dts: rockchip: rk3588s-u-boot: Add sdmmc node")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Jonas Karlman
6737771600 rockchip: rk3588: Add support for sdmmc clocks in SPL
Booting from sdmmc on RK3588 currently works because of a workaround in
the device tree, clocks are reordered so that the driver use ciu-sample
instead of ciu, and the BootRom initializes sdmmc clocks before SPL is
loaded into DRAM.

The sdmmc clocks are normally controlled by TF-A using SCMI. However,
there is a need to control these clocks in SPL, before TF-A has started.

This adds a rk3588_scru driver to control the sdmmc clocks in SPL before
TF-A has started, using scru regs. It also adds a small glue driver to
bind the scmi clock node to the rk3588_scru driver in SPL.

Fixes: 7a474df740 ("clk: rockchip: Add rk3588 clk support")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Jonas Karlman
e1962a9efe rockchip: rk35xx: Enable fdtoverlay and kernel compression
Add fdtoverlay_addr_r, kernel_comp_addr_r and imply use of
OF_LIBFDT_OVERLAY on RK3568 and RK3588 to support fdtoverlay
and kernel compression.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-21 15:16:01 +08:00
Jonas Karlman
9f412347be rockchip: rk35xx: Fix boot with a large fdt blob
The TF-A blobs used to boot RK3568 and RK3588 boards is based on atf
v2.3. Mainline atf v2.3 contains an issue that could lead to a crash
when it fails to parse the fdt blob being passed as the platform param.
An issue that was fixed in atf v2.4.

The vendor TF-A seem to suffer from a similar issue, and this prevents
booting when fdt blob is large enough to trigger this condition.

Fix this by implying SPL_ATF_NO_PLATFORM_PARAM to let u-boot pass a
NULL pointer instead of the fdt blob as the platform param.

This fixes booting Radxa ROCK 3A after recent sync of device tree.

Fixes: 073d911ae6 ("rockchip: rk3568-rock-3a: Sync device tree from linux")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-04-21 15:16:01 +08:00
Jonas Karlman
f1e190a192 rockchip: rk3588-rock-5b: Fix sdmmc boot
Running U-Boot from a SD-card on ROCK 5 Model B fails to load atf using
DMA and prints debug_uart messages.

  <debug_uart>

  <debug_uart>

  U-Boot SPL 2023.04-rc3 (Mar 12 2023 - 00:30:16 +0000)
  Trying to boot from MMC1
  ## Checking hash(es) for config config-1 ... OK
  ## Checking hash(es) for Image atf-1 ... sha256 error!
  Bad hash value for 'hash' hash node in 'atf-1' image node
  mmc_load_image_raw_sector: mmc block read error
  SPL: failed to boot from all boot devices
  ### ERROR ### Please RESET the board ###

Use fifo-mode to disable DMA in SPL, add same-as-spl to boot-order and
remove DEBUG_UART_ANNOUNCE option to fix this.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
John Keeping
999680c4ed rockchip: misc: fix misc_read() return check
misc_read() is documented to return the number of bytes read or a
negative error value.  The Rockchip drivers currently do not implement
this correctly and instead return zero on success or a negative error
value.

In preparation for fixing the drivers, fix the condition here to only
error on negative values.

Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
98125086d6 arm: dts: rockchip: sync rk3066/rk3188 DT files from linux-next v6.2-rc4
Sync rk3066/rk3188 DT files from Linux.
This is the state as of linux-next v6.2-rc4.
New nfc node for MK808 rk3066a.
CRU nodes now have a clock property.
To prefend dtoc errors a fixed clock must also be
included for tpl/spl in the rk3xxx-u-boot.dtsi file.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
e16be4dd8b arm: dts: rockchip: rk3188-u-boot: add gpio-ranges
The gpio node names are made generic, but without
gpio bank ID. Add gpio-ranges to rk3188-u-boot.dtsi
for now till a better method is found.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
fed814c088 arm: dts: rockchip: rk3066a-u-boot: add gpio-ranges
The gpio node names are made generic, but without
gpio bank ID. Add gpio-ranges to rk3066a-u-boot.dtsi
for now till a better method is found.
Disable gpio6 as the driver gives an error code
on return as status.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
ba607e2b9a arm: dts: rockchip: rk3288: partial sync pwm nodes
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the pwm nodes.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
7c1ee7a848 arm: dts: rockchip: rk3288: partial sync vop/lvds/mipi/hdmi nodes
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the vop/lvds/mipi/hdmi nodes.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>  # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
bf13676e0b arm: dts: rockchip: rk3288: partial sync edp node
The rk3288 edp node has a phy node in Linux with a clock
property while current U-Boot driver expects this clock
on position index 1. Move U-Boot-specific DT clock properties
to rk3288-u-boot.dtsi and partially sync the edp node.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>  # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
da5ae37fcd arm: dts: rockchip: rk3288: partial sync grf and pmu nodes
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the grf and pmu nodes.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>  # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:00 +08:00
Johan Jonker
35e9e8aebf arm: dts: rockchip: rk3288: move io-domains nodes
In order to better compare the Linux rk3288.dtsi version
with the U-Boot version move the io-domains nodes.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: John Keeping <john@metanate.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>  # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:00 +08:00
John Keeping
24fea3f837 rockchip: rk3288: Use ft_system_setup instead of ft_board_setup
ft_board_setup() should be availble for use in board files but using it
in the rk3288 machine file blocks this functionality.

ft_system_setup() is the more appropriate function to use in a machine
definition.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:00 +08:00
Jonas Karlman
f7ad2912c6 rockchip: Use an external TPL binary on RK3588
There is no support to initialize DRAM on RK3588 SoCs using U-Boot TPL
and instead an external TPL binary must be used to generate a bootable
u-boot-rockchip.bin image.

Enable ROCKCHIP_EXTERNAL_TPL by default for RK3588, add build steps for
RK3588 to documentation and clean up CONFIG_BINMAN_FDT options.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jagan Teki <jagan@edgeble.ai>
2023-04-21 15:16:00 +08:00
Kever Yang
cf8658cdac board: rockchip: Add rk3588 evb
rk3588 evb1 v10 is a evalution board from Rockchip, it is a dev board for
rockchip and also a reference board for board vendors.

Hardware:
SoC: RK3588
DRAM: LPDDR4X 8GB
Debug: UART2 via USB
PCIe: 3x4 *1
SATA *2
HDMI out *2
HDMI IN *1
USB2.0 Host *2
USB3.0 Host *1
Type C *1
MIPI DSI panel

dts Sync from Linux v6.2.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@edgeble.ai>
2023-04-21 15:16:00 +08:00
Rasmus Villemoes
daf07215e8 stm32mp: fix various array bounds checks
In all these cases, the index on the LHS is immediately afterwards
used to access the array appearing in the ARRAY_SIZE() on the RHS - so
if that index is equal to the array size, we'll access
one-past-the-end of the array.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-04-19 10:02:28 +02:00
Christophe Kerello
fa998c8aea ARM: dts: stm32: add FMC support on STM32MP13x SoC family
Add FMC support on STM32MP13x SoC family.

Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-04-19 09:59:36 +02:00