Commit graph

768 commits

Author SHA1 Message Date
Miquel Raynal
748b5b34d3
sunxi: move the NAND parameters to Kconfig
Move the NAND parameters from defconfig files to Kconfig for SUNXI
architecture only. Fort now only the CHIP pro is migrated.

It would have been better to convert this defconfig entry to Kconfig for
all supported machines/architectures but it has been abandoned due to a
fairly high amount of errors reported by the moveconfig.py tool. This is
due to defines quite often being multiplications of values/other defines
not correctly handled.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 12:13:32 +02:00
Miquel Raynal
b56052f4ca
sunxi: make NAND_SUNXI use ARCH_SUNXI as default in Kconfig
Remove NAND_SUNXI from the CHIP pro defconfig to be automatically
selected depending on the state of ARCH_SUNXI.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 12:13:27 +02:00
Miquel Raynal
6d094d535c
sunxi: automatically select SPL_NAND_SUPPORT in Kconfig
Make SUNXI_NAND select SPL_NAND_SUPPORT in Kconfig, this limit the
number of entries to add in defconfig files when adding NAND support.

For now, the only board using it is the CHIP pro.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 12:13:06 +02:00
Miquel Raynal
663e8a9b54
sunxi: allow NAND support to be compiled for sun8i platforms
Add some clocks/PLL definitions as well as the dependency on MACH_SUN8I
in Kconfig.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 12:11:52 +02:00
Miquel Raynal
6ddbb1e936
spl: nand: sunxi: use PIO instead of DMA
SPL support was first written to support only the earlier generations of
Allwinner SoCs, and was only really enabled on the A13 / GR8. However,
those old SoCs had a DMA engine that has been replaced since the A31 by
another DMA controller that is no longer compatible.

Since the code directly uses that DMA controller, it cannot operate
properly on the later SoCs, while the NAND controller has not changed.

There's two paths forward, the first one would have been to add support
for that DMA controller too, the second to just remove the DMA usage
entirely and rely on PIO.

The later has been chosen because CPU overload at this stage is not an
issue and it makes the driver more generic, and easier to understand.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 12:11:43 +02:00
Miquel Raynal
7440bd7885
spl: nand: sunxi: declare the ecc_bytes array globally
Move the ecc_bytes array out of nand_max_ecc_strength() for future use
by nand_read_page().

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 12:11:38 +02:00
Miquel Raynal
22f0aa0528
spl: nand: sunxi: make the reset column helper more generic
Prepare the future use of an helper to move the data pointer (the
column) of the NAND chip by renaming nand_reset_column() to
nand_change_column(). Resetting the column is just a matter of giving 0
as argument.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 12:11:28 +02:00
Miquel Raynal
4dac80a5e9
spl: nand: sunxi: ensure enough time has passed after changing the column
When changing the column, the ONFI specification states that a minimum
time of tCCS (Change Column Setup time) must elapse between the last
address cycle is asserted on the bus and the first data cycle is
clocked. An usual value for average NANDs is 500 nanoseconds. Round it
up to 1 microsecond to be safe.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 12:11:22 +02:00
Miquel Raynal
a084cb6664
spl: nand: sunxi: create an helper to handle command execution
Executing a command is matter of always doing the following sequence:
  * Waiting for the FIFO to be empty so we can fill it with the new
    command.
  * Clearing the status register.
  * Writing the command in the FIFO.
  * Waiting for the command to finish.

Add a nand_exec_cmd() helper to handle this instead of repeating the
logic through the various functions.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 12:11:17 +02:00
Miquel Raynal
781e70cff1
spl: nand: sunxi: add missing status clear
It is best practice to always clear the status register before executing
a command to be sure that the status read afterwards is relevant.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 12:11:13 +02:00
Miquel Raynal
60fb179133
spl: nand: sunxi: introduce the nand_wait_cmd_fifo_empty() helper
One bit in the control registers indicates if the NAND controller is
ready to receive a new command. Otherwise, the command FIFO is full and
we should wait for this bit to flip. It then states that the last
command has been processed and the FIFO is now free to welcome another
command.

Add this sanity check before starting any new command.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 12:11:07 +02:00
Miquel Raynal
28f7a9d375
spl: nand: sunxi: introduce the nand_wait_int() helper
The pattern of polling on a status register until a bit is set or a
timeout occurs is repeated multiple times in the driver. Mutualize the
code by introducing the nand_wait_int() helper that does wait for the
bit to flip or returns an error in case of timeout.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 12:11:04 +02:00
Miquel Raynal
802f766994
spl: nand: sunxi: fix typo on register name
Change NFC_SEND_ADR to NFC_SEND_ADDR.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 12:10:59 +02:00
Miquel Raynal
a0a984e14a
spl: nand: sunxi: fix second case of modulo by zero error
In the nand_read_buffer() step, the seed is calculated by doing a modulo
by conf->nseeds which is always zero when not using the randomizer (most
of SLC NANDs).

This situation turns out to lead to a run time freeze with certain
toolchains.

Derive this seed only when the randomizer is enabled (and conf->nseeds
logically not zero), exactly like what has been done before with an
identical situation, see commit ea3f750c73 ("nand: sunxi: Fix modulo
by zero error").

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 12:10:55 +02:00
Miquel Raynal
f3aff37689
mtd: nand: sunxi: fix ECC strength choice
When the requested ECC strength does not exactly match the strengths
supported by the ECC engine, the driver is selecting the closest
strength meeting the 'selected_strength > requested_strength'
constraint. Fix the fact that, in this particular case, ecc->strength
value was not updated to match the 'selected_strength'.

For instance, one can encounter this issue when no ECC requirement is
filled in the device tree while the NAND chip minimum requirement is not
a strength/step_size combo natively supported by the ECC engine.

Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 12:10:46 +02:00
Vipul Kumar
2453c69518 arm64: zynqmp: nand: Fixed NAND erase issue for size 1GiB or more
NAND erase was not happening for size 1GiB or more. Erase
command was executing successfully but in actual, it was not
erasing.
This patch fixed erase issue for 1 GiB or more size nand.

Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:34:44 +01:00
Stefan Roese
ec9c80d643 nand: Remove unused ppc4xx NAND driver and references
ppc4xx support was removed some time ago. Lets remove the now unused
NAND driver and all its references for this platform as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Scott Wood <oss@buserror.net>
2018-03-19 16:14:23 -04:00
Adam Ford
99bec1aead Convert CONFIG_APBH_DMA et al to Kconfig
This converts the following to Kconfig:
   CONFIG_APBH_DMA
   CONFIG_APBH_DMA_BURST
   CONFIG_APBH_DMA_BURST8

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
[trini: Add in MMC as well]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-02-08 12:48:11 -05:00
Stefan Agner
c87c81186c Convert CONFIG_NAND_MXS to Kconfig
This converts CONFIG_NAND_MXS to Kconfig.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-02-08 10:17:17 -05:00
Ezequiel Garcia
d55c8159bd nand: arasan: Select CONFIG_SYS_NAND_SELF_INIT
The Arasan NFC driver requires the self-init mode,
so it should select it.

Instead of having the config header define the macro,
it's cleaner to select the option at the Kconfig level.

Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-30 14:29:07 +01:00
Siva Durga Prasad Paladugu
f25ac66c52 nand: arasan_nfc: Use the calculated ecc address for updating ecc register
This patch corrects the ecc address calculation before updating
to ecc register. The ecc address has to be calculated based on
page, oob and ecc sizes of the device.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-30 14:29:07 +01:00
Siva Durga Prasad Paladugu
cacb8a029f nand: arasan_nfc: Add support for ondie ecc
This patch adds support for ondie ecc. As of now
this adds support for micron parts which supports
ondie ecc.
Didn't found any better way to detect ondie ecc
support by a device except sorting out with
manufacture and device id's.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-30 14:29:07 +01:00
Siva Durga Prasad Paladugu
b08fc34f3f nand: arasan_nfc: Move common ecc struct initialization init routine
Move common part of ecc structure initialization to
arasan_nand_init() routine.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-30 14:29:07 +01:00
Jagan Teki
ca9d211e2c mtd: nand: mxs_nand_spl: Remove nand size print
It is not much needed to print nand size in SPL during nand boot,
and most of nand spl drivers doesn't print the same.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-01-08 17:37:12 +01:00
Masahiro Yamada
dc774e69bb mtd: nand: denali: make NAND_DENALI unconfigurable option
denali.c has no driver entry in itself.  It makes sense only when
compiled together with denali_dt.c

Let NAND_DENALI_DT select NAND_DENALI, and hide NAND_DENALI from
the Kconfig menu.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-12 00:36:11 +09:00
Masahiro Yamada
0faef2eba9 mtd: nand: denali: consolidate include directives
Include necessary headers explicitly without relying on indirect
header inclusion.

<common.h>, <malloc.h> are unneeded.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-04 22:00:03 +09:00
Masahiro Yamada
681ed4d0d5 mtd: nand: denali_dt: replace printf() with pr_err()
The Linux derived log functions can be used anywhere and easily
turned on/off by CONFIG_LOGLEVEL.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-04 22:00:02 +09:00
Masahiro Yamada
6ae3900a86 mtd: nand: Rename nand.h into rawnand.h
This header was renamed to rawnand.h in Linux.

The following is the corresponding commit in Linux.

  commit d4092d76a4a4e57b65910899948a83cc8646c5a5
  Author: Boris Brezillon <boris.brezillon@free-electrons.com>
  Date:   Fri Aug 4 17:29:10 2017 +0200

      mtd: nand: Rename nand.h into rawnand.h

      We are planning to share more code between different NAND based
      devices (SPI NAND, OneNAND and raw NANDs), but before doing that
      we need to move the existing include/linux/mtd/nand.h file into
      include/linux/mtd/rawnand.h so we can later create a nand.h header
      containing all common structure and function prototypes.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-04 22:00:00 +09:00
Masahiro Yamada
57f9bb9404 mtd: nand: denali: remove ad-hoc board_nand_init() entry
This driver is highly dependent on the configuration from denali_dt.c
Please enable CONFIG_NAND_DENALI_DT if you use this driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-04 21:59:59 +09:00
Masahiro Yamada
1a7e176d27 mtd: nand: denali: remove bogus __maybe_unused
denali_setup_data_interface() is always used.

I put __maybe_unused for a temporal use, then forgot to delete it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-04 21:59:53 +09:00
Sean Nyekjaer
e13921a951 fix: nand: pxa3xx: fix defined but not used warnings
bbt_mirror_descr and bbt_main_descr is defined but not used
when compiling without CONFIG_SYS_NAND_USE_FLASH_BBT set.

Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-30 08:25:06 +01:00
Tom Rini
b06c46de63 Xilinx changes for v2018.1
Zynq:
 - Add support for Syzygy and cc108 boards
 - Add support for mini u-boot configurations (cse)
 - dts updates
 - config/defconfig updates in connection to Kconfig changes
 - Fix psu_init handling
 
 ZynqMP:
 - SPL fixes
 - Remove slcr.c
 - Fixing r5 startup sequence
 - Add support for external pmufw
 - Add support for new ZynqMP chips
 - dts updates
 - Add support for zcu102 rev1.0 board
 
 Drivers:
 - nand: Support external timing setting and board init
 - ahci: Fix wording
 - axi_emac: Wait for bit, non processor mode, readl/write conversion
 - zynq_gem: Fix SGMII/PCS support
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Merge tag 'xilinx-for-v2018.01' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.1

Zynq:
- Add support for Syzygy and cc108 boards
- Add support for mini u-boot configurations (cse)
- dts updates
- config/defconfig updates in connection to Kconfig changes
- Fix psu_init handling

ZynqMP:
- SPL fixes
- Remove slcr.c
- Fixing r5 startup sequence
- Add support for external pmufw
- Add support for new ZynqMP chips
- dts updates
- Add support for zcu102 rev1.0 board

Drivers:
- nand: Support external timing setting and board init
- ahci: Fix wording
- axi_emac: Wait for bit, non processor mode, readl/write conversion
- zynq_gem: Fix SGMII/PCS support
2017-11-29 08:26:07 -05:00
Joe Hershberger
6d3fa0dfdd mtd: nand: zynq: Add support for the NAND lock/unlock operation
Zynq NAND driver is not support for NAND lock or unlock operation.
Hence, accidentally write into the critical NAND region might cause
data corruption to occur.

This commit is to add NAND lock/unlock command into NAND SMC register
set for NAND lock/unlock operaion.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Scott Wood <oss@buserror.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Wilson Lee
310995d9f9 mtd: zynq: nand: Move board_nand_init() function to board.c
Putting board_nand_init() function inside NAND driver was not appropriate
due to it doesn't allow board vendor to customise their NAND
initialization code such as adding NAND lock/unlock code.

This commit was to move the board_nand_init() function from NAND driver
to board.c file. This allow customization of board_nand_init() function.

Signed-off-by: Wilson Lee <wilson.lee@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Cc: Scott Wood <oss@buserror.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29 08:02:40 +01:00
Masahiro Yamada
350d052dab mtd: nand: denali: sync with Linux 4.15-rc1
I largely reworked the Denali NAND controller driver in Linux.
This commit imports the improvements from Linux.  The code is
almost synced with Linux 4.15-rc1.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:59 +09:00
Masahiro Yamada
e6001371d1 mtd: nand: introduce NAND_ROW_ADDR_3 flag
Several drivers check ->chipsize to see if the third row address cycle
is needed.  Instead of embedding magic sizes such as 32MB, 128MB in
drivers, introduce a new flag NAND_ROW_ADDR_3 for clean-up.  Since
nand_scan_ident() knows well about the device, it can handle this
properly.  The flag is set if the row address bit width is greater
than 16.

Delete comments such as "One more address cycle for ..." because
intention is now clear enough from the code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Wenyou Yang <wenyou.yang@microchip.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

[Linux commit: 14157f861437ebe2d624b0a845b91bbdf8ca9a2d]
2017-11-29 00:28:59 +09:00
Masahiro Yamada
470c29d1c2 mtd: nand: add generic helpers to check, match, maximize ECC settings
Driver are responsible for setting up ECC parameters correctly.
Those include:
  - Check if ECC parameters specified (usually by DT) are valid
  - Meet the chip's ECC requirement
  - Maximize ECC strength if NAND_ECC_MAXIMIZE flag is set

The logic can be generalized by factoring out common code.

This commit adds 3 helpers to the NAND framework:
nand_check_ecc_caps - Check if preset step_size and strength are valid
nand_match_ecc_req - Match the chip's requirement
nand_maximize_ecc - Maximize the ECC strength

To use the helpers above, a driver needs to provide:
  - Data array of supported ECC step size and strength
  - A hook that calculates ECC bytes from the combination of
    step_size and strength.

By using those helpers, code duplication among drivers will be
reduced.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

[Linux commit: 2c8f8afa7f92acb07641bf95b940d384ed1d0294]
2017-11-29 00:28:59 +09:00
Boris Brezillon
52cde35b96 mtd: nand: Pass the CS line to ->setup_data_interface()
Some NAND controllers can assign different NAND timings to different
CS lines. Pass the CS line information to ->setup_data_interface() so
that the NAND controller driver knows which CS line is concerned by
the setup_data_interface() request.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 104e442a67cfba4d0cc982384761befb917fb6a1]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:59 +09:00
Masahiro Yamada
436fb2b84d mtd: nand: allow drivers to request minimum alignment for passed buffer
In some cases, nand_do_{read,write}_ops is passed with unaligned
ops->datbuf.  Drivers using DMA will be unhappy about unaligned
buffer.

The new struct member, buf_align, represents the minimum alignment
the driver require for the buffer.  If the buffer passed from the
upper MTD layer does not have enough alignment, nand_do_*_ops will
use bufpoi.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

[Linux commit: 477544c62a84d3bacd9f90ba75ffc16c04d78071]
2017-11-29 00:28:59 +09:00
Boris Brezillon
c7c553f249 mtd: nand: Wait for PAGEPROG to finish in drivers setting NAND_ECC_CUSTOM_PAGE_ACCESS
Drivers setting NAND_ECC_CUSTOM_PAGE_ACCESS are supposed to handle the
full read/write page sequence, and waiting for a page to actually be
programmed is part of this write-page sequence.
This is also what is done in ->write_oob_xxx() hooks, so let's do that in
->write_page_xxx() as well to make it consistent.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 41145649f4acb30249b636b945053db50c9331c5]
[masahiro:
 There is no driver setting NAND_ECC_CUSTOM_PAGE_ACCESS in U-Boot.
 No driver is affected by this change.]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Boris Brezillon
94b50a8aae mtd: nand: Drop the ->errstat() hook
The ->errstat() hook is no longer implemented NAND controller drivers.
Get rid of it before someone starts abusing it.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 7d135bcced20be2b50128432c5426a7278ec4f6d]
[masahiro: modify davinci_nand.c for U-Boot]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Boris Brezillon
4d75596e6d mtd: nand: Drop unused cached programming support
Cached programming is always skipped, so drop the associated code until
we decide to really support it.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 0b4773fd1649e0d418275557723a7ef54f769dc9]
[masahiro: modify davinci_nand.c for U-Boot]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Marc Gonzalez
1fb87de83d mtd: nand: Support controllers with custom page
If your controller already sends the required NAND commands when
reading or writing a page, then the framework is not supposed to
send READ0 and SEQIN/PAGEPROG respectively.

Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 3371d663bb4579f1b2003a92162edd6d90edd089]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Boris Brezillon
6f84b26b53 mtd: nand: Add a few more timings to nand_sdr_timings
Add the tR_max, tBERS_max, tPROG_max and tCCS_min timings to the
nand_sdr_timings struct.
Assign default/safe values for the statically defined timings, and
extract them from the ONFI parameter table if the NAND is ONFI
compliant.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
[Linux commit: 204e7ecd47e26cc12d9e8e8a7e7a2eeb9573f0ba
 Fixup commit: 6d29231000bbe0fb9e4893a9c68151ffdd3b5469]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Boris Brezillon
3d841b3214 mtd: nand: Fix data interface configuration logic
When changing from one data interface setting to another, one has to
ensure a specific sequence which is described in the ONFI spec.

One of these constraints is that the CE line has go high after a reset
before a command can be sent with the new data interface setting, which
is not guaranteed by the current implementation.

Rework the nand_reset() function and all the call sites to make sure the
CE line is asserted and released when required.

Also make sure to actually apply the new data interface setting on the
first die.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fixes: d8e725dd8311 ("mtd: nand: automate NAND timings selection")
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
[Linux commit: 73f907fd5fa56b0066d199bdd7126bbd04f6cd7b]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Boris Brezillon
27c4792cd2 mtd: nand: automate NAND timings selection
The NAND framework provides several helpers to query timing modes supported
by a NAND chip, but this implies that all NAND controller drivers have
to implement the same timings selection dance. Also currently NAND
devices can be resetted at arbitrary places which also resets the timing
for ONFI chips to timing mode 0.

Provide a common logic to select the best timings based on ONFI or
->onfi_timing_mode_default information. Hook this into nand_reset()
to make sure the new timing is applied each time during a reset.

NAND controller willing to support timings adjustment should just
implement the ->setup_data_interface() method.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
[Linux commit: d8e725dd831186a3595036b2b1df9f68cbc6efa3]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Sascha Hauer
b893e83330 mtd: nand: Expose data interface for ONFI mode 0
The nand layer will need ONFI mode 0 to use it as timing mode
before and right after reset.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 6e1f9708dbf3c50a8da93c1952a01a7a2acb5e66]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Sascha Hauer
46deff57da mtd: nand: convert ONFI mode into data interface
struct nand_data_interface is the designated type to pass to
the NAND drivers to configure the timing. To simplify further
patches convert the onfi_sdr_timings array from type struct
nand_sdr_timings nand_data_interface.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: b1dd3ca203fccd111926c3f6ac59bf903ec62b05]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:58 +09:00
Sascha Hauer
1728eb577d mtd: nand: Create a NAND reset function
When NAND devices are resetted some initialization may have to be done,
like for example they have to be configured for the timing mode that
shall be used. To get a common place where this initialization can be
implemented create a nand_reset() function. This currently only issues
a NAND_CMD_RESET to the NAND device. The places issuing this command
manually are replaced with a call to nand_reset().

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 2f94abfe35b210e7711af9202a3dcfc9e779219a]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:57 +09:00
Boris Brezillon
19d30ded88 mtd: nand: Add an option to maximize the ECC strength
The generic NAND DT bindings allows one to tweak the ECC strength and
step size to their need. It can be used to lower the ECC strength to
match a bootloader/firmware config, but might also be used to get a better
reliability.

In the latter case, the user might want to use the maximum ECC strength
without having to explicitly calculate the exact value (this value not
only depends on the OOB size, but also on the NAND controller, and can
be tricky to extract).

Add a generic 'nand-ecc-maximize' DT property and the associated
NAND_ECC_MAXIMIZE flag, to let ECC controller drivers select the best
ECC strength and step-size on their own.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
[Linux commit: ba78ee00e1ff84de9b3ad33edbd3ec599099ee82]
[masahiro: of_property_read_bool -> fdt_getprop for U-Boot]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:57 +09:00
Masahiro Yamada
ed3986ca30 bitops: collect BIT macros to include/linux/bitops.h
Same macros are defined in various places.  Collect them into
include/linux/bitops.h like Linux.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29 00:28:57 +09:00
Jeff Westfahl
8000d6ea3f mtd: nand: zynq: Add a config option to use 1st stage bootloader timing
In legacy method, 1st stage bootloader was used to configure the HW
setting such as NAND timing. Hence, adding a config option in Zynq
NAND driver for the compatibility of device that using 1st stage
bootloder instead of U-boot SPL.

This commit is to add config option
CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS that allow NAND driver use
timing values set by the 1st stage bootloader, instead of the hard-coded
values in the Zynq NAND driver.

Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com>
Signed-off-by: Wilson Lee <wilson.lee@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Scott Wood <oss@buserror.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 15:53:07 +01:00
Tom Rini
39e709611d omap2: nand: Make NAND_OMAP_GPMC_PREFETCH default
This option provides better performance and should really always be
enabled.  Make this be default y.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2017-11-17 07:44:13 -05:00
Kurt Kanzenbach
99145c488f mtd: nand: fsl-ifc: fix support of multiple NAND devices
Currently the chipselect used to identify the corresponding NAND chip
is stored at the controller and only set during fsl_ifc_chip_init().
This way, only the last NAND chip is working, as the previous value
of cs_nand gets overwritten.

In order to solve this issue the chipselect is computed on demand by
evaluating the bank variable. Thus, the correct chipselect for each
NAND chip operation is used.

Tested on hardware with two NAND chips connected to the IFC
controller.

Signed-off-by: Kurt Kanzenbach <kurt@linutronix.de>
Acked-by: Scott Wood <oss@buserror.net>
[YS: reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-11-14 08:33:20 -08:00
Masahiro Yamada
166cae20dd mtd: replace MTDDEBUG() with pr_debug()
In old days, the MTD subsystem in Linux had debug facility like
DEBUG(MTD_DEBUG_LEVEL1, ...).

They were all replaced with pr_debug() until Linux 3.2.  See Linux
commit 289c05222172 ("mtd: replace DEBUG() with pr_debug()").

U-Boot still uses similar macros.  Covert all of them for easier sync.

Done with the help of Coccinelle.

The semantic patch I used is as follows:

// <smpl>
@@
expression e1, e2;
@@
-MTDDEBUG(e1, e2)
+pr_debug(e2)
@@
expression e1, e2;
@@
-MTDDEBUG(e1, e2,
+pr_debug(e2,
 ...)
// </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23 14:07:26 -04:00
Adam Ford
0a9ef45158 Convert CONFIG_NAND_OMAP_GPMC et al and CONFIG_NAND_MXC to Kconfig
This converts the following to Kconfig:
   CONFIG_NAND_MXC
   CONFIG_NAND_OMAP_GPMC
   CONFIG_NAND_OMAP_GPMC_PREFETCH
   CONFIG_NAND_OMAP_ELM
   CONFIG_SPL_NAND_AM33XX_BCH
   CONFIG_SPL_NAND_SIMPLE
   CONFIG_SYS_NAND_BUSWIDTH_16BIT

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
[trini: Finish migration of CONFIG_SPL_NAND_SIMPLE, fix some build issues,
        add CONFIG_NAND_MXC so we can do CONFIG_SYS_NAND_BUSWIDTH_16BIT]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-20 16:44:07 -04:00
Masahiro Yamada
a89b9bc095 mtd: nand: denali_dt: add clock support
Enable clock in the probe hook.  The clock rate will be necessary
when setup_data_interface hook is supported.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15 22:32:25 +09:00
Masahiro Yamada
fe3fddfad7 mtd: nand: do not check R/B# for CMD_SET_FEATURES in nand_command(_lp)
Set Features (0xEF) command toggles the R/B# pin after 4 sub feature
parameters are written.

Currently, nand_command(_lp) calls chip->dev_ready immediately after
the address cycle because NAND_CMD_SET_FEATURES falls into default:
label.  No wait is needed at this point.

If you see nand_onfi_set_features(), R/B# is already cared by the
chip->waitfunc call.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

[ Linux commit: c5d664aa5a4c4b257a54eb35045031630d105f49 ]
2017-10-15 22:32:10 +09:00
Masahiro Yamada
6f29c7a8f1 mtd: nand: do not check R/B# for CMD_READID in nand_command(_lp)
Read ID (0x90) command does not toggle the R/B# pin.  Without this
patch, NAND_CMD_READID falls into the default: label, then R/B# is
checked by chip->dev_ready().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

[ Linux commit: 3158fa0e739615769cc047d2428f30f4c3b6640e ]
2017-10-15 22:31:35 +09:00
Masahiro Yamada
9b643e312d treewide: replace with error() with pr_err()
U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:

  # define __compiletime_error(message) __attribute__((error(message)))

This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux.  (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)

Let's convert error() into now treewide-available pr_err().

Done with the help of Coccinelle, excluing tools/ directory.

The semantic patch I used is as follows:

// <smpl>
@@@@
-error
+pr_err
 (...)
// </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-04 11:59:44 -04:00
Masahiro Yamada
6c71b6f454 mtd: nand: denali: allow to override corrupted revision register
The Denali IP does not update the revision register properly.
Allow to override it with SoC data associated with compatible.

Linux had already finished big surgery of this driver, but I need
to prepare the NAND core before the full sync of the driver.
For now, I am fixing the most fatal problem on UniPhier platform.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-18 20:26:00 +09:00
Masahiro Yamada
1d9654dc43 mtd: nand: denali_dt: add a DT driver
A patch for NAND uclass support was proposed about half a year ago:
https://patchwork.ozlabs.org/patch/722282/

It was not merged and I do not see on-going work for this.

Without DM-based probing, we need to set up pinctrl etc. in an ad-hoc
way and give lots of crappy CONFIG options for base addresses and
properties, which are supposed to be specified by DT.  This is painful.

This commit just provides a probe hook to retrieve "reg" from DT and
allocate private data in a DM manner.  This DT driver is not essentially
a NAND driver, in fact it is (ab)using UCLASS_MISC.  Once UCLASS_NAND is
supported, it would be possible to migrate to it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Adam Ford
5bbc265bec Convert CONFIG_NAND to Kconfig
This converts the following to Kconfig:
   CONFIG_NAND

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Sync up a few more, add imply's]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-12 09:18:47 -04:00
Tom Rini
8f1a80e99e configs: Migrate CMD_NAND*
Migrate all remaining instances of CMD_NAND, CMD_NAND_TRIMFFS
CMD_NAND_LOCK_UNLOCK and CMD_NAND_TORTURE from the headers into the
defconfig files.

Tested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-31 12:21:40 -04:00
Tom Rini
39632b4a01 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2017-07-18 08:42:48 -04:00
Stefano Babic
552a848e4f imx: reorganize IMX code as other SOCs
Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/<SOC>.

This change is also coherent with the structure in kernel.

Signed-off-by: Stefano Babic <sbabic@denx.de>

CC: Fabio Estevam <fabio.estevam@nxp.com>
CC: Akshay Bhat <akshaybhat@timesys.com>
CC: Ken Lin <Ken.Lin@advantech.com.tw>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Heiko Schocher <hs@denx.de>
CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com>
CC: Christian Gmeiner <christian.gmeiner@gmail.com>
CC: Stefan Roese <sr@denx.de>
CC: Patrick Bruenn <p.bruenn@beckhoff.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Nikita Kiryanov <nikita@compulab.co.il>
CC: Otavio Salvador <otavio@ossystems.com.br>
CC: "Eric Bénard" <eric@eukrea.com>
CC: Jagan Teki <jagan@amarulasolutions.com>
CC: Ye Li <ye.li@nxp.com>
CC: Peng Fan <peng.fan@nxp.com>
CC: Adrian Alonso <adrian.alonso@nxp.com>
CC: Alison Wang <b18965@freescale.com>
CC: Tim Harvey <tharvey@gateworks.com>
CC: Martin Donnelly <martin.donnelly@ge.com>
CC: Marcin Niestroj <m.niestroj@grinn-global.com>
CC: Lukasz Majewski <lukma@denx.de>
CC: Adam Ford <aford173@gmail.com>
CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr>
CC: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Soeren Moch <smoch@web.de>
CC: Richard Hu <richard.hu@technexion.com>
CC: Wig Cheng <wig.cheng@technexion.com>
CC: Vanessa Maegima <vanessa.maegima@nxp.com>
CC: Max Krummenacher <max.krummenacher@toradex.com>
CC: Stefan Agner <stefan.agner@toradex.com>
CC: Markus Niebel <Markus.Niebel@tq-group.com>
CC: Breno Lima <breno.lima@nxp.com>
CC: Francesco Montefoschi <francesco.montefoschi@udoo.org>
CC: Jaehoon Chung <jh80.chung@samsung.com>
CC: Scott Wood <oss@buserror.net>
CC: Joe Hershberger <joe.hershberger@ni.com>
CC: Anatolij Gustschin <agust@denx.de>
CC: Simon Glass <sjg@chromium.org>
CC: "Andrew F. Davis" <afd@ti.com>
CC: "Łukasz Majewski" <l.majewski@samsung.com>
CC: Patrice Chotard <patrice.chotard@st.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Hans de Goede <hdegoede@redhat.com>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
CC: Stephen Warren <swarren@nvidia.com>
CC: Andre Przywara <andre.przywara@arm.com>
CC: "Álvaro Fernández Rojas" <noltari@gmail.com>
CC: York Sun <york.sun@nxp.com>
CC: Xiaoliang Yang <xiaoliang.yang@nxp.com>
CC: Chen-Yu Tsai <wens@csie.org>
CC: George McCollister <george.mccollister@gmail.com>
CC: Sven Ebenfeld <sven.ebenfeld@gmail.com>
CC: Filip Brozovic <fbrozovic@gmail.com>
CC: Petr Kulhavy <brain@jikos.cz>
CC: Eric Nelson <eric@nelint.com>
CC: Bai Ping <ping.bai@nxp.com>
CC: Anson Huang <Anson.Huang@nxp.com>
CC: Sanchayan Maity <maitysanchayan@gmail.com>
CC: Lokesh Vutla <lokeshvutla@ti.com>
CC: Patrick Delaunay <patrick.delaunay@st.com>
CC: Gary Bisson <gary.bisson@boundarydevices.com>
CC: Alexander Graf <agraf@suse.de>
CC: u-boot@lists.denx.de
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-07-12 10:17:44 +02:00
Fabio Estevam
a1d1fdc920 mx6: soc: Move mxs_dma_init() into the mxs nand driver
Currently the following build error is seen when a board using MMC SPL
is built and the MXS nand driver is also selected:

arch/arm/cpu/armv7/built-in.o: In function `arch_cpu_init':
arch/arm/cpu/armv7/mx6/soc.c:432: undefined reference to 'mxs_dma_init'

On mx6 the only user of mxs_dma_init() is the mxs nand driver, so
move it there.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-07-12 09:44:22 +02:00
Grygorii Strashko
7a9dfe75cf mtd: nand: make nand_info array static
Make make nand_info array static, since all direct users of nand_info array
have been converted to use get_nand_dev_by_index() API.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:54 -04:00
Grygorii Strashko
88b81bf792 mtd: nand: drv: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:49 -04:00
Mugunthan V N
ad92dff28c cmd: nand: abstract global variable usage for dm conversion
nand_info is used all over the file so abstract it with
get_nand_dev_by_index() which will help for DM conversion.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:44 -04:00
Heiko Schocher
064b55cfcb powerpc, 5xxx, 512x: remove support for mpc5xxx and mpc512x
There was for long time no activity in the mpx5xxx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in mpc5xxx,
so remove it.

Signed-off-by: Heiko Schocher <hs@denx.de>
2017-06-16 10:14:55 -04:00
Simon Glass
5644aeea8e samsung: nand: Drop s3c2410_nand driver
This is not used anymore. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05 11:02:31 -04:00
Simon Glass
150c5afe5b dm: gpio: Add live tree support
Add support for requesting GPIOs with a live device tree.

This involves adjusting the function signature for the legacy function
gpio_request_by_name_nodev(), so fix up all callers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes to stm32f746-disco.c:
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-01 07:03:10 -06:00
Konstantin Porotchkin
1d45329ada fix: nand: pxa3xx: Remove hardcode values from the driver
Obtain NAND controller setup parameters from the device
tree instead of using hardcoded values.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Scott Wood <oss@buserror.net>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-05-09 13:38:18 +02:00
Ladislav Michl
18cae43b62 mtd: nand: Consolidate nand spl loaders implementation
nand_spl_load_image implementation was copied over into three
different drivers and now with nand_spl_read_block used for
ubispl situation gets even worse. For now use least intrusive
solution and #include the same implementation to nand drivers.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08 11:57:26 -04:00
Masahiro Yamada
90d6500c0f drivers: remove Blackfin specific drivers
These drivers have no user since commit ea3310e8aa ("Blackfin:
Remove").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-04-18 10:29:14 -04:00
Wenyou Yang
0de077df38 mtd: nand: atmel: use another functions to set gpio value
Because there isn't the implementation of gpio_set/get_value()
and gpio_set/get_value() after the at91 gpio driver is converted
to support the driver model, use at91_set_gpio_value() and
at91_get_gpio_value()

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-13 14:44:49 -06:00
Cooper Jr., Franklin
6e1eb089be mtd: nand: am335x_spl_bch: Incorporate tWB delay in nand_command function
Various commands to NAND flash results in the NAND flash becoming busy.
For those commands the SoC should wait until the NAND indicates it is
no longer busy before sending further commands. However, there is a delay
between the time the SoC sends its last command and when the NAND flash
sets its Ready/Busy Pin. This delay (tWB) must be respected or the SoC may
falsely assume the flash is ready when in reality it just hasn't had enough
time to indicate that it is busy.

Properly delaying by tWB is already done for nand_command/nand_command_lp
in nand_base.c including the version of it in the Linux kernel. Therefore,
this patch brings the handling of tWB delay inline to nand_base.c

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
[trini: Reformat comments slightly]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-08 21:34:50 -04:00
Maxime Ripard
ff93c28265 nand: sunxi: Add options for the SPL NAND configuration
The SPL image needs to be built with a different ECC configuration than the
U-Boot binary.

Add Kconfig options with defaults to provide a value that should work for
anyone, but is still configurable if needs be.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Scott Wood <oss@buserror.net>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-07 11:23:46 +05:30
Maxime Ripard
adc706b2fe mtd: sunxi: Change U-Boot offset
The default U-Boot offset for the Allwinner SoCs was set to 32kB.

This was probably to try to maintain some compatibility with the current
image that we build for the MMC where the U-Boot binary is also located at
a 32kB offset.

However, this causes a number of issues. The first one is that it prevents
us from using a backup SPL entirely, which is troublesome in case where the
first would be corrupt (especially on MLC which have a higher number of
bitflips).

We also cannot use the original MMC image on the NAND, because we need to
prepare the SPL image to include the ECCs and randomizer settings, which
reduces the interest of setting it at that particular offset.

It also prevents us from upgrading and flashing the U-Boot and SPLs
independantly, since it's very likely that it will fall in the same erase
block.

Since that default wasn't used by any board, change it for 8MB, which will
be in an erase block of its own, all the erase blocks being multiple of
two. The highest erase block size we encountered is 4MB, which means that
in this particular setup, the first and second erase blocks will be for the
SPL and its backup, and the third for U-Boot.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-07 11:23:46 +05:30
Maxime Ripard
5fe4c9f4d2 mtd: sunxi: Select the U-Boot location config option
We'll need that symbol so that the default offset are defined

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-07 11:23:45 +05:30
Maxime Ripard
ea3f750c73 nand: sunxi: Fix modulo by zero error
When trying to autodetect the ECC and randomization configurations, the
driver starts with a randomization disabled and no seeds.

In this case, the number of seeds is obviously 0, and the randomize boolean
is set to false.

However, the logic that retrieves the seed for a given page offset will
blindly use the number of seeds, without testing if the randomization is
enabled, basically doing a modulo by 0.

As it turns out, the libgcc in the common toolchain returns 0 here, which
was our expected value in such a case, and why we would not detect it.
However, U-Boot's libgcc will for some reason return from the function
instead, resulting in an error to load the U-Boot binary in the SPL.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Scott Wood <oss@buserror.net>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-07 11:23:45 +05:30
Tom Rini
ea3310e8aa Blackfin: Remove
The architecture is currently unmaintained, remove.

Cc: Benjamin Matthews <mben12@gmail.com>
Cc: Chong Huang <chuang@ucrobotics.com>
Cc: Dimitar Penev <dpn@switchfin.org>
Cc: Haitao Zhang <hzhang@ucrobotics.com>
Cc: I-SYST Micromodule <support@i-syst.com>
Cc: M.Hasewinkel (MHA) <info@ssv-embedded.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Martin Strubel <strubel@section5.ch>
Cc: Peter Meerwald <devel@bct-electronic.com>
Cc: Sonic Zhang <sonic.adi@gmail.com>
Cc: Valentin Yakovenkov <yakovenkov@niistt.ru>
Cc: Wojtek Skulski <info@skutek.com>
Cc: Wojtek Skulski <skulski@pas.rochester.edu>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-05 13:52:01 -04:00
Hou Zhiqiang
203db38a94 mtd: nand: remove nand size print from nand_init function
Add nand_size() function to move the nand size print into initr_nand().
Remove nand size print from nand_init() to allow other function to call
nand_init() without printing nand size.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 10:39:33 -07:00
Hou Zhiqiang
d72158c045 mtd: nand: add initialization flag
Add initialization flag to avoid initializing NAND Flash multiple
times, otherwise it will calculate a wrong total size.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 10:38:37 -07:00
Andrey Yurovsky
f78038dc0d mtd: nand: build MXS driver for MX7 as well
The i.MX7 has the same GPMI controller as i.MX6 and is covered by the MXS
driver. Tell Kconfig that we can use this driver on the MX7 platform (the MXS
driver already has the few i.MX7-specific changes needed for basic operation
and the board itself sets the pinmux correctly).

Tested on i.MX7D with the Sabre board and a NAND Flash soldered to U12.

Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
2017-02-19 16:20:28 +01:00
Ladislav Michl
6fe7fe12cc omap-gpmc: use SECTOR_BYTES instead of hardcoded value
Replace hardcoded value with defined constant SECTOR_BYTES.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-01-14 16:47:18 -05:00
Jagan Teki
101000b771 mtd: nand: mxs_nand_spl: Fix to remove twise 'NAND' print
SPL from nand will print 'NAND' in boot_from_devices based on
the image_loader name, remove the extra 'NAND ' in mxs_nand_spl driver.

Original behaviour:
-------------------
U-Boot SPL 2017.01-rc2-gf84dd8b (Jan 02 2017 - 22:24:19)
Trying to boot from NANDNAND : 512 MiB

After the fix:
-------------
U-Boot SPL 2017.01-rc2-gf84dd8b-dirty (Jan 02 2017 - 23:17:00)
Trying to boot from NAND: 512 MiB

Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:56:44 +01:00
Fabien Parent
cf07d39fb1 NAND: davinci: add support for NAND chips with 16 bits bus
The OMAPL138-LCD board uses a NAND chip with a 16 bits bus. Add
support into the davinci driver for 16 bit bus NAND chips.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-12-03 13:21:15 -05:00
Boris Brezillon
11777a5ea7 mtd: nand: add support for the TC58NVG2S0H chip
Add the description of the Toshiba TC58NVG2S0H SLC nand to the nand_ids
table so we can use the NAND ECC infos and the ONFI timings.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-11-28 15:10:30 -05:00
Siva Durga Prasad Paladugu
02bcff2c56 nand: arasan_nfc: Clear ecc on bit while sending read command
Clear ecc ON bit while sending read command as all types
of read command(like reading spare) doesnt need ECC to be
enabled. It has been anyway taken care in other places
whereever required using arasan_nand_enable_ecc().

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:27:57 +01:00
Siva Durga Prasad Paladugu
ae798d2e7d mtd: nand: zynq_nand: Add nand driver support for zynq
Add nand flash controller driver support for zynq SoC.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:27:50 +01:00
Jagan Teki
df10a850c5 mtd: nand: Kconfig: Add NAND_MXS entry
Added kconfig for NAND_MXS driver.

Cc: Scott Wood <oss@buserror.net>
Cc: Simon Glass <sjg@chromium.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26 16:53:16 +02:00
Masahiro Yamada
1221ce459d treewide: replace #include <asm/errno.h> with <linux/errno.h>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content.  (both just wrap <asm-generic/errno.h>)

Replace all include directives for <asm/errno.h> with <linux/errno.h>.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-23 17:55:42 -04:00
Tom Rini
16f416661e Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-09-09 09:45:32 -04:00
Stefan Agner
2a83c95fdb mtd: nand: mxs: fix cache alignment for cache lines >32
Currently the command buffer gets allocated with a size of 32 bytes.
This causes warning messages on systems with cache lines bigger than
32 bytes:
CACHE: Misaligned operation at range [9df17a00, 9df17a20]

Define command buffer to be at least 32 bytes, but more if cache
line is bigger.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-09-06 18:22:48 +02:00
Scott Wood
8b7d51249e nand: Fix some more NULL name tests
Now that nand_info[] is an array of pointers we need to test the
pointer itself rather than using name as a proxy for NULLness.

Fixes: b616d9b0a7 ("nand: Embed mtd_info in struct nand_chip")
Signed-off-by: Scott Wood <oss@buserror.net>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Tony Lindgren <tony@atomide.com>
Acked-by: Tony Lindgren <tony@atomide.com>
2016-09-01 20:08:48 -05:00
Chris Packham
91395b5d4e mtd: nand: pxa3xx: use nand_set_controller_data
In commit 17cb4b8f32 ("mtd: nand: Add+use mtd_to/from_nand and
nand_get/set_controller_data") the assignment of mtd->priv was removed
but was not replaced. This adds the required nand_set_controller_data()
call.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2016-09-01 17:30:11 -05:00
Hector Palacios
ebb7febc92 mtd: nand: fix bug writing 1 byte less than page size
nand_do_write_ops() determines if it is writing a partial page with the
formula:
	part_pagewr = (column || writelen < (mtd->writesize - 1))

When 'writelen' is exactly 1 byte less than the NAND page size the formula
equates to zero, so the code doesn't process it as a partial write, although
it should.
As a consequence the function remains in the while(1) loop with 'writelen'
becoming 0xffffffff and iterating until the watchdog timeout triggers.

To reproduce the issue on a NAND with 2K page (0x800):
	=> nand erase.part <partition>
	=> nand write $loadaddr <partition> 7ff

Signed-off-by: Hector Palacios <hector.palacios@digi.com>
2016-07-24 20:36:29 -05:00
Boris Brezillon
cd7f5e1cdf mtd: nand: Add a full-id entry for the H27QCG8T2E5R‐BCF NAND
Add a full-id entry for the H27QCG8T2E5R‐BCF NAND.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2016-07-24 20:36:28 -05:00
Boris Brezillon
4ccae81cda mtd: nand: Add the sunxi NAND controller driver
We already have an SPL driver for the sunxi NAND controller, now add
the normal/standard one.

The source has been copied from Linux 4.6 with a few changes to make
it work in u-boot.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2016-07-24 20:36:28 -05:00
Brian Norris
42bd19ce6c mtd: nand: add common DT init code
These are already-documented common bindings for NAND chips. Let's
handle them in nand_base.

If NAND controller drivers need to act on this data before bringing up
the NAND chip (e.g., fill out ECC callback functions, change HW modes,
etc.), then they can do so between calling nand_scan_ident() and
nand_scan_tail().

The original commit has been slightly reworked to use the fdtdec_xxx()
helpers (instead of the of_xxxx() ones).

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2016-07-24 20:36:28 -05:00
Ladislav Michl
0568dd0663 armv7: make gpmc_cfg const
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
[trini: Adapt am33xx, duovero, omap_zoom1]
Signed-off-by: Tom Rini <trini@konsulko.com>

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-07-22 14:46:00 -04:00
Thomas Gleixner
e1a89e9358 nand_spl_simple: Add a simple NAND read function
To support UBI in SPL we need a simple NAND read function. Add one to
nand_spl_simple and keep it as simple as it goes.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Acked-by: Scott Wood <oss@buserror.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2016-07-22 09:52:59 -04:00
Sumit Garg
8f01397ba7 powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPL
As part of Chain of Trust for Secure boot, the SPL U-Boot will validate
the next level U-boot image. Add a new function spl_validate_uboot to
perform the validation.

Enable hardware crypto operations in SPL using SEC block.
In case of Secure Boot, PAMU is not bypassed. For allowing SEC block
access to CPC configured as SRAM, configure PAMU.

Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-21 11:09:23 -07:00
Robert P. J. Day
62a3b7dd08 Various, unrelated tree-wide typo fixes.
Fix a number of typos, including:

     * "compatble" -> "compatible"
     * "eanbeld" -> "enabled"
     * "envrionment" -> "environment"
     * "FTD" -> "FDT" (for "flattened device tree")
     * "ommitted" -> "omitted"
     * "overriden" -> "overridden"
     * "partiton" -> "partition"
     * "propogate" -> "propagate"
     * "resourse" -> "resource"
     * "rest in piece" -> "rest in peace"
     * "suport" -> "support"
     * "varible" -> "variable"

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2016-07-16 09:43:12 -04:00
Andre Renaud
62f8183f6a mtd: nand: Drop a blank line in nand_wait()
This empty line should not be there. Remove it.
Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2016-06-24 17:23:14 -04:00
Tom Rini
2313d48445 Merge git://git.denx.de/u-boot-nand-flash 2016-06-20 05:15:52 -04:00
Boris Brezillon
30780f9483 mtd: nand: Patch remaining places where nand_to_mtd() should be used
Some drivers are still directly accessing the chip->mtd field. Patch
them to use nand_to_mtd() instead.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-06-19 19:28:38 -05:00
Max Krummenacher
e1c29086d5 nand: nand torture: follow sync with linux v4.6
follow parameter name change (nand to mtd) to fix compiler error.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2016-06-19 19:19:30 -05:00
Boris Brezillon
7748b41482 spl: nand: sunxi: add support for NAND config auto-detection
NAND chips are supposed to expose their capabilities through advanced
mechanisms like READID, ONFI or JEDEC parameter tables. While those
methods are appropriate for the bootloader itself, it's way to
complicated and takes too much space to fit in the SPL.

Replace those mechanisms by a dumb 'trial and error' mechanism.

With this new approach we can get rid of the fixed config list that was
used in the sunxi NAND SPL driver.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2016-06-19 19:12:02 -05:00
Boris Brezillon
4e7d1b3beb spl: nand: sunxi: split 'load page' and 'read page' logic
Split the 'load page' and 'read page' logic in 2 different functions so
we can later load the page and test different ECC configs without the
penalty of reloading the same page in the NAND cache.

We also move common setup to a dedicated function (nand_apply_config()) to
avoid rewriting the same values in NFC registers each time we read a page.

These new functions are passed a pointer to an nfc_config struct to limit
the number of parameters.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2016-06-19 19:12:01 -05:00
Boris Brezillon
bb9783b66b spl: nand: sunxi: rework status polling loop
check_value_xxx() helpers are using a 1ms delay between each test, which
can be quite long for some operations (like a page read on an SLC NAND).
Since we don't have anything to do but to poll this register, reduce the
delay between each test to 1us.

While we're at it, rename the max_number_of_retries parameters and the
MAX_RETRIES macro into timeout_us and DEFAULT_TIMEOUT_US to reflect that
we're actually waiting a given amount of time and not only a number of
retries.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2016-06-19 19:12:01 -05:00
Boris Brezillon
fa30115878 spl: nand: sunxi: stop guessing the redundant u-boot offset
Use CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND value instead of trying to guess
where the redundant u-boot image is based on simple (and most of the time
erroneous) heuristics.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

# Conflicts:
#	drivers/mtd/nand/sunxi_nand_spl.c
2016-06-19 19:12:01 -05:00
Boris Brezillon
80ef700f8d spl: nand: support redundant u-boot image
On modern NAND it's more than recommended to have a backup copy of the
u-boot binary to recover from corruption: bitflips are quite common on
MLC NANDs, and the read-disturbance will corrupt your u-boot partitition
more quickly than what you would see on an SLC NAND.

Add an extra Kconfig option to specify the offset of the redundant u-boot
image.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
[scottwood: added ifdef to fix build break]
Signed-off-by: Scott Wood <oss@buserror.net>
2016-06-19 19:11:57 -05:00
Boris Brezillon
494e108651 spl: nand: rework SYS_NAND_U_BOOT_OFFS Kconfig option dependency
The SYS_NAND_U_BOOT_OFFS is quite generic, but the Kconfig entry is forced
to explicitly depend on platforms that are not already defining it in their
include/configs/<board>.h header.

Add the SYS_NAND_U_BOOT_LOCATIONS option, make the SYS_NAND_U_BOOT_OFFS
depends on it, remove the dependency on NAND_SUNXI and make it dependent
on SPL selection.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2016-06-19 19:11:48 -05:00
Boris Brezillon
c4adf9db5d spl: nand: sunxi: remove support for so-called 'syndrome' mode
The sunxi SPL NAND controller driver supports use 'BootROM'-like configs,
that is, configs where the ECC bytes and real data are interleaved in the
page instead of putting ECC bytes in the OOB area.

Doing that has several drawbacks:
- since you're interleaving data and ECC bytes you can't use the whole page
  otherwise you might override the bad block marker with non-FF bytes.
- to solve the bad block marker problem, the ROM code supports partially
  using the page, but this introduces a huge penalty both in term of read
  speed and NAND memory usage. While this is fine for rather small
  binaries(like the SPL one which is at maximum 24KB large), it becomes
  non-negligible for the bootloader image (several hundred of KB).
- auto-detection of the page size is not reliable (this is in my opinion
  the biggest problem). If you get the page size wrong, you'll end up
  reading data at a different offset than what was specified by the caller
  and the reading may succeed (if valid data were written at this address).

For all those reasons I think it's wiser to completely remove support for
'syndrome' configs. If we ever need to support it again, then I'd recommend
specifying all the config parameters through Kconfig options.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2016-06-19 18:52:35 -05:00
Tom Rini
fd9102dafe Merge branch 'master' of git://git.denx.de/u-boot-atmel 2016-06-13 08:50:58 -04:00
Andre Renaud
65319f15ca at91: nand: Set up the ECC strength correctly
This needs to be set to avoid a fatal error when ECC is used.

Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2016-06-12 23:49:38 +02:00
Andre Renaud
5a9ae33316 at91: Correct NAND ECC register access
This uses the wrote base register value. Fix it.

Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2016-06-12 23:49:38 +02:00
Tom Rini
3fc304b8d7 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-06-12 12:51:34 -04:00
Heiko Schocher
3a504d9639 mtd: nand: omap: allow to switch to BCH16
support in omap_nand_switch_ecc() also an eccstrength
from 16.

Signed-off-by: Heiko Schocher <hs@denx.de>
2016-06-09 13:53:12 -04:00
Heiko Schocher
5d29e27eb9 nand: add nand mtd concat support
add for nand devices mtd concat support. Generic MTD concat
support is already ported to mainline, and used in the cfi_mtd
driver. This patch adds it similiar for nand devices.

Signed-off-by: Heiko Schocher <hs@denx.de>
2016-06-09 13:53:12 -04:00
Max Krummenacher
667067faa1 nand: fix nand torture to use changed mtd api
The mtd subsystem deprecated and renamed the direct use of the mtd_info
struct's functionpointers. Instead the corresponding mtd_xxx function
should be used.

See also:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=3c3c10bba1e4ccb75b41442e45c1a072f6cded19

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2016-06-03 20:29:05 -05:00
Scott Wood
ceee07b658 mtd: nand: Sync with Linux v4.6
Updates the NAND code to match Linux v4.6.  The previous sync was from
Linux v4.1 in commit d3963721d9.

Note that none of the individual NAND drivers tracked Linux closely
enough to be synced themselves, other than manually applying a few
cross-tree changes.

Signed-off-by: Scott Wood <oss@buserror.net>
Tested-by: Heiko Schocher <hs@denx.de>
2016-06-03 20:27:48 -05:00
Scott Wood
81c772521f mtd: nand: Add page argument to write_page() etc.
This change is part of the Linux 4.6 sync.  It is being done before the
main sync patch in order to make it easier to address the issue across
all NAND drivers (many/most of which do not closely track their Linux
counterparts) separately from other merge issues.

Signed-off-by: Scott Wood <oss@buserror.net>
2016-06-03 20:27:48 -05:00
Scott Wood
17cb4b8f32 mtd: nand: Add+use mtd_to/from_nand and nand_get/set_controller_data
These functions are part of the Linux 4.6 sync.  They are being added
before the main sync patch in order to make it easier to address the
issue across all NAND drivers (many/most of which do not closely track
their Linux counterparts) separately from other merge issues.

Signed-off-by: Scott Wood <oss@buserror.net>
2016-06-03 20:27:48 -05:00
Scott Wood
b616d9b0a7 nand: Embed mtd_info in struct nand_chip
nand_info[] is now an array of pointers, with the actual mtd_info
instance embedded in struct nand_chip.

This is in preparation for syncing the NAND code with Linux 4.6,
which makes the same change to struct nand_chip.  It's in a separate
commit due to the large amount of changes required to accommodate the
change to nand_info[].

Signed-off-by: Scott Wood <oss@buserror.net>
2016-06-03 20:27:48 -05:00
Scott Wood
151c06ec61 mtd: nand: Remove nand_info_t typedef
This typedef serves no purpose other than causing confusion with
struct nand_chip.

Signed-off-by: Scott Wood <oss@buserror.net>
2016-06-03 20:27:48 -05:00
Scott Wood
ea7d1eec66 mtd: nand: Remove docg4 driver and palmtreo680 flashing tool
Commit ad4f54ea86 ("arm: Remove palmtreo680 board") removed the only
user of the docg4 driver and the palmtreo680 image flashing tool.  This
patch removes them.

Signed-off-by: Scott Wood <oss@buserror.net>
Cc: Mike Dunn <mikedunn@newsguy.com>
Cc: Simon Glass <sjg@chromium.org>
2016-06-03 20:27:48 -05:00
Marek Vasut
5d74e3a6f1 mtd: nand: Remove jz4740 driver
This driver is not used by anyone, remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Scott Wood <oss@buserror.net>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-06-03 20:27:48 -05:00
Siva Durga Prasad Paladugu
a39d14406a mtd: nand: arasan_nfc: Correct nand ecc initialization
Correct the nand ecc initialization code
This fixes the issue of incorrect nand ecc
init if no device is found in ecc_matrix then
it endsup ecc init with junk initialization
instead of the most suited one.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
2016-06-03 20:27:48 -05:00
Lokesh Vutla
0985294604 mtd: nand: am335x: spl: Fix copying of image
When offset is not aligned to page address, it is possible that extra offset
will be read from nand. Adjust the image such that first byte of the image
is at load address after the first page is read.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-05-27 15:41:41 -04:00
Peng Fan
9aa550d2e8 mtd: nand: mxs: use simpler runtime cpu dection macros
Use simpler runtime cpu dection macros.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Scott Wood <oss@buserror.net>
2016-05-24 14:59:57 +02:00
Vagrant Cascadian
eae4b2b67b Fix spelling of "occurred".
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-02 18:37:09 -04:00
Purna Chandra Mandal
6d9481047e drivers: remove writes{b,w,l,q} and reads{b,w,l,q}.
Definition of writes{bwlq}, reads{bwlq} are now added into arch specific
asm/io.h. So removing them from driver to fix re-definition error

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
2016-04-10 17:18:41 +02:00
Chris Packham
46a16bd895 kirkwood_nand: claim MPP pins on the fly
Claim the MPP pins for the NAND flash controller only when it's actually
being used. This allows the pins to be shared with the SPI interface
which already supports an equivalent on-access MPP reconfiguration.

Reviewed-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Scott Wood <oss@buserror.net>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-04-06 15:40:33 +02:00
Graham Moore
15305c2f03 mtd: nand: denali: max_banks calculation changed in revision 5.1
Read Denali hardware revision number and use it to
calculate max_banks,  The encoding of max_banks changed
in Denali revision 5.1.

[ Linux commit : 271707b1d817f5104e02b2bd1bab43f0c8759418 ]

Signed-off-by: Graham Moore <grmoore@opensource.altera.com>
[Brian: parentheses around macro arg]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
[Masahiro: import from Linux and adjust ioread32() to readl() ]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-01 00:16:55 +09:00
Masahiro Yamada
73b5b27b7a mtd: denali: fix warning when compiled for 64bit system
The 64-bit compiler (ex. aarch64) emits "warning: cast from pointer
to integer of different size".

Make it work with 64bit DMA address while I am here.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-24 01:36:49 +09:00
Siva Durga Prasad Paladugu
e4b40e921d arasan: nfc: Add initial nand driver support for arasan
Added initial nand driver support for arasan nand flash
controller.This supports nand erase,nand read, nand write
This uses the hardware ECC for read and write operations
ZynqMP uses this  driver.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
[scottwood: Fix checkpatch warnings]
Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-12 17:27:41 -06:00
Siva Durga Prasad Paladugu
78cb965af0 zynqmp: nand: Add Nand driver support for zynqmp
Add nand driver support for zynqmp. The Nand
controller used in ZynqMP is Arasan Nand Flash
controller.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
[scottwood: Fix checkpatch warning]
Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-12 17:27:28 -06:00
Kevin Smith
065a373d93 mtd: pxa3xx_nand: Don't alloc unneeded memory
The allocation size is reduced from what was introduced from the
Linux kernel, as U-boot uses the statically allocated nand_info
instead of needing to dynamically allocate an mtd_info instance.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Scott Wood <scottwood@freescale.com>
2016-02-12 17:13:50 -06:00
Kevin Smith
84caff35df mtd: pxa3xx_nand: Correct offset calculation
Correct some pointer math in initialization.  An offset was added
to a struct-typed pointer instead of one casted to a byte-size,
resulting in a much larger offset than intended.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Scott Wood <scottwood@freescale.com>
2016-02-12 17:13:47 -06:00
Kevin Smith
b7d3e4a635 mtd: pxa3xx_nand: Correct null dereference
Correct a null pointer dereference in board_nand_init().  Zeroed
memory was allocated, then immediately dereferenced.  The
dereference is completely removed, since this pointer is later
initialized in alloc_nand_resources.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Scott Wood <scottwood@freescale.com>
2016-02-12 17:13:42 -06:00
Peng Fan
549d7c0e09 nand: mxs: fix error handling for mxs_nand_init
Fix error handling for mxs_nand_init.

The original error handling is wrong for err2 and err1.
Should first free desc[x], then free desc.

This patch also correctly handle err3, should use
MXS_DMA_CHANNEL_AHB_APBH_GPMI0 as the check point.

Cc: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <Fabio.Estevam@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2016-02-12 17:10:15 -06:00
Bin Meng
a187559e3d Use correct spelling of "U-Boot"
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-02-06 12:00:59 +01:00
Josh Wu
258b21fc69 atmel_nand: Add 32 bit ecc support for sama5d2 chip
Also if minimum ecc requirment is bigger then what we support, then just
use our maxium pmecc support.
But it is not safe, so we'll output a warning about this.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-02 11:49:11 +01:00
Josh Wu
fa651f5d53 atmel_nand_ecc: update pmecc registers according to sama5d2 chip
1. add the pmecc register mapping for sama5d2.
2. add the pmecc error location register mapping for sama5d2.
3. add some new field that is different from old ip.
4. add sama5d2 pmecc ip version number.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-02 11:49:10 +01:00
Josh Wu
422b49e289 atmel_nand: use the definition: PMECC_OOB_RESERVED_BYTES instead magic number
As atmel_nand_ecc.h is sync with v4.1 kernel, which adds the
PMECC_OOB_RESERVED_BYTES. So use it in the driver.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2016-01-27 13:58:59 +01:00
Josh Wu
4c6a6ea3e1 atmel_nand: add '\n' in the end of error message for better display
Also align the open parenthesis.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-01-27 13:58:59 +01:00