Commit graph

17485 commits

Author SHA1 Message Date
Patrick Wildt
6a4b07e086 imx8m: fix rom version check to unbreak some B0 chips
Recently the version check was improved to be able to determine that
we're running on SoC revision 2.1.  A check for B0 was tightened so
that it now must equal 0x20 instead of being bigger than 0x20.  On
some B0 chips the value returned is 0x1020 instead of 0x20.  This
means even though it's B0, the check will fail and code relying on
the correct chip revision will make wrong decisions.  There is no
documentation of those bits, but it seems that NXP always uses a
byte to encode the revision.  Thus remove the upper bits to fix the
regression.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
2019-12-09 11:52:06 +01:00
Masahiro Yamada
90ab311a7c x86: simplify ljmp to 32-bit code
You can directly specify the label as the operand for ljmp.

This commit saves 4-byte code.

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed the gas warning]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-08 19:10:21 +08:00
Masahiro Yamada
0d915a9aa4 x86: use data32 directive instead of macro for operand-size prefix
This file defines 'a32' and 'o32' macros to avoid magic numbers
of operand/address-size prefixing.

GAS supports 'data32' and 'addr32' for that purpose.

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-08 19:10:12 +08:00
Tom Rini
bead4f2f2c Merge tag 'u-boot-rockchip-20191206' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- rockchip pwm driver update to support all the SoCs
- RK3308 GMAC and pinctrl support
- More UART interface support on PX30 and pmugrf reg fix
- Fixup on misc for eth_addr/serial#
- Other updates on variant SoCs
2019-12-06 10:35:18 -05:00
Marek Vasut
edaec53212 ARM: imx: vining2000: Repair PCIe support
Ever since the conversion to DM PCI, the board was missing the PCIe DT
nodes, hence the PCI did not really work. Fill in the DT nodes and add
missing PCIe device reset.

Moreover, bring the PCIe power domain up before booting Linux. This is
mandatory to keep old broken vendor kernels working, as they do not do
so and depend on the bootloader to bring the power domain up.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
2019-12-06 13:57:42 +01:00
Marek Vasut
7d84f4469f ARM: imx: vining2000: Convert to SPL framework
In preparation for use of DDR DRAM fine-tuning upon boot,
convert the board to SPL framework instead of using DCD
tables to bring up DRAM and pinmux.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
2019-12-06 13:57:42 +01:00
Marek Vasut
df1b721f60 ARM: mx6: pmu: Expose PMU LDO configuration interface
Make the PMU LDO configuration interface available to board code,
so that board code can reconfigure the internal LDOs of the SoC.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric@nelint.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Eric Nelson <eric@nelint.com>
2019-12-06 13:57:42 +01:00
Igor Opaniuk
c671d8af0b board: colibri_imx7: reserve DDR memory for Cortex-M4
i.MX 7's Cortex-M4 core can run from DDR and uses DDR memory for
the rpmsg communication. Both use cases need a fixed location of
memory reserved. For the rpmsg use case the reserved area needs
to be in sync with the kernel's hardcoded vring descriptor location.

Use the linux,usable-memory property to carve out 1MB of memory
in case the M4 core is running. Also make sure that the i.MX 7
specific rpmsg driver does not get loaded in case we do not carve
out memory.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-12-06 12:09:30 +01:00
Fabio Estevam
d396f1384c mx6: Allow configuring the NoC registers on i.MX6QP
The NoC registers on i.MX6QP needs to be configured, otherwise some
usecases in the kernel behave incorrectly, such as rotation and resize.

Currently the NoC registers are not configured in the kernel, so
configure them in U-Boot like it is done in the NXP U-Boot tree.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2019-12-06 12:09:25 +01:00
Fabio Estevam
2d4b87f867 mx7ulp: Sync the device tree related files
Sync the mx7ulp device tree related files with the one from
NXP U-Boot vendor tree (imx_v2019.04_4.19.35_1.0.0).

The mainline support for i.MX7ULP is very premature at this stage.

We should probably re-sync with mainline Linux dts when it gets
in better shape, but for now sync with the U-Boot vendor code.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-12-06 12:05:08 +01:00
Fabio Estevam
d136eb9bfe mx7ulp: scg: Remove unnused scg_a7_apll_init()
scg_a7_apll_init() is not called anywhere, so remove such dead code

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-12-06 12:05:08 +01:00
Fabio Estevam
0619af0942 mx7ulp: Remove the _RUN notation from the PMC1 LDOVL definitions
The LDOVL definitions is common to all the modes, not only RUN mode,
so in order to avoid confusion, remove the _RUN notation from the PMC1
LDOVL definitions.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-12-06 12:05:08 +01:00
Fabio Estevam
b8cabb0e3d mx7ulp: Introduce the CONFIG_LDO_ENABLED_MODE option
Introduce the CONFIG_LDO_ENABLED_MODE option so that i.MX7ULP boards
designed to operate with LDO enabled mode can work with 0.95V at LDO
output in RUN mode as per the datasheet.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-12-06 12:05:08 +01:00
Fabio Estevam
72a093a8ac mx7ulp: Print the LDO mode status
As per the i.MX7ULP datasheet, it can boot in LDO enabled mode
or LDO bypass mode.

Print the LDO mode status in the U-Boot log for convenience.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-12-06 12:05:08 +01:00
David Wu
e0e6c96a67 arm: rockchip: rk3308: Initialize the iomux configuration
When we want to use plus pinctrl feature, we need to enable
them at spl.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-06 00:06:23 +08:00
David Wu
4ee6d51c5a pwm: rk_pwm: Make PWM driver to support all Rockchip Socs
This PWM driver can be used to support pwm functions
for on all Rockchip Socs.

The previous chips than RK3288 did not support polarity,
and register layout was different from the RK3288 PWM.

The RK3288 keep the current functions.

RK3328 and the chips after it, which can support hardware lock,
configure duty, period and polarity at next same period, to
prevent the intermediate temporary state.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-06 00:06:23 +08:00
David Wu
aebd9eddb3 dts: rk3308: Enable ethernet function supported for Firefly ROC_RK3308_CC
The Firefly ROC_RK3308_CC use ref_clock of input mode,
and rmii pins of m1 group.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-06 00:06:23 +08:00
David Wu
982fab393d arm: dts: Add mac node for rk3308 at dtsi level
The rk3308 only support RMII mode, and if it is output clock
mode, better to use ref_clk pin with drive strength 12ma.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-06 00:06:23 +08:00
Heiko Stuebner
fd3a7ae8e6 rockchip: misc: protect serial# from getting overwritten
serial# is one of the vendor properties and thus protected from being
overwritten if already set. If env_set is called anyway this result in
some nasty warnings, so check for presence before trying that.

In the same direction check for the presence of cpuid# and compare it
to the actual hardware and emit a warning if they don't match.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-05 23:53:07 +08:00
Heiko Stuebner
d490fadc70 rockchip: misc: don't fail if eth_addr already set
rockchip_setup_macaddr() runs from an initcall, so returning an error
code will make that initcall fail thus breaking the boot process.

And if an ethernet address is already set this is definitly not a
cause for that, so just return success in that case.

Fixes: 0482538499 ("rockchip: rk3399: derive ethaddr from cpuid");
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-05 23:53:07 +08:00
Paul Kocialkowski
c541bfda2f rockchip: px30: Add support for using UART3 as debug UART
Some generic PX30 SoMs found in the wild use UART3 as their debug output
instead of UART2 (used for MMC) and UART5.

Make it possible to use UART3 as early debug output, with the associated
clock and pinmux configuration. Two sets of output pins are supported (M0/M1).

Future users should also note that the pinmux default in the dts is to use
the M1 pins while the Kconfig option takes M0 as a default.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
2019-12-05 23:53:07 +08:00
Paul Kocialkowski
ec4fafdf1f rockchip: px30: Rename CONFIG_DEBUG_UART2_CHANNEL to CONFIG_DEBUG_UART_CHANNEL
UART3 also has two sets of pins that can be selected.

Rename the config option to a common name, to allow it to be used for both
UART2 and UART3.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-05 23:53:07 +08:00
Paul Kocialkowski
b0c5e37d0e rockchip: px30: Fixup PMUGRF registers layout order
According to the PX30 TRM, the iomux registers come first, before the pull
and strength control registers.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
2019-12-05 23:53:07 +08:00
Andy Yan
afe18f205e rockchip: px5: enable spl-fifo-mode for emmc for px5-evb
We need load some parts of ATF to sram, but rockchip
dwmmc controllers can't do dma to non-ddr addresses
space, so set the mmc controller into fifo mode in spl.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-05 23:53:07 +08:00
Andy Yan
081a51c937 rockchip: rk3308: enable spl-fifo-mode for emmc
We need load some parts of ATF to sram, but rockchip
dwmmc controllers can't do dma to non-ddr addresses
space, so set the mmc controller into fifo mode in spl.

And show my best respect to Heiko's work for this solution.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-05 23:53:07 +08:00
Thomas Hebb
9f67b56772 Fix typo in macros, "FIRMEWARE" -> "FIRMWARE"
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
2019-12-05 10:28:39 -05:00
Miquel Raynal
eb446ef625 cmd: nand/sf: isolate legacy code
The 'sf' command is not supposed to rely on the MTD stack, but both
'sf' and 'nand' commands use helpers located in mtd_uboot.c. Despite
their location, these functions do not depend at all on the MTD
stack.

This file (drivers/mtd/mtd_uboot.c) is only compiled if CONFIG_MTD is
selected, which is inconsistent with the current situation. Solve this
by moving these three functions (which are only used by the above two
commands) out of mtd_uboot.c and put them in a C file only compiled
with cmd/sf.c and cmd/nand.c.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[trini: Don't export get_part function now]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-12-04 17:10:51 -05:00
Miquel Raynal
88718be300 mtd: rename CONFIG_NAND -> CONFIG_MTD_RAW_NAND
Add more clarity by changing the Kconfig entry name.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[trini: Re-run migration, update a few more cases]
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
2019-12-03 23:04:10 -05:00
mingming lee
abf2c68566 ARM: MediaTek: add basic support for MT8518 boards
This adds a general board file based on MT8518 SoCs from MediaTek.

Apart from the generic parts (cpu) we add some low level init codes
and initialize the early clocks.

This commit is adding the basic boot support for the MT8518 eMMC board.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
[trini: Migrate env location to defconfig, set ENV_IS_IN_MMC]
Signeed-off-by: Tom Rini <trini@konsulko.com>
2019-12-03 12:00:03 -05:00
mingming lee
485627dd5f pinctrl: add driver for MT8518
Add Pinctrl driver for MediaTek MT8518 SoC.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2019-12-03 08:44:14 -05:00
mingming lee
13e89d7522 ARM: MediaTek: Add support for MediaTek MT8518 SoC
Add support for MediaTek MT8518 SoC. This include the file
that will initialize the SoC after boot and its device tree.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2019-12-03 08:44:14 -05:00
Bartosz Golaszewski
598d9bccc5 board: omapl138_lcdk: add the mmc device to SPL
We don't have full device-tree support in SPL yet - add an appropriate
U_BOOT_DEVICE() to the board file.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-12-03 08:44:14 -05:00
Bartosz Golaszewski
6a97153cbf mmc: davinci: drop support for ti,dm6441-mmc
The DM family of DaVinci SoCs is no longer supported. Drop the
irrelevant code from the driver.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-12-03 08:44:13 -05:00
Giulio Benetti
1b3d24b735 armv7m: cache: add invalidate_icache_all() stub
This commit:
d409c96216
causes build failure with ICACHE enabled. This is due to missing
invalidate_icache_all() stub. Let's add empty invalidate_icache_all() in
the case where ICACHE is not enabled.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2019-12-03 08:43:24 -05:00
Thomas Hebb
32f2ca2a7e cosmetic: Fix spelling and whitespace errors
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
2019-12-03 08:43:23 -05:00
Tom Rini
a4ef0657e3 Merge branch '2019-12-02-master-imports'
- A large series of clean-ups to reduce common.h contents
2019-12-02 22:05:35 -05:00
Simon Glass
d67bdaa799 common: Move trap_init() out of common.h
Move this function into the init.h header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-12-02 18:25:25 -05:00
Simon Glass
5255932f01 common: Move some board functions out of common.h
A number of board function belong in init.h with the others. Move them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:21 -05:00
Simon Glass
67c4e9f815 common: Move board_get_usable_ram_top() out of common.h
Move this function into init.h which seems to be designed for this sort
of thing. Also update the header to declare struct global_data so that it
can be included without global_data.h being needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:04 -05:00
Simon Glass
288b29e44d common: Move command functions out of common.h
Move these functions into the command.h header file which is a better fit.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:02 -05:00
Simon Glass
36bf446b64 common: Move enable/disable_interrupts out of common.h
Move these two functions into the irq_funcs.h header file. Also move
interrupt_handler_t as this is used by the irq_install_handler() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:01 -05:00
Simon Glass
c30b7adbca common: Move interrupt functions into a new header
These functions do not use driver model but are fairly widely used in
U-Boot. But it is not clear that they will use driver model anytime soon,
so we don't want to label them as 'legacy'.

Move them to a new irq_func.h header file. Avoid the name 'irq.h' since it
is widely used in U-Boot already.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:00 -05:00
Simon Glass
9d3915b2df arm: powerpc: Tidy up code style for interrupt functions
Remove the unwanted space before the bracket.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:24:59 -05:00
Simon Glass
1eb69ae498 common: Move ARM cache operations out of common.h
These functions are CPU-related and do not use driver model. Move them to
cpu_func.h

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:24:58 -05:00
Simon Glass
3374d28b34 common: Drop checkicache() and checkdcache()
These are used by only one arch and only within a single file. Drop the
declarations from the common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:56 -05:00
Simon Glass
9edefc2776 common: Move some cache and MMU functions out of common.h
These functions belong in cpu_func.h. Another option would be cache.h
but that code uses driver model and we have not moved these cache
functions to use driver model. Since they are CPU-related it seems
reasonable to put them here.

Move them over.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:55 -05:00
Simon Glass
6cc915b5fb arm: powerpc: Tidy up code style for cache functions
Remove the unwanted space before the bracket.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:14 -05:00
Simon Glass
62270f4395 common: Move some SMP functions out of common.h
These functions belong in cpu_func.h so move them over.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:14 -05:00
Simon Glass
30c7c43473 common: Move checkcpu() out of common.h
This function belongs in cpu_func.h so move it over.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:14 -05:00
Simon Glass
b5981474f1 common: Move some CPU functions out of common.h
These functions belong in cpu_func.h since they do not use driver model.
Move them over. Don't bother adding comments since these functions should
be deleted.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:13 -05:00
Simon Glass
68a6aa85ec common: Move mii_init() function out of common.h
This function belongs in mii.h so move it over.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:13 -05:00
Simon Glass
1045315df0 common: Move get_ticks() function out of common.h
This function belongs in time.h so move it over and add a comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:13 -05:00
Simon Glass
e3107d159c arm: pxa: Drop pxa_wait_ticks()
This function has a similar name to the common wait_ticks(). It is only
used in one place and seems small enough to drop.

Inline it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:11 -05:00
Simon Glass
6887c5bed9 common: Move some time functions out of common.h
These functions belong in time.h so move them over and add comments.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:11 -05:00
Simon Glass
b03e0510d7 common: Move serial functions out of common.h
These functions belong in serial.h so move them over.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:11 -05:00
Simon Glass
2189d5f1e8 Move strtomhz() to vsprintf.h
At present this function sits in its own file but it does not really
justify it. There are similar string functions in vsprintf.h, so move it
there. Also add the missing function comment.

Use the vsprintf.h include file explicitly where needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:09 -05:00
Simon Glass
3db7110857 crc32: Use the crc.h header for crc functions
Drop inclusion of crc.h in common.h and use the correct header directly
instead.

With this we can drop the conflicting definition in fw_env.h and rely on
the crc.h header, which is already included.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:08 -05:00
Simon Glass
c076e5c9b3 status_led: Tidy up the code style
There are a few whitespace problems with this code. Tidy them up.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:06 -05:00
Simon Glass
9ce2aa1710 Drop CONFIG_SHOW_ACTIVITY
This feature is not enabled by any board. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-12-02 18:23:06 -05:00
Simon Glass
62f9b65447 common: Move older CPU functions to their own header
These should be moved to driver model, but in the meantime, move them
out of the common header to help reduce its size.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:06 -05:00
Tom Rini
1f3813c2ab Merge branch 'master' of git://git.denx.de/u-boot-mips
- MIPS: remove Micronas VCT boards
2019-12-02 10:53:07 -05:00
Daniel Schwierzeck
2a250ae9b6 MIPS: remove Micronas VCT boards
The deadline for migration to CONFIG_DM is v2020.01. The VCT
baords would need an almost complete rewrite of all drivers to
support driver model.

Unless someone has access to the hardware and volunteers to do the migration,
the board should be scheduled for removal.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
2019-11-29 16:18:35 +01:00
Tom Rini
dd38416d6b Merge git://git.denx.de/u-boot-socfpga
- Assorted Gen5 fixes
2019-11-28 07:34:41 -05:00
Tom Rini
089612da33 Merge tag 'mmc-11-27-2019' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- fsl_esdhc update and some cleanup in ls1021a/mpc83xx code
- mmc tmio sdhi update for hs400
2019-11-28 07:33:45 -05:00
Tom Rini
29061447a0 - Solve warning for stih410-b2260
- Device tree alignment on v5.4-rc4 for all stm32 boards
 - Correct the eMMC pin configuration on stm32mp157c-ev1
 - Add DFU and SPI-NAND support for stm32mp1 board
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCgAdFiEE56Yx6b9SnloYCWtD4rK92eCqk3UFAl3dN0YACgkQ4rK92eCq
 k3WlywgAisVONrdkoC345Kq1vQRcKGYxcWVd0IWkuK3QZ4KrMRQrhEqXhmR7OhWD
 4YrAlgV6FEBTlacfKKsxaL7MJ3VK+h5YLvqoGzZS2Inmrx09v6rOofVTRevmB4Qz
 SlIeUKVBijORmRi31I/WcLdiPgd3RR53wQgAugU3PUpuoUb1Z+sJdOreOkl5qGyZ
 8aRgvG/if8afILXfH/a4IUuPboaVjaC5B20JCzX4M4ks8lHJ3atbtawgj/e41yYv
 Ybq3QudM62g4SvTgJ5/1yqjQ4Oj8dkAY7JyAiXfHa9Kip7s16aBDFklDH7eR9v7F
 IxyoYcFhuPADE7ApdWtij/y/KRS66Q==
 =oVPG
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-stm32-20191126' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Solve warning for stih410-b2260
- Device tree alignment on v5.4-rc4 for all stm32 boards
- Correct the eMMC pin configuration on stm32mp157c-ev1
- Add DFU and SPI-NAND support for stm32mp1 board
2019-11-28 07:33:16 -05:00
Tom Rini
4b39568cfd Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
- powerpc: Fix DM_MMC related build warnings by adding eSDHC device
  module support for T4240RDB, T2080RDB, T1042D4RDB, T1024RDB, P5040DS,
  P4080DS, P3041DS, P2041RDB, P2020RDB, P1020RDB platforms
2019-11-28 07:32:44 -05:00
Yangbo Lu
1eaffca076 mpc83xx: remove unused clock.h
The clock.h was to define mxc_get_clock() providing clock value
to fsl_esdhc driver. Since fsl_esdhc driver is using global data
gd->arch.sdhc_clk directly now, we can remove this file.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-27 16:55:56 +08:00
Yangbo Lu
d3eb317ea5 arm: drop eSDHC clock getting in mxc_get_clock() for layerscape
Although layerscape platforms reuse mxc_get_clock() of i.MX platforms,
eSDHC clock getting do not have to use it. It uses global data
gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more
than one eSDHC controllers on SoC, they use same reference clock.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-27 16:55:56 +08:00
Patrick Delaunay
4d7d0e2e78 ARM: dts: stm32: update eMMC configuration for stm32mp157c-ev1
Update the sdmmc2 node for eMMC support on eval board stm32mp157c-ev1.
- update slew-rate for pin configuration
- update "vqmmc-supply"
- remove "st,sig-dir"
- add mandatory "pinctrl-names"
- add "mmc-ddr-3_3v"

This patch solve the eMMC detection issue for command "mmc dev 1".

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-11-26 10:11:48 +01:00
Patrick Delaunay
62d620c243 ARM: dts: stm32: DT alignment with kernel v5.4-rc4
Device tree and binding alignment with kernel v5.4-rc4

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2019-11-26 10:11:48 +01:00
Patrick Delaunay
e07a86b5e3 ARM: dts: stm32: DT alignment with kernel v5.3
Device tree and binding alignment with kernel v5.3
and converted to SPDX.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2019-11-26 10:11:48 +01:00
Tom Rini
4b19b89ca4 - add RPi4 upstream compatible to pinctrl
- fix boot banner on RPi3/4
 - add support for one binary on RPi3/4
 -----BEGIN PGP SIGNATURE-----
 
 iQJGBAABCAAwFiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAl3a8R4SHG1icnVnZ2Vy
 QHN1c2UuY29tAAoJEC9tfk32wqh+AfQP/iO4qiJWUsY1WgChKl0wZNnkJKViNu6v
 F7zczCIUyI7krdVb3E3PB/ZJwXY/ay1rQeY91cU/9f0Z3yOlsoiwnEfOT/HwwkmD
 KnS6nhisqL0W1yd8sK8XaLOydIFfe05Do1UvF1JhOl3061R81fdruXygkHlgFXiK
 /hrEXLb9l0Zf4XMSD9hQJZiC/K3qeUZV1KsEdSGArjjTj3kivvS++Z0XD1YZsBVs
 rsEl3ZhPeUmzAxmg26IfyJan02NjWY+MyuoSd8QW5kVGsF4WOgvDuBOY1YJ08C/7
 NhLGkub/XhqHVSaMDwiSoX9d2z7ZqTaw7+IZW38+fCMUFAEHiErqMDq+Zfk1DKCd
 WynOzMj6k+Kli+amHQMHuUqIY54XPwpXdn671C7XbQ8xWh7HhWH/sEHP7ekrSV74
 Et7dy5fcleCcrr8EDhdC5iO2fLKhswq4iT0PbnFMtha4jhPqFVHVaAZDacucJ1/V
 JpfYRkLrmEbva3G1emve80tzlDNDxjraX8G6/6trN+F0xjorcbImp64RtRjgdL62
 DwIuba15BGR18LQJY/yHSHT4h3ReEG5qF9vxX+r6vMiFACZbnBPAP/b/REDQ6LWs
 dwW01JQ343dmZiegBQOe98fRDMGhmTd52mAJ/8p60X+byIh5I4XFKCdEdUpSVBpK
 ARrdtg9vtLxv
 =4Z+A
 -----END PGP SIGNATURE-----

Merge tag 'rpi-next-2020.01' of https://github.com/mbgg/u-boot

- add RPi4 upstream compatible to pinctrl
- fix boot banner on RPi3/4
- add support for one binary on RPi3/4
2019-11-25 12:56:27 -05:00
Marek Vasut
a1a9843a29 ARM: socfpga: Unreset NAND in SPL on Gen5
In case the SPL on Gen5 loads U-Boot from NAND, unreset the NAND IP
explicitly in the platform code as the denali-spl driver is not aware
of DM at all.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-25 13:12:56 +01:00
Marek Vasut
2007a730ee ARM: socfpga: Add ArriaV ST/SX ID
Add new FPGA ID for ArriaV ST/D3 or SX/B3 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-25 13:12:56 +01:00
Marek Vasut
97a72bc286 ARM: socfpga: Purge pending transactions upon enabling bridges on Gen5
On Gen5, when the FPGA is loaded and there was some prior interaction
between the HPS and the FPGA via bridges (e.g. Linux was running and
using some of the IPs in the FPGA) followed by warm reset, it has been
observed that there might be outstanding unfinished transactions. This
leads to an obscure misbehavior of the bridge.

When the bridge is enabled again in U-Boot and there are outstanding
transactions, a read from within the bridge address range would return
a result of the previous read instead. Example:
=> bridge enable ; md 0xff200000 1
ff200000: 1234abcd
=> bridge enable ; md 0xff200010 1
ff200010: 5678dcba <------- this is in fact a value which is stored in
                            a memory at 0xff200000
=> bridge enable ; md 0xff200000 1
ff200000: 90effe09 <------- this is in fact a value which is stored in
                            a memory at 0xff200010
and so it continues. Issuing a write does lock the system up completely.

This patch opens the FPGA bridges in 'bridge enable' command, the tears
them down again, and then opens them again. This allows these outstanding
transactions to complete and makes this misbehavior go away.

However, it is not entirely clear whether this is the correct solution.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-25 13:12:56 +01:00
Marek Vasut
446cf811c5 ARM: socfpga: Actually put bridges into reset on Gen5 in bridge disable
On Gen5, the 'bridge disable' command write 0x0 to brgmodrst register,
which releases all bridges from reset, instead of putting all bridges
into reset. Fix this by inverting the mask and actually putting the
bridges into reset.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-25 13:12:55 +01:00
Yinbo Zhu
c44d05d97b arch: powerpc: add eSDHC node to t4240 dts
Add eSDHC node to t4240 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
3f8f668d8c arch: powerpc: add eSDHC node to t104x dts
Add eSDHC node to t104x dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
d2c398b75f arch: powerpc: add eSDHC node to t102x dts
Add eSDHC node to t102x dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
428e7a1da6 arch: powerpc: add eSDHC node to p5040 dts
Add eSDHC node to p5040 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
9d05cd2ae9 arch: powerpc: add eSDHC node to p4080 dts
Add eSDHC node to p4080 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
dfeb70c182 arch: powerpc: add eSDHC node to p3041 dts
Add eSDHC node to p3041 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
067e09f23f arch: powerpc: add eSDHC node to p2041 dts
Add eSDHC node to p2041 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:26 +05:30
Yinbo Zhu
e126363dc7 arch: powerpc: add eSDHC node to p2020 dts
Add eSDHC node to p2020 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:26 +05:30
Yinbo Zhu
b73d5379c5 arch: powerpc: add eSDHC node to p1020 dts
Add eSDHC node to p1020 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:26 +05:30
Matthias Brugger
5694090670 ARM: defconfig: add unified config for RPi3 and RPi4
Provide a defconfig which allows us to boot Raspberrry Pi 4
and Raspberry Pi 3 Model B/B+
Instead of using the embedded DTB as done in RPi3 we use the
devicetree provided by the firmware.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:28 +01:00
Matthias Brugger
917a1e9a78 ARM: bcm283x: Set memory map at run-time
For bcm283x based on arm64 we also have to change the mm_region.
Add assign this in mach_cpu_init() so we can create now one binary
for RPi3 and RPi4.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:28 +01:00
Matthias Brugger
dd47ca7873 ARM: bcm283x: Set rpi_bcm283x_base at run-time
As part of the effort to create one binary for several bcm83x SoCs
we read the IO base address from device-tree.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:27 +01:00
Matthias Brugger
8e3361c88a ARM: bcm283x: Move BCM283x_BASE to a global variable
We move the per SOC define BCM283x_BASE to a global variable.
This is a first step to provide a single binary for several bcm283x
SoCs.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:27 +01:00
Matthias Brugger
5051377a0b arm: dts: bcm283x: Rename U-Boot file
Rename the file bcm283x-uboot.dtsi so that it get
automatically include through the scripts/Makefile.lib
using $(CONFIG_SYS_SOC))-u-boot.dtsi

Without this uarts and pincontroller miss the property dm-pre-reloc
and the first call to bcm283x_mu_serial_ofdata_to_platdata() fails
as the pins are not set correctly.
As a result the U-Boot banner isn't shown on boot.

Before commmit
143256b353 ("fdt: update bcm283x device tree sources to Linux 5.1-rc6 state")
we included bcm283x-uboot.dtsi directly in the device-tree file.
Which got deleted by the metioned commit.
This is a much robuster solution.

Reported-by: Tom Rini <trini@konsulko.com>
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Tom Rini <trini@konsulko.com> [RPi 3, 32b and 64b modes]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:27 +01:00
Matthias Brugger
89e47e8eb6 fdt: fix bcm283x dm-pre-reloc definitions
In commmit
143256b353 ("fdt: update bcm283x device tree sources to Linux 5.1-rc6 state")
we deleted the label for the node soc from bcm283x.dtsi

As we don't need to add the property dm-pre-reloc to the soc node,
we can delete it from bcm283x-uboot.dtsi

Tested-by: Tom Rini <trini@konsulko.com> [RPi 3, 32b and 64b modes]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:27 +01:00
Tom Rini
9a0cbae22a Merge tag 'u-boot-rockchip-20191124' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Clean vid/pid in Kconfig and add fastboot for rk3399
- add 'u-boot, spl-fifo-mode' for mmc
- Use FIT generator for rk3229 optee and rk3368 ATF
- fan53555: add support for Silergy SYR82X and SYR83X
2019-11-23 20:50:11 -05:00
Heinrich Schuchardt
16540d07fd arm: fix -march for ARM11
In GCC 9 support for the Armv5 and Armv5E architectures (which have no
known implementations) has been removed, cf.
https://gcc.gnu.org/gcc-9/changes.html

ARM11 is an armv6 implementation. So change the architecture flag for the
compiler to armv6 for ARM11.

Suggested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-11-23 14:53:48 -05:00
Heiko Stuebner
8019d32c47 rockchip: px30: enable spl-fifo-mode for both emmc and sdmmc on evb
As part of loading trustedfirmware, the SPL is required to place portions
of code into the socs sram but the mmc controllers can only do dma
transfers into the regular memory, not sram.

The results of this are not directly visible in u-boot itself, but
manifest as security-relate cpu aborts during boot of for example Linux.

There were a number of attempts to solve this elegantly but so far
discussion is still ongoing, so to make the board at least boot correctly
put both mmc controllers into fifo-mode, which also circumvents the
issue for now.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-11-23 23:41:44 +08:00
Jagan Teki
c618bb0042 rockchip: Setup dwc3_device (for non-dm gadgets)
Setup dwc3_device structure for non-dm gadgets, which is used
in rk3399 platforms.

dwc3_device would have basic regbase, dr_mode, high speed
and 16-bit UTMI+ etc.

Cc: Marek Vasut <marex@denx.de>
Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Fix to use CONFIG_USB_DWC3_GADGET instead of CONFIG_USB_DWC3)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23 23:41:44 +08:00
Kever Yang
65325fba5a rockchip: Convert to use FIT generator for optee
Use generator script so that we can use environment for TEE source.
$TEE for tee.bin, and if file not exist, the script can report a warning,
and meke the build success without a error.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23 22:29:49 +08:00
Tom Rini
47b48fe186 Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- Assorted fixes
2019-11-22 10:41:46 -05:00
Tom Rini
71d96eb99e Merge branch 'master' of git://git.denx.de/u-boot-sh
- Assorted Gen3 fixes
2019-11-22 10:24:14 -05:00
Ooi, Joyce
0c14bb5ad3 arm: socfpga: stratix10: Add alias for gmac0 in S10 dts
Add 'ethernet0' as alias for 'gmac0' in S10 device tree.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-22 03:08:12 +01:00
Ooi, Joyce
7dad444c76 arm: dts: Stratix10: change pad skew values for EMAC0 PHY driver
The HPS EMAC0 drive strength is changed to 4mA because the initial 8mA
drive strength has caused CE test to fail. This requires changes on the
pad skew for EMAC0 PHY driver. Based on several measurements done, Tx
clock does not require the extra 0.96ns delay which was needed in
Arria10.

Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-22 03:08:12 +01:00