Commit graph

20 commits

Author SHA1 Message Date
Moritz Fischer
ac6991fb5f zynq: spi: Honour the activation / deactivation delay
This is not currently implemented. Add support for this so that the
Chrome OS EC can be used reliably.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-05-03 11:03:04 +05:30
Simon Glass
e160f7d430 dm: core: Replace of_offset with accessor
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-08 06:12:14 -07:00
Tom Rini
19d051a2b7 Merge branch 'master' of git://git.denx.de/u-boot-spi 2016-09-22 11:36:45 -04:00
Michal Simek
5f647c2284 spi: zynq: Use variable to remove u32 to u64 conversions
Current code generates warning when it is compiled for arm64:
Warnings:
In file included from drivers/spi/zynq_spi.c:14:0:
drivers/spi/zynq_spi.c: In function ‘zynq_spi_init_hw’:
drivers/spi/zynq_spi.c:95:9: warning: large integer implicitly truncated
to unsigned type [-Woverflow]
  writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
         ^
./arch/arm/include/asm/io.h:146:34: note: in definition of macro
‘writel’
 #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v;
})
                                  ^
drivers/spi/zynq_spi.c: In function ‘zynq_spi_release_bus’:
drivers/spi/zynq_spi.c:177:9: warning: large integer implicitly
truncated to unsigned type [-Woverflow]
  writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
         ^
./arch/arm/include/asm/io.h:146:34: note: in definition of macro
‘writel’
 #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v;
})
                                  ^
This patch is using one variable to do conversion via u32 variable.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-09-22 07:33:20 +02:00
Lad, Prabhakar
d2998286fc spi: zynq_spi: Fix infinite looping while xfer
During spi transfer, for example:
sspi 1:1.0 8 ff

the rx_len values will  be:
rx_len = 0
rx_len = 4294967295

This caused a busy looping during xfer, this patch fixes it
by adding a check while reading the rx fifo

Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-09-22 00:58:26 +05:30
Michal Simek
23ef5aea84 spi: zynq_spi: Add cadence compatible string
Extend compatible list table for cdns,spi-r1p6 compatible string.

Reviewed-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-11 22:12:23 +05:30
Jagan Teki
9cf2ffb3c3 spi: zynq_[q]spi: Use GENMASK macro
GENMASK macro used on zynq_spi.c and zynq_qspi.c

GENMASK is used to create a contiguous bitmask([hi:lo]).
Ex: (0x7 << 3) => GENMASK(5, 3)

Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:19:15 +05:30
Jagan Teki
736b4df15d spi: zynq_[q]spi: Use BIT macro
Used BIT macro on zynq_spi.c and zynq_qspi.c

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:18:48 +05:30
Jagan Teki
86e99b9861 spi: zynq_spi: Remove unneeded headers
- Removed unneeded inclusion of header files
- Add "Xilinx" on license text

Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25 20:17:03 +05:30
Jagan Teki
191269987c spi: zynq_spi: Store cs value into private data
Store cs value into private data and use it while activating
chipselect instead of passing through function.

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25 20:17:02 +05:30
Jagan Teki
dda6241a1d spi: zynq_spi: Rename baudrate divisor mask name
Rename ZYNQ_SPI_CR_BRD_MASK to ZYNQ_SPI_CR_BAUD_MASK
for more readable.

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25 20:17:02 +05:30
Jagan Teki
46ab8a6a13 spi: zynq_spi: Add config reg shift named macros
Update the numerical values for baudrate and chipselect
with config reg shift named macro's

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25 20:17:02 +05:30
Jagan Teki
a22bba81e4 spi: zynq_spi: Fix to configure CPOL, CPHA mask
priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.

This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-11 16:43:06 +05:30
Simon Glass
4e9838c102 dm: Use dev_get_addr() where possible
This is a convenient way for a driver to get the hardware address of a
device, when regmap or syscon are not being used. Change existing callers
to use it as an example to others.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-08-31 07:57:26 -06:00
Michal Simek
80fd9792f5 spi: zynq_spi: Simplify debug macro
Trivial fix.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:28 +02:00
Michal Simek
40b383fa84 spi: Fix zynq SPI binding
Zynq is using Cadence IP where binding is documented in the Linux kernel
and there is no reason to use different binding.
Synchronize it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:22 +02:00
Jagan Teki
cdc9dd0750 spi: zynq_spi: Add fdt support in driver
Now zynq spi driver platform data is controlled by devicetree,
enable the status by saying "okay" on respective board dts to use
the devicetree generated platdata.

Ex:
&spi1 {
	status = "okay";
};

Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
2015-07-01 21:15:03 +05:30
Jagan Teki
b1c82da266 dm: spi: zynq_spi: Convert to driver model
This converts the zynq spi driver to use the driver model.

Minimal functional changes like using meaningful name on
structure members wrt mainlined dm spi drivers.
- input_hz -> frequency
- req_hz -> freq
- base -> regs

Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
2015-07-01 21:15:03 +05:30
Siva Durga Prasad Paladugu
8c48a68346 zynq: spi: Remove unnecessary error condition
Removed the unnecessary error check from spi_xfer
as the bitlen zero is possible now to deassert the
chip select for which no data is required to be transfered.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-04-22 16:49:51 +05:30
Jagannadha Sutradharudu Teki
1465d055f9 spi: Add zynq spi controller driver
Zynq spi controller driver supports 2 buses and
3 chipselects on each bus.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-08-07 01:09:47 +05:30