Commit graph

54 commits

Author SHA1 Message Date
Simon Glass
d2da54bfc4 Convert CONFIG_SYS_IDE_MAXBUS et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_IDE_MAXBUS
   CONFIG_SYS_IDE_MAXDEVICE
   CONFIG_SYS_ATA_BASE_ADDR
   CONFIG_SYS_ATA_STRIDE
   CONFIG_SYS_ATA_DATA_OFFSET
   CONFIG_SYS_ATA_REG_OFFSET
   CONFIG_SYS_ATA_ALT_OFFSET
   CONFIG_SYS_ATA_IDE0_OFFSET
   CONFIG_SYS_ATA_IDE1_OFFSET
   CONFIG_ATAPI
   CONFIG_IDE_RESET

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09 09:16:47 -05:00
Simon Glass
e567122b32 x86: coreboot: Support getting a logo from virtio
Enable this feature so that a splash screen can be provided.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:33:26 +01:00
Bin Meng
ceeee8f7b5 x86: coreboot: Add generic coreboot payload support
Currently building U-Boot as the coreboot payload requires user
to change the build configuration for a specific board during
menuconfig process. This uses the board's native device tree
to configure the hardware. For example, the device tree provides
PCI address range for the PCI host controller and U-Boot will
re-program all PCI devices' BAR to be within this range. In order
to make sure we don't mess up the hardware, we should guarantee
the range matches what coreboot programs the chipset.

But we really should make the coreboot payload support easier.
Just like EFI payload, we can create a generic coreboot payload
for all x86 boards as well. The payload is configured to include
as many generic drivers as possible. All stuff that touches low
level initialization are not allowed as such is the coreboot's
responsibility. Platform specific drivers (like gpio, spi, etc)
are not included.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-08-20 13:52:06 +08:00
Bin Meng
fa48e51013 x86: Remove include/configs/coreboot.h
Since we already swtiched to use the new mechanism for building
U-Boot for coreboot, coreboot.h is no longer needed so remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:04 -08:00
Bin Meng
9d74f03460 x86: coreboot: Move coreboot-specific defines from coreboot.h to Kconfig
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.

Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch
to board configuration file to build U-Boot later.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:03 -08:00
Bin Meng
41702bac01 x86: Rename coreboot-serial to x86-serial
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:08 -07:00
Simon Glass
880a3cc438 x86: config: Move common x86 configs to a common file
Many of the x86 CONFIG options will be common across different boards. Move
them to a common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:12 +01:00
Simon Glass
026090e4c5 x86: config: Increase CONFIG_SYS_BOOTM_LEN to 16MB
The code density of x86_64 is not wonderful. Increase the maximum boot
size and adjust the load address to cope.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-29 13:11:54 -06:00
Simon Glass
92cc94a1fe x86: Display basic CPU information on boot
Display the type of CPU (x86 or x86_64) when starting up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-28 20:42:56 -06:00
Simon Glass
e98a03ca68 dm: x86: Convert coreboot serial to use driver model
This makes use of the existing device tree node to use driver model
for the serial console.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-23 19:45:45 -06:00
Simon Glass
7414112d70 dm: x86: Convert Intel ICH6 GPIO driver to use driver model
Convert over this driver, using device tree to pass in the required
information. The peripheral is still probed, just the number of GPIO banks
and their offsets is in the device tree (previously this was a table in
the driver).

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-23 19:45:28 -06:00
Simon Glass
c0561d14c5 x86: Enable FIT, ELF on coreboot
Enable FIT support and the bootelf command. Also change the default load
address to somewhere other than the normal load address of the kernel,
to allow for decompression without overwriting the original file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 21:50:33 -06:00
Simon Glass
c67161c1f1 x86: config: link: Display the board model on the screen
To get a display in U-Boot on link you must either build a coreboot that
always sets it up, or use Esc-Refresh-Power to reset the machine.

When we do have a display, it is nice to display the model at the top, so
enable this option.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 21:50:33 -06:00
Simon Glass
39c0b633c0 x86: link: Tidy up the command lines options
We may as well use hush. The auto-complete option was incorrect so this was
not enabled. Also expand the command line size a little and go back to the
default prompt since "boot>" doesn't seem any more useful.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 21:50:33 -06:00
Simon Glass
14db950945 x86: cros_ec: Enable cros_ec for link
Add defines to enable the Chrome OS EC interface and set it up on init.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 21:50:33 -06:00
Simon Glass
2d41046531 x86: config: Enable dhcp on link
The dhcp option is required to get bootp to work on the Chromebook Pixel,
so enable it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 21:50:32 -06:00
Masahiro Yamada
f1ef2b6233 kconfig: move CONFIG_DEFAULT_DEVICE_TREE to kconfig
This option specifies the default Device Tree used for the run-time
configuration of U-Boot.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Michal Simek <michal.simek@xilinx.com>
2014-09-25 09:31:24 -04:00
Masahiro Yamada
783e6a72b8 kconfig: move CONFIG_OF_* to Kconfig
This commit moves:
  CONFIG_OF_CONTROL
  CONFIG_OF_SEPARATE
  CONFIG_OF_EMBED
  CONFIG_OF_HOSTFILE

Because these options are currently not supported for SPL,
the "Device Tree Control" menu does not appear in the SPL
configuration.

Note:
zynq-common.h should be adjusted so as not to change the
default value of CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2014-09-25 09:27:50 -04:00
Siva Durga Prasad Paladugu
64e809afea fpga: Guard the LOADMK functionality with CMD_FPGA_LOADMK
Guard the LOADMK functionality with config to provide
an option to enable or disable it.
Enable it for all platforms in mainline which enable CONFIG_CMD_FPGA.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20 15:23:46 +02:00
Vladimir Zapolskiy
2c808a12ea kgdb: configs: remove obsolete CONFIG_KGDB_SER_INDEX
The last users of CONFIG_KGDB_SER_INDEX were removed more than 3 years
ago in commits 550650ddd0 and bf16500f79, either kgdb subsystem should
care about this parameter or it should be gone completely.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2013-12-13 09:15:32 -05:00
Rob Herring
f232950f82 config: remove platform CONFIG_SYS_HZ definition part 2/2
Remove platform CONFIG_SYS_HZ definition for configs a-z*.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-11-04 11:06:16 -05:00
Wolfgang Denk
3765b3e7bd Coding Style cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:53 -04:00
Rob Herring
344ca0b40c ahci: convert to use libata functions and definitions
libata already has similar functions as implemented in the ahci code.
Refactor the code to use the libata variants and remove the dependency on
ata.h. Convert some defines to use the version from libata.h. Also, remove
some unnecessary memset's of bss data.

This is a step toward hopefully merging ahci.c and dw_ahsata.c which are
essentially the same driver.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-09-06 13:09:07 -04:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Simon Glass
b5f3193734 x86: config: Add tracing options
Add configs to enable tracing when it is needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26 10:18:56 -04:00
Tom Wai-Hong Tam
5bdf46b71b x86: config: Reflect the name changes of LPC TPM configs
The new name is more aligned with Linux kernel's naming of TPM driver.

Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-03 01:26:25 -07:00
Simon Glass
04dbf77d62 x86: config: Enable LZO for coreboot, remove zlib, gzip
We don't use zlib and gzip but do use lzo, so enable this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13 13:33:22 -07:00
Simon Glass
2e65959be6 x86: Enable bootstage for coreboot
This is a convenient way of finding out where boottime is going. Enable
it for coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13 13:33:21 -07:00
Simon Glass
d0b6f247a1 x86: Re-enable PCAT timer 2 for beeping
While we don't want PCAT timers for timing, we want timer 2 so that we can
still make a beep. Re-purpose the PCAT driver for this, and enable it in
coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13 13:33:21 -07:00
Simon Glass
e761ecdbb8 x86: Add TSC timer
This timer runs at a rate that can be calculated, well over 100MHz. It is
ideal for accurate timing and does not need interrupt servicing.

Tidy up some old broken and unneeded implementations at the same time.

To provide a consistent view of boot time, we use the same time
base as coreboot. Use the base timestamp supplied by coreboot
as U-Boot's base time.

Signed-off-by: Simon Glass <sjg@chromium.org>base
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13 13:33:21 -07:00
Simon Glass
617c246f3c x86: config: Init PCI before SPI
Since the ICH SPI controller uses PCI, we must ensure that PCI is available
before it is inited.

This fixes the current "ICH SPI: Cannot find device" message on boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-04-15 16:26:43 -07:00
Tom Rini
8b906a9f0b Merge branch 'spi' of git://git.denx.de/u-boot-x86 2013-03-20 14:55:10 -04:00
Simon Glass
363464f993 x86: Enable time command for coreboot
This command is useful for measuring SPI flash load times and the like.
Enable gettime as well to obtain absolute time tick values.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19 08:45:37 -07:00
Simon Glass
e30bd5cfee x86: Enable SPI flash support for coreboot
Turn on SPI flash support and related commands.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19 08:45:37 -07:00
Simon Glass
0641ce5b5a x86: Enable USB features for coreboot
Enable PCI EHCI, storage, keyboard and Ethernet for USB.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-18 18:58:54 +01:00
Simon Glass
fc959081d4 x86: Enable CONFIG_OF_CONTROL on coreboot
Make use of a device tree on coreboot boards, and set the default
to link.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-04 15:57:52 -08:00
Simon Glass
588a13f742 x86: Rename CONFIG_NO_X86_RESET_VECTOR to CONFIG_X86_RESET_VECTOR
Invert the polarity of this option to simplify the Makefile logic.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Gabe Black <gabeblack@chromium.org>
2013-02-14 20:18:58 -08:00
Simon Glass
a08afb398b x86: coreboot: Enable io command
Enable the io command for x86 on coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-26 10:36:25 -08:00
Simon Glass
ac426b7290 x86: Fix coreboot config to boot on Chromebook
The config is current broken. It compiles but does not boot because IDE is
enabled. Remove all IDE options, and enable SCSI instead.

Also add a working boot command and Linux bootargs, and enable command
line editing to make it easier to work with.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:45 -08:00
Gabe Black
d954a431ec x86: Turn on support for EFI's GPT in the coreboot config
This allows u-boot to figure out the partitions of a chrome-os install.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Simon Glass
cbca883c46 x86: coreboot: Enable video display
Enable the display on coreboot, using CFB.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Stefan Reinauer
300081aa68 x86: Emit port 80 post codes in show_boot_progress()
This helps us monitor boot progress and determine where U-Boot dies if
there are any problems.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Simon Glass
34d6057be1 x86: Enable CONFIG_CMD_ZBOOT for coreboot
Enable this option to support booting a zImage.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:40 -08:00
Simon Glass
a7e6d5496c x86: Enable ICH6 GPIO controller for coreboot
Coreboot uses this controller to implement GPIO access.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:38 -08:00
Simon Glass
a78d49473c x86: Define CONFIG_SYS_VSNPRINTF for coreboot
This option protects the printf() functions from overflow.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:05 -08:00
Simon Glass
420a2ca73f x86: Select stdio devices for coreboot
We want to support VGA, serial, USB keyboard and the Coreboot memory
console buffer.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30 13:44:03 -08:00
Simon Glass
d02a568e9a x86: coreboot: Enable LPC TPM
Coreboot boards have an LPC TPM connected, so enable this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:05 -08:00
Simon Glass
cd23e6923f x86: Remove coreboot start16 code
Now that coreboot doesn't need the start16 code, remove it. We need
to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:05 -08:00
Graeme Russ
8d61625d6a x86: Put global data on the stack
Putting global data on the stack simplifies the init process (and makes it
slightly quicker). During the 'flash' stage of the init sequence, global
data is in the CAR stack. After SDRAM is initialised, global data is copied
from CAR to the SDRAM stack

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28 11:40:03 -08:00
Simon Glass
51bdad67cb x86: config: Enable AHCI support for coreboot
Enable AHCI driver for Intel SATA devices.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-02 15:20:43 -07:00