Commit graph

26 commits

Author SHA1 Message Date
Daniel Golle
bcfb23ec7e pinctrl: mediatek: set R1/R0 in case pullen/pullsel succeeded
Commit dafe0fbfb0 ("pinctrl: mediatek: rewrite mtk_pinconf_set and
related functions") changed the logic deciding to set R0 and R1
registers for V1 devices.

Before:
	/* Also set PUPD/R0/R1 if the pin has them */
	err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PUPD, !pullup);
	if (err != -EINVAL) {
		mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R0, r0);
		mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R1, r1);
	}

After:
	/* try pupd_r1_r0 if pullen_pullsel return error */
	err = mtk_pinconf_bias_set_pullen_pullsel(dev, pin, disable, pullup,
						  val);
	if (err)
		return mtk_pinconf_bias_set_pupd_r1_r0(dev, pin, disable,
						       pullup, val);

Tracing mtk_pinconf_bias_set_pullen_pullsel shows that the function
always either returns 0 in case of success or -EINVAL in case any error
has occurred. Hence the logic responsible of the decision to program R0
and R1 has been inverted.

This leads to problems on BananaPi R2 (MT7623N) when booting from
SDMMC, it turns out accessing eMMC no longer works since
U-Boot 2022.07:

MT7623> mmc dev 0
Card did not respond to voltage select! : -110

The problem wasn't detected for a long time as both eMMC and SDMMC work
fine if they are used to boot from, and hence R0 and R1 were already
setup by the bootrom and/or preloader.

Fix the logic to restore the originally intended and correct behavior
and also change the descriptive comment accordingly.

Fixes: dafe0fbfb0 ("pinctrl: mediatek: rewrite mtk_pinconf_set and related functions")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Tested-By: Frank Wunderlich <frank-w@public-files.de>
2023-05-03 09:05:24 -04:00
Weijie Gao
59acdf8afe pinctrl: mediatek: add pinctrl driver for MT7986 SoC
This patch adds pinctrl and gpio support for MT7986 SoC

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:15 -04:00
Weijie Gao
ace67d1097 pinctrl: mediatek: add pinctrl driver for MT7981 SoC
This patch adds pinctrl and gpio support for MT7981 SoC

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23 15:09:15 -04:00
Sam Shih
1a80ef5520 pinctrl: mediatek: add support for different types of IO pins
There are many pins in an SoC, and register usage may vary by pins.
This patch introduces a concept of "io type" and "io type group"
to mediatek pinctrl drivers. This can provide different pinconf
handlers implementation (eg: "bias-pull-up/down", "driving" and
"input-enable") for IO pins that belong to different types.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2022-05-05 09:29:58 -04:00
Sam Shih
10334e0bc8 pinctrl: mediatek: introduce multiple memory bases support
Pinctrl design of some mediatek SoC need to access registers that
distribute in multiple memory base address. this patch introduce new
mechanism in mediatek pinctrl driver to support the chips which have
the new design.

This patch add a member 'base_calc' in pinctrl private data, and changed
original 'base' private data to an array of *iomem.

When 'base_calc' attribute is set, it will requests multiplue regs base
from the DT, if 'base_calc' attribute is not set, it only use legacy way
to request single reg resource from the DT.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2022-05-05 09:29:58 -04:00
Sam Shih
dafe0fbfb0 pinctrl: mediatek: rewrite mtk_pinconf_set and related functions
There are many pins in a SoCs, and different pin may belong
to different "io_type", For example: some pins of MT7622 belongs
to "io_type A", the other belongs to "io_type B", and pinctrl "V0"
means handle pinconf via "io_type A" or "io_type B", so SoCs that
contain "io_type A" and "io_type B" pins, use "V0" in pinctrl driver.

This patch separates the implementation of register operations
(e.g: "bias-pull-up/down", "driving" and "input-enable") into
different functions, and lets the original V0/V1
ops to call the new functions.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2022-05-05 09:29:57 -04:00
Wolfgang Denk
66356b4c06 WS cleanup: remove trailing empty lines
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30 08:08:56 -04:00
Simon Glass
83061dbd1c Rename GPIO_SUPPORT to GPIO
Rename these options so that CONFIG_IS_ENABLED can be used with them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-28 14:29:36 -04:00
Weijie Gao
a449cdb881 pinctrl: mt7629: add jtag function and pin group
The EPHY LEDs of mt7629 can be used as JTAG. This patch adds the jtag pin
group to the pinctrl driver.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-03-20 16:24:27 -04:00
Weijie Gao
70a2b4220e pinctrl: mediatek: do not probe gpio driver if not enabled
The mtk pinctrl driver is a combination driver with support for both
pinctrl and gpio. When this driver is used in SPL, gpio support may not be
enabled, and this will result in a compilation error.

To fix this, macros are added to make sure gpio related code will only be
compiled when gpio support is enabled.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-03-20 16:24:27 -04:00
Sam Shih
e254d2c0a4 pinctrl: mediatek: add get_pin_muxing ops for mediatek pinctrl
This patch add get_pin_muxing support for mediatek pinctrl drivers

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2021-03-20 16:24:27 -04:00
Sam Shih
4fc5d4cedb pinctrl: mediatek: fix wrong assignment in mtk_get_pin_name
This is a bug fix for mtk pinctrl common part. Appearently pins should be
used instead of grps in mtk_get_pin_name().

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2021-03-20 16:24:27 -04:00
Heinrich Schuchardt
97bf73762f pinctrl: mediatek: correct error handling
If no GPIO controller is found, the return value should not depend on a
random value on the stack. Initialize variable ret.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2021-01-18 15:23:06 -05:00
Simon Glass
41575d8e4c dm: treewide: Rename auto_alloc_size members to be shorter
This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.

Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 08:00:25 -07:00
Chunfeng Yun
324220da63 pinctrl: mediatek: mt8512: fix the wrong start address of ranges
The start address of dout, pullen and pullsel ragnes are wrong,
so fix up them.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2020-08-19 17:37:37 -04:00
David Woodhouse
e05fdd9364 pinctrl: mediatek: add PUPD/R0/R1 support for MT7623
The pins for the MMC controller weren't being set up correctly because the
pinctrl driver only sets the GPIO pullup/pulldown config and doesn't
handle the special cases with PUPD/R0/R1 control.

Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
2020-07-29 08:43:40 -04:00
Sean Anderson
082faeb865 dm: Fix error handling for dev_read_addr_ptr
dev_read_addr_ptr had different semantics depending on whether OF_LIVE was
enabled. This patch converts both implementations to return NULL on error,
and converts all call sites which check for FDT_ADDR_T_NONE to check for
NULL instead. This patch also removes the call to map_physmem, since we
have dev_remap_addr* for those semantics.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-01 15:01:21 +08:00
Simon Glass
cd93d625fd common: Drop linux/bitops.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Sam Shih
cf400b63b4 pinctrl: mediatek: add support for different pinctrl
Due to the pinctrl hardware of MT7622 is difference from others
SoC which using the common part of mediatek pinctrl.
So we need to modify the common part of mediatek pinctrl.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
Sam Shih
a430149c99 pinctrl: mediatek: add driver for MT7622
This patch add Pinctrl driver for MediaTek MT7622 SoC.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
mingming lee
51fcd56c0d pinctrl: mediatek: add driver for MT8512
Add Pinctrl driver for MediaTek MT8512 SoC.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
mingming lee
485627dd5f pinctrl: add driver for MT8518
Add Pinctrl driver for MediaTek MT8518 SoC.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2019-12-03 08:44:14 -05:00
Fabien Parent
e66b202eb3 pinctrl: mediatek: fix warning
Fix the following warning when CONFIG_PINCONF=n:

drivers/pinctrl/mediatek/pinctrl-mtk-common.c:35:36:
warning: ‘mtk_drive’ defined but not used [-Wunused-const-variable=]
 static const struct mtk_drive_desc mtk_drive[] = {
                                    ^~~~~~~~~

Signed-off-by: Fabien Parent <fparent@baylibre.com>
2019-07-29 09:32:10 -04:00
Fabien Parent
6fdb50c098 pinctrl: add driver for MT8516
Add Pinctrl driver for MediaTek MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-23 17:57:26 -04:00
Ryder Lee
59a8fef342 pinctrl: MediaTek: add pinctrl driver for MT7623 SoC
This patch adds pinctrl support for MT7623 SoC. And most of the
structures are used to hold the hardware configuration for each
pin.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Tested-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:52 -05:00
Ryder Lee
01aa9d1d54 pinctrl: MediaTek: add pinctrl driver for MT7629 SoC
This patch adds pinctrl support for MT7629 SoC. The IO core found on
the SoC has the registers for pinctrl, pinconf and gpio mixed up in
the same register range.  Hence the driver also implements the gpio
functionality through UCLASS_GPIO.

This also creates a common file as there might be other chips that use
the same binding and driver, then being a little more abstract could
help in the long run.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:52 -05:00