Commit graph

10895 commits

Author SHA1 Message Date
Kever Yang
b0a569da08 rockchip: enable DEBUG_UART_BOARD_INIT by default
All Rockchip SoCs use DEBUG_UART_BOARD_INIT to init per board
UART IOMUX, enable it by default.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:06 +02:00
Kever Yang
b1b449bf1f rockchip: correct ARCH_SOC name
The ARCH_SOC name default as 'rockchip' and we put all the
header file in 'arch/arm/include/asm/arch-rockchip/', but
the 'rockchip' is not the SOC name, let's correct it after
we update all the source file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsiich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Kever Yang
15f09a1a83 rockchip: use 'arch-rockchip' as header file path
Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common
header file path, so that we can get the correct path directly.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Kever Yang
6916dad511 rockchip: arm: use 'arch-rockchip' for common header
rockchip platform header file is in 'arch-rockchip'
instead of arch-$(SOC) for all SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Kever Yang
9f09b9d3cc rockchip: arm: remove no use macro
TIMER7_BASE is no used by source code now, remove it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Urja Rannikko
59ef021b99 rk3288-board: remove pinctrl call for debug uart
This failed and caused a boot failure on c201, and afaik
the pins should be setup by the new pinctrl driver.

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Jagan Teki
ed9c9059f2 rockchip: rk3399: Add Orangepi RK3399 support
Add initial support for Orangepi RK3399 board.

Specification
- Rockchip RK3399
- 2GB/4GB DDR3
- 16GB eMMC
- SD card slot
- RTL8211E 1Gbps
- AP6356S WiFI/BT
- HDMI In/Out, DP, MIPI DSI/CSI
- Mini PCIe
- Sensors, Keys etc
- DC12V-2A and DC5V-2A

Commit details about Linux DTS sync:
"arm64: dts: rockchip: Add support for the Orange Pi RK3399"
(sha1: d3e71487a790979057c0fdbf32f85033639c16e6)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Jagan Teki
e05b4a4fa8 rockchip: dts: rk3399: Create initial rk3399-u-boot.dtsi
u-boot,dm-pre-reloc is required for SDMMC booted rk3399 boards and
which is U-Boot specific devicetrees binding.

Move it on global rk3399-u-boot.dtsi file and rest of the U-Boot
bindings will move it future based on the requirement.

This would help to sync the devicetrees from Linux whenever required
instead of adding specific nodes.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Jagan Teki
288dbc66da rockchip: dts: rk3399: Sync rk3399-opp from Linux
Sync rk3399-opp.dtsi from Linux.

Linux commit details about the rk3399-opp.dtsi sync:
"arm64: dts: rockchip: use SPDX-License-Identifier"
(sha1: 4ee99cebd486238ac433da823b95cc5f8d8a6905)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:04 +02:00
Simon Goldschmidt
7110259f55 dts: arm: socfpga: fix socfpga_de10_nano console
Booting this board failed as the initial console isn't found since
commit c402e81702 ("dts: arm: socfpga: merge gen5 devicetrees from linux")

The uart0 devicetree entry was missing "clock-frequency = <100000000>:"
since that commit

Fixes: c402e81702 ("dts: arm: socfpga: merge gen5 devicetrees from linux")
Reported-by: rafael mello <rafaelmello_3@hotmail.com>
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-29 20:33:23 +02:00
Marek Vasut
c5f4b80575 ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()
The usage of socfpga_sdram_apply_static_cfg() seems rather dubious and
is confirmed to lead to a rare system hang when enabling bridges. This
patch removes the socfpga_sdram_apply_static_cfg() altogether, because
it's use seems unjustified and problematic.

The socfpga_sdram_apply_static_cfg() triggers write to SDRAM staticcfg
register to set the applycfg bit, which according to old vendor U-Boot
sources can only be written when there is no traffic between the SDRAM
controller and the rest of the system. Empirical measurements confirm
this, setting the applycfg bit when there is traffic between the SDRAM
controller and CPU leads to the SDRAM controller accesses being blocked
shortly after.

Altera originally solved this by moving the entire code which sets the
staticcfg register to OCRAM [1]. The commit message claims that the
applycfg bit needs to be set after write to fpgaportrst register. This
is however inverted by Altera shortly after in [2], where the order
becomes the exact opposite of what commit message [1] claims to be the
required order. The explanation points to a possible problem in AMP
use-case, where the FPGA might be sending transactions through the F2S
bridge.

However, the AMP is only the tip of the iceberg here. Any of the other
L2, L3 or L4 masters can trigger transactions to the SDRAM. It becomes
rather non-trivial to guarantee there are no transactions to the SDRAM
controller.

The SoCFPGA SDRAM driver always writes the applycfg bit in SPL. Thus,
writing the applycfg again in bridge enable code seems redundant and
can presumably be dropped.

[1] 75905816ec
[2] 8ba6986b04

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-04-29 10:33:45 +02:00
Marek Vasut
72c347ced8 ARM: socfpga: Add support for selecting bridges in bridge command
Add optional "mask" argument to the SoCFPGA bridge command, to select
which bridges should be enabled/disabled. This allows the user to avoid
enabling bridges which are not connected into the FPGA fabric. Default
behavior is to enable/disable all bridges.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-04-29 10:08:56 +02:00
Marek Vasut
ba2cfcee88 ARM: socfpga: Fully unmap the FPGA bridges from L3 space
Instead of just putting the bridges into reset, fully remove the bridges
from the L3 main bridge space when disabling them by clearing bits in
NIC-301 remap register. Moreover, only touch the 3 LSbits in brgmodrst
register as the rest of the bits are undefined.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-04-29 10:08:55 +02:00
Marek Vasut
c1d4b464c8 ARM: socfpga: Disable bridges in SPL unless booting from FPGA
Disable bridges between L3 Main switch and FPGA unless booting
from FPGA and keep them disabled to prevent glitches and possible
hangs of the L3 Main switch.

The current version of the code could have enabled the bridges
between the L3 Main switch and FPGA for a short period of time
in board_init_f() in case the FPGA was programmed and then again
disable them at the end of board_init_f(). Replace this with a
code which only sets up the handoff registers and let the user
enable the bridges later on.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-04-29 10:08:55 +02:00
Marek Vasut
8df653c325 ARM: socfpga: Factor out handoff register configuration
Factor out the code for programming preloader handoff register values,
the ISWGRP Handoff 0 and 1. These registers later control which bridges
are enabled by the "bridge" command on Gen5 devices.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-04-29 10:08:55 +02:00
Heinrich Schuchardt
b85d155199 arm: dts: add missing vexpress device trees
Add the device trees for

* vexpress_ca5x2_defconfig
* vexpress_ca9x4_defconfig
* vexpress_ca15_tc2_defconfig

as available in Linux 5.1 rc5.

We are using the vexpress_ca15_tc2_defconfig and vexpress_ca9x4_defconfig
for Travis testing via QEMU.

The UEFI base Embedded Base Boot Requirements Specification (EBBR) requires
that an embedded board either provides a device tree or an ACPI table.

All block devices are meant to be moved to the driver model. On ARM this
requires a device tree.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-04-26 18:58:22 -04:00
Gregory CLEMENT
c8aac24629 arm: lpc32xx: Fix timer initialization
The match controller register is not cleared during
initialization. However, some bits of this register may reset the TC if
tnMRx match it.

As we can't make any assumption about how U-Boot is launched by the first
stage bootloader (such as S1L) clearing this register ensure that the
timers work as expected.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-04-26 18:58:20 -04:00
Andrew F. Davis
508369672c arm: mach-k3: Add secure device build support
K3 HS devices require signed binaries for boot, use the SECDEV tools
to sign the boot artifacts during build.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
2019-04-26 17:51:51 -04:00
Andrew F. Davis
3a543a8084 arm: mach-k3: Add secure device support
K3 devices have High Security (HS) variants along with the non-HS already
supported. Like the previous generation devices (OMAP/Keystone2) K3
supports boot chain-of-trust by authenticating and optionally decrypting
images as they are unpacked from FIT images. Add support for this here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
2019-04-26 17:51:51 -04:00
Andrew F. Davis
407a219261 arm: K3: Avoid use of MCU_PSRAM0 before SYSFW is loaded
On HS devices the 512b region of reset isolated memory called
MCU_PSRAM0 is firewalled by default. Until SYSFW is loaded we
cannot use this memory. It is only used to store a single value
left at the end of SRAM by ROM that will be needed later. Save
that value to a global variable stored in the .data section.
This section is used as .bss will be cleared between saving
this value and using it.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-26 17:51:51 -04:00
Tom Rini
07b68b7843 Merge git://git.denx.de/u-boot-marvell
- Add DM based generic watchdog start and reset implementation
  and remove all ad-hoc implementations (Stefan)
- Move mv_sdhci to DM (Pierre)
- Misc turris_omnia updates (Pierre)
- Change openrd targets to correctly build again (size changes
  and fixes to the dts targets) and bring it back into Travis
  builds (Stefan)
- Add Kirkwood db-88f6281-bp board (Chris)
2019-04-26 13:50:00 -04:00
Tom Rini
1c64692df2 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2019-04-26 13:49:58 -04:00
Stefan Roese
c2ff69a444 watchdog: at91sam9_wdt: Remove now superfluous wdt start and reset
With the new generic function, the scattered other functions are now
removed to be replaced by the generic one. The new version also enables
the configuration of the watchdog timeout via the DT "timeout-sec"
property (if enabled via CONFIG_OF_CONTROL).

The watchdog servicing is enabled via CONFIG_WATCHDOG.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
2019-04-26 09:16:32 +02:00
Chris Packham
d55254ab77 ARM: kirkwood: add db-88f6281-bp board
This is Marvell's Kirkwood development board. It has the following
features

 - 512M DDR2
 - 2 PCI connectors
 - 1 x1 PCI-e interface
 - 1 Gigabit Ethernet Port
 - 2 SATA Ports
 - USB 2.0 Interface
 - SDIO
 - 128M NAND Flash
 - 16M SPI Flash

It can be strapped to boot from SPI or NAND so there are two defconfigs
(one per boot media).

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-26 07:35:38 +02:00
Stefan Roese
9408665709 arm: kirkwood: dts: Add openrd-* dtb makefile build targets
The following Kirkwood dtb build targets are currently missing:

kirkwood-openrd-base.dtb
kirkwood-openrd-client.dtb
kirkwood-openrd-ultimate.dtb

This patch adds them to the Makefile to fix the build error.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-26 07:35:38 +02:00
Pierre Bourdon
4ec9dd4071 mmc: mv_sdhci: add driver model support
The new DM implementation currently does not support the Sheeva
88SV331xV5 specific quirk present in the legacy implementation. The
legacy code is thus kept for this SoC and others not yet migrated to
DM_MMC.

Signed-off-by: Pierre Bourdon <delroth@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-26 07:35:38 +02:00
Pierre-Jean Texier
6b503f9e65 warp7: Switch to DM USB
This commit switches to DM USB for warp7 and warp7_bl33 defconfigs.

Signed-off-by: Pierre-Jean Texier <pjtexier@koncepto.io>
Signed-off-by: Joris Offouga <offougajoris@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-04-25 19:21:00 +02:00
Pierre-Jean Texier
0710726d04 warp7: Switch to DM Serial
This commit switches to DM SERIAL for warp7 and warp7_bl33 defconfigs.

Signed-off-by: Pierre-Jean Texier <pjtexier@koncepto.io>
Signed-off-by: Joris Offouga <offougajoris@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-04-25 19:20:32 +02:00
Marcel Ziswiler
d32273b91c ARM: dts: colibri-imx6ull: update device tree
Fix compatible node to use regular Toradex notation.
Annotate device tree with standard Colibri pin muxing comments.
Use open-drain I2C pin muxings.
Alphabetically re-order iomuxc nodes.
Rename snvs-ad7879-int-grp touch interrupt node as per Linux device tree.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-25 19:18:50 +02:00
Marcel Ziswiler
d487351959 ARM: dts: colibri-imx6ull: add osc32k_32k_out pinctrl
Add GPIO1_IO03__OSC32K_32K_OUT pin muxing.
While at it also fix indentation of pinfunc header file.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-25 19:18:46 +02:00
Marcel Ziswiler
7b69baea42 ARM: dts: i.MX6Q: fix avoid_unnecessary_addr_size warnings
Re-synced the device tree with Linux 5.0.

This fixes the following warnings:

w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/
 port@2/endpoint@0:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/
 port@2/endpoint@1:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/
 port@2/endpoint@2:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/
 port@2/endpoint@3:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/
 port@2/endpoint@4:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/
 port@3/endpoint@1:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/
 port@3/endpoint@2:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/
 port@3/endpoint@3:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/
 port@3/endpoint@4:reg: property has invalid length (4 bytes)
 (#address-cells == 2, #size-cells == 1)
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@0: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@0: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@1: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@1: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@2: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@2: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@3: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@3: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@4: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@2/endpoint@4: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@3/endpoint@1: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@3/endpoint@1: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@3/endpoint@2: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@3/endpoint@2: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@3/endpoint@3: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@3/endpoint@3: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@3/endpoint@4: Relying on default #address-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size):
 /soc/ipu@2800000/port@3/endpoint@4: Relying on default #size-cells
 value
w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size):
 Failed prerequisite 'avoid_default_addr_size'

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-25 19:16:24 +02:00
Parthiban Nallathambi
d8d33b6d4d imx: Add variscite DART-6UL Evaluation Kit
Port for the DART-6UL Evaluation Kit SBC. Based on the variscite
DART-6UL iMX6ULL SoM.

CPU:   Freescale i.MX6ULL rev1.1 900 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 43C
Reset cause: POR
Model: Variscite DART-6UL Evaluation Kit
Board: Variscite DART-6UL Evaluation Kit
DRAM:  512 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:    serial@02020000
Out:   serial@02020000
Err:   serial@02020000
Net:   FEC0

Working:
 - Eth0
 - i2c
 - MMC/SD
 - eMMC
 - USB host
 - UART 1

Note: LCDIF porting needs DM_VIDEO
https://lists.denx.de/pipermail/u-boot/2019-April/365506.html

Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>
2019-04-25 19:16:24 +02:00
Peng Fan
702339bdf4 imx: i.MX8MQ: clear ocotp error bit
In case ocotp error bit is set, clear it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 19:16:24 +02:00
Peng Fan
7a0c9b0888 imx: add lowlevel init for ARM64
Sometimes we met SERROR, but only to catch it when Linux boots up.
Let's enable catching in U-Boot to catch it ealier and ease debug.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 19:16:24 +02:00
Chris Packham
4eceb4bc8b ARM: imx: Fix typo in select option for ZMX25
Correct CPU_ARM926EJS1 to CPU_ARM926EJS.

Reported-by: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-04-25 19:16:24 +02:00
Filip Brozovic
8e10571f09 dts: imx6ull: add USB aliases to support DM
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
2019-04-25 19:16:24 +02:00
Joris Offouga
4e267b92fb pico-imx7d: Convert DM MMC
This patch enable convert DM MMC for imx7d-pico board and variant.

Before the DM conversion only usdhc3 was enabled and therefore it appeared
as MMC 0 to u-boot. After enabling MMC DM though usdhc3 defaults to MMC 2,
which left unattended would drive changes to existing pico-pi bootscripts and
environment variables that rely on mmc 0.

Setup the alias of mmc0 and usdhc3 so that existing pico-imx7d boot code will
work unmodified.

When converting to DM_MMC it is necessary that SPL initializes eMMC
by itself, so move the original eMMC initialization from U-Boot
proper to SPL.

Signed-off-by: Joris Offouga <offougajoris@gmail.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-04-25 19:16:24 +02:00
Marcel Ziswiler
270f1fb7b2 arm: dts: imx8dx: add lpuart1, lpuart2, lpuart3
Add support for lpuart1, lpuart2 and lpuart3.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-25 19:16:24 +02:00
Marcel Ziswiler
edcd4d1b88 misc: imx8: remove duplicates from scfw api
Remove duplicate function declarations from the SCFW API header file.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-25 19:16:24 +02:00
Joris Offouga
7c748933e3 Arm: imx7d-pico: Import all Linux device tree for Pico i.MX7D SOM
This patch imports the Linux kernel base board imx7d-pico.dtsi,
pi board imx7d-pico-pi.dts and hobbit board imx7d-pico-hobbit.dts
from Linux v5.1-rc1.

Signed-off-by: Joris Offouga <offougajoris@gmail.com>
2019-04-25 19:16:24 +02:00
Marcel Ziswiler
9233c3d377 ARM: dts: colibri-imx6ull: fix uart-has-rtscts property
Remove vendor pre-fix fsl, from uart-has-rtscts property.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-25 17:03:25 +02:00
Marcel Ziswiler
5d67b73c1a colibri-imx6ull: migrate fec to using driver model
Migrate Ethernet FEC to using driver model.
Drop PHY_MICREL_KSZ90X1 which slipped in from Apalis iMX6.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-25 17:03:25 +02:00
Marcel Ziswiler
87b32297f5 colibri-imx6ull: migrate usb to using driver model
Migrate USB to using driver model.
Add USBH_PEN GPIO regulator.
While at it also add alias e.g. as required for UMS.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-25 17:03:25 +02:00
Marcel Ziswiler
535800d33f colibri-imx6ull: migrate mmc to using driver model
Migrate MMC to using driver model.
Migrate USDHC to using pinctrl.
While at it also add GPIO1_IO03__OSC32K_32K_OUT pin muxing.
While at it also update copyright period.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-25 17:03:25 +02:00
Marcel Ziswiler
75b942df87 colibri_vf: fix ethernet by adding explicit phy node
The implicit fallback mechanism for searching the whole MDIO bus for at
least one PHY has been gone with the following commit b882005a18
("drivers/net/fec: phy_init: remove redundant logic"). This lead to the
Ethernet driver erroring out as follows:

Net:   Could not get PHY for FEC0: addr -19
eth-1: fec@400d1000
Colibri VFxx # dhcp
Could not get PHY for FEC0: addr -19
Could not get PHY for FEC0: addr -19
Could not get PHY for FEC0: addr -19
Could not get PHY for FEC0: addr -19
No ethernet found.
Could not get PHY for FEC0: addr -19
Colibri VFxx #

This commit adds an explicit PHY node which makes it work again.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-04-25 17:03:25 +02:00
Peng Fan
0d331c035a imx: support i.MX8QM MEK board
Add i.MX8QM MEK board support.
Included a basic dts, enabled SPL FIT

Boot log as below:
U-Boot SPL 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800)
Normal Boot
Trying to boot from MMC2_2

U-Boot 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800)

CPU:   NXP i.MX8QM RevB A53 at 142933 MHz

Model: Freescale i.MX8QM MEK
Board: iMX8QM MEK
Build: SCFW 9330215b
Boot:  SD1
DRAM:  6 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:    serial@5a060000
Out:   serial@5a060000
Err:   serial@5a060000
Net:
Error: ethernet@5b040000 address not set.
eth-1: ethernet@5b040000
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00
Peng Fan
4ba1b34dfe imx8: imx8-pins: add i.MX8QM
Add i.MX8QM entry

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00
Peng Fan
7f50af6090 imx8: add cpu support
Add cpu type and Kconfig entry

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00
Peng Fan
b18da229a3 arm: dts: introduce dtsi for i.MX8QM
Introduce basic dtsi for i.MX8QM, only support SDHC/FEC/LPUART.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00
Lukasz Majewski
13e7b72f32 ARM: defconfig: kp_imx53: Enable DM_USB support on HSC|DDC boards
This commit enables the DM_USB on HSC|DDC i.MX53 based boards.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-25 17:03:25 +02:00