This old patch was marked as deferred. Bring it back to life, to continue
towards the removal of common.h
Move this out of the common header and include it only where needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
For debug purpose, it should be useful to indicate the slew rate for
each pins.
Add ospeed register information for pins which are configured in
either alternate function or gpio output.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Add support for "st,stm32mp135-pinctrl" for STM32MP13x
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank
Example:
If GPIO bank have 16 GPIO pins [0-15].
In particular SoC's package case, some GPIO bank can have less GPIO pins:
- [0-10] => 11 pins;
- [2-7] => 6 pins.
Commit dbf928dd26 ("gpio: stm32f7: Add gpio bank holes management")
proposed a first implementation by not counting GPIO "inside" hole. GPIO
are not displaying correctly using gpio or pinmux command when GPIO holes
are located at the beginning of GPIO bank.
To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges
struct to indicate if a GPIO is mapped or not. GPIO uclass offers several
GPIO functions ("input", "output", "unused", "unknown" and "func"), use
"unknown" GPIO function to indicate that a GPIO is not mapped.
stm32_offset_to_index() is no more needed and removed.
This must be reflected using the "gpio" command to indicate to user
that a particular GPIO is not mapped (marked as "unknown") as shown below:
Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins
mapped):
GPIOI0 : unknown
GPIOI1 : unknown
GPIOI2 : analog
GPIOI3 : analog
GPIOI4 : alt function 0 push-pull pull-down
GPIOI5 : alt function 0 push-pull pull-down
GPIOI6 : alt function 0 push-pull pull-down
GPIOI7 : analog
GPIOI8 : unknown
GPIOI9 : unknown
GPIOI10 : unknown
GPIOI11 : unknown
GPIOI12 : unknown
GPIOI13 : unknown
GPIOI14 : unknown
GPIOI15 : unknown
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
GPIOF_UNKNOWN becomes a valid pin muxing information to indicate
that a pin is not mapped.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
pinmux_mode[] is linked to gpio_function[] defined in gpio-uclass.c
So reuse the same gpio_func_t enum value
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
The stm32 gpio driver private data are not needed in arch include files,
they are not used by code except for stm32 gpio and pincontrol drivers,
using the same IP; the defines for this IP is moved in a new file
"stm32_gpio_priv.h" in driver/gpio.
This patch avoids to have duplicated file gpio.h for each SOC
in MPU directory mach-stm32mp and in each MCU directory arch-stm32*
and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Bind only the enabled GPIO subnode, to avoid to probe the node
"gpio-controller" present in SOC dtsi (disabled by default) but
not enabled in the included pincontrol dtsi file.
For example, in stm32mp15xxac-pinctrl.dtsi 2 gpio bank are absent:
gpioj: gpio@5000b000
gpiok: gpio@5000c000
Then these GPIO are absent in output of command "dm tree" and
"gpio status -a"
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
OTYPE can be used for output or for alternate function to select
PP = push-pull or OP = open-drain mode, according reference manual
(Table 81. Port bit configuration table).
This patch removes this indication for input pins and adds it
for AF and output pins for pinmux command output.
Fixes: b305dbc08b ("pinctrl: stm32: display bias information for all pins")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change debug to log macro and define LOG_CATEGORY.
Remove "%s:" with __func__ as it is managed by log macro
(CONFIG_LOGF_FUNC)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.
Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
Display the bias information for input gpios or AF configuration,
and not only for output pin, as described in Reference manual
(Table 81. Port bit configuration table).
Fixes: da7a0bb1f2 ("pinctrl: stm32: add information on pin configuration")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Add information on pin configuration used for pinmux command:
- bias configuration for output (disable, pull up, pull down)
- otype for input (open drain or push pull)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.
Move the compatibility features into a separate header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Update .bind callback in order to bind all pinctrl subnodes
with "gpio-controller" property to gpio_stm32 driver.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
This patch solves the following warnings:
warning: comparison of unsigned expression < 0 is always false [-Wtype-limits]
if (*idx < 0)
^
drivers/pinctrl/pinctrl_stm32.c: At top level:
warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes]
int stm32_pinctrl_probe(struct udevice *dev)
^~~~~~~~~~~~~~~~~~~
Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Due to gpio holes management, stm32_pinctrl_get_gpio_dev() must
be updated.
stm32_pinctrl_get_gpio_dev() returns from a given pin selectors
the corresponding bank gpio device and the gpio_offset inside this
gpio bank.
Update also all functions which makes usage of stm32_pinctrl_get_gpio_dev.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Move gpio_dev list filling outside probe() to speed-up U-boot
boot sequence execution. This list is populated only when needed.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Protect configuration registers with a hardware spinlock.
If a hwspinlock is defined in the device-tree node used it
to be sure that none of the others processors on the SoC could
change the configuration at the same time.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Add get_pin_muxing() ops to obtain the pin muxing description
a given pin index.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add get_pin_name ops to obtain a pin name given a
pin index of a specified pin-controller.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add get_pins_count ops to obtain the number of pins
owns by a pin-controller.
On STM32 SoCs bindings, each pin-controller owns
several gpio banks. Each GPIO bank can own up to 16 pins.
To obtain the total pins count, walk through each sub-nodes
(ie GPIO banks) and sum each GPIO banks pins number. For that
in probe() we build a list with each GPIO device reference found.
This list will also be used with future get_pin_muxing and get_pin_name
ops to speed up and optimize walk through all GPIO banks.
As this code is common to all STM32 SoCs, this code is put
under SPL_BUILD compilation flag to avoid to increase SPL code size
for STM32F7 which is limited to 32Ko.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
- add the 2 new compatible used by STM32MP157
"st,stm32mp157-pinctrl"
"st,stm32mp157-z-pinctrl"
- update the mask for the port
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
STM32F4 SoCs uses the same pinctrl block as found into
STM32F7 and H7 SoCs.
We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl"
compatible string into pinctrl_stm32.c.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
U-Boot widely uses error() as a bit noisier variant of printf().
This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:
# define __compiletime_error(message) __attribute__((error(message)))
This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux. (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)
Let's convert error() into now treewide-available pr_err().
Done with the help of Coccinelle, excluing tools/ directory.
The semantic patch I used is as follows:
// <smpl>
@@@@
-error
+pr_err
(...)
// </smpl>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini <trini@konsulko.com>
STM32H7 SoCs uses the same pinctrl block as found into
STM32F7 SoCs
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
set_state_ops is kept under PINCTRL_FULL flag in order
to decrease memory footprint in some configuration.
PINCTRL_FULL can be enabled for debug purpose.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.
Signed-off-by: Simon Glass <sjg@chromium.org>
The number of pins to be configured could be more than 50 e.g. in case
of sdram controller, there are about 56 pins (32 data lines, 12 address
& some control signals).
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
With this gpio driver supporting DM, there is no need to enable clocks
for different gpios (for pin muxing) in the board specific code.
Need to increase the allocatable area required before relocation from 0x400 to
0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver uses the same pin control binding as that of linux, binding
document of this patch is copied from linux. One addition done is for
GPIO input and output mode configuration which was missing.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
