Commit graph

193 commits

Author SHA1 Message Date
Kumar Gala
8f29084a4f powerpc/fsl_pci: Fix device tree fixups for newer platforms
We assumed that only a small set of compatiable strings would be needed
to find the PCIe device tree nodes to be fixed up.  However on newer
platforms the simple rules no longer work.  We need to allow specifying
the PCIe compatiable string for each individual SoC.

We introduce CONFIG_SYS_FSL_PCIE_COMPAT for this purpose and set it if
the default isn't sufficient.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-05-20 00:48:41 -05:00
Steven A. Falco
644362c40a PPC405EX CHIP_21 erratum
APM errata CHIP_21 for the 405EX/EXr (from the rev 1.09 document dated
4/27/11) states that rev D processors may wake up with the wrong feature
set.  This patch implements the APM-proposed workaround.

To enable this patch for your board, add the appropriate define for your
CPU to your board header file.  See kilauea.h for more information.  The
following variants are supported:

#define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
#define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY

Please note that if you select the wrong define, your board will not
boot, and JTAG will be required to recover.

Tested on custom boards using:

CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY  <sfalco@harris.com>
CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY     <eibach@gdsys.de>

Signed-off-by: Steve Falco <sfalco@harris.com>
Acked-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2011-05-12 16:10:51 +02:00
Mingkai Hu
273feafefd powerpc: eSPI and eSPI controller support
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Singed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-29 07:34:09 -05:00
Kumar Gala
66412c6371 powerpc/85xx: Change timebase divisor to be defined per processor
Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because
different SoCs have different divisor amounts.  All the PQ3 parts are
/8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28 22:09:24 -05:00
Timur Tabi
d90fdba6ca powerpc/85xx: Implement work-around for P4080 erratum SERDES-A001
Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1
are swapped.

Erratum SERDES-A001 says that if bank two is kept disabled and after bank
three is enabled, then the PLL for bank three won't lock properly.  The
work-around is to enable and then disable bank two after bank three is
enabled.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28 22:09:23 -05:00
Timur Tabi
f68d306349 powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORA
Part of the SERDES9 erratum work-around is to set some bits in the SerDes
TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA.  The
current code does this only for XAUI, so extend it to the other protocols.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28 22:09:23 -05:00
Timur Tabi
da30b9fd97 powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005
SerDes PLL bandwidth default setting is incorrect when no lanes are
configured as PCI Express.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28 22:09:23 -05:00
Matthew McClintock
ae425c1eca powerpc/85xx: Don't set FT_FSL_PCI_SETUP if CONFIG_PCI is not set
A lot of boards set FT_FSL_PCI_SETUP directly in their board code
and don't check to see if CONFIG_PCI is actually defined. This
will cause the board compilation to fail if CONFIG_PCI is not
defined. The p1022ds board is one such example.

Instead of fixing every board this patch wraps FT_FSL_PCI_SETUP
around CONFIG_PCI so we can remove CONFIG_PCI and boards will
still build properly.

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:40:32 -05:00
Kim Phillips
416202f672 powerpc/85xx: handle both "secX.Y" and "sec-vX.Y" properties
versioned SEC properties changed names during development, so
for now search and update LIODNs for both "secX.Y" and
"sec-vX.Y" based properties.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:29:04 -05:00
Lei Xu
300097669c powerpc/85xx: Enable ESDHC111 erratum on P2040/P3041/P5010/P5020 SoCs
The workaround for ESDHC111 should also be applied on
P2040/P3041/P5010/P5020 SoCs.

Signed-off-by: Lei Xu <B33228@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:29:04 -05:00
Roy Zang
86221f09fb powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020
The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we
need to enable for them to function.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:29:04 -05:00
Kumar Gala
e02aea61cb powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code)
The P3041DS & P5020DS boards are almost identical (except for the
processor in them).  Additionally they are based on the P4080DS board
design so we use the some board code for all 3 boards.

Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have
meaning on P3041DS/P5020DS.  We utilize some of these for SERDES clock
configuration.

Additionally, the P3041DS/P5020DS support NAND.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:29:04 -05:00
Emil Medve
df8af0b4a6 p4080/serdes: Implement the XAUI workaround for SERDES9 erratum
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:29:04 -05:00
Emil Medve
3d28c5c8ed powerpc/85xx: fsl_corenet_serdes code rework
Rework and add some new APIs to the fsl_corenet_serdes code for use by
erratum and drivers.

* Rename serdes_get_bank() to serdes_get_bank_by_lane()
* Add serdes_get_first_lane returns which SERDES lane is used by device

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:29:04 -05:00
Haiying Wang
2a0ffb84c7 powerpc/85xx: Add device tree fixup for bman portal
Fix fdt bportal to pass the bman revision number to kernel via device tree.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:29:03 -05:00
Ramneek Mehresh
2bad42a0c8 powerpc/85xx: Add support for 2nd USB controller on p1_p2_rdb
Second USB controller only works for SPI and SD boot because of pin muxing

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2011-04-27 22:29:03 -05:00
Dipen Dudhat
4b77047c2a powerpc/85xx: Added PMUXCR1 and PMUXCR2 defines for P1010/P1014 SoC
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:29:03 -05:00
Timur Tabi
1fade70203 powerpc: fix implementation of out_8 to match the other out_XX functions
Signed-off-by: Timur Tabi <timur@freescale.com>
2011-04-28 00:55:16 +02:00
Andy Fleming
865ff85640 fsl: Change fsl_phy_enet_if to phy_interface_t
The fsl_phy_enet_if enum was, essentially, the phy_interface_t enum.
This meant that drivers which used fsl_phy_enet_if to deal with
PHY interfaces would have to convert between the two (or we would have
to have them mirror each other, and deal with the ensuing maintenance
headache). Instead, we switch all clients of fsl_phy_enet_if over to
phy_interface_t, which should become the standard, anyway.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-20 15:09:35 -05:00
Andy Fleming
063c12633d tsec: Convert tsec to use PHY Lib
This converts tsec to use the new PHY Lib.  All of the old PHY support
is ripped out.  The old MDIO driver is split off, and placed in
fsl_mdio.c.  The initialization is modified to initialize the MDIO
driver as well.  The powerpc config file is modified to configure PHYLIB
if TSEC_ENET is configured.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-20 15:09:34 -05:00
Priyanka Jain
32c8cfb23c fsl_esdhc: Deal with watermark level register related changes
P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark
level register description has been changed:

9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00
25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-10 11:17:55 -05:00
Jiang Yutang
b93f81a418 powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DS
For soc which have pin multiplex relation, some of them can't enable
simultaneously. This patch add environment var 'hwconfig' content
defination for them. you can enable some one function by setting
environment var 'hwconfig' content and reset board. Detail setting
please refer doc/README.p1022ds

Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-10 11:17:55 -05:00
Zhao Chenhui
4aa8405c91 powerpc/85xx: Add some defines & registers in immap_85xx.h
* Added SDHCDCR register to GUR struct
* Added SDHCDCR_CD_INV define related to SDHCDCR
* Added Pin Muxing define related to TDM on P102x

Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-05 10:18:39 -05:00
Haiying Wang
a52d2f816d powerpc/85xx: Add P1021 specific QE and UEC support
P1021 has some QE pins which need to be set in pmuxcr register before
using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and
UCC5 in Eth mode.  QE9 and QE12 are set for MII management. QE12 needs to
be released after MII access because QE12 pin is muxed with LBCTL signal.

Also added relevant QE support defines unique to P1021.

The P1021 QE is shared on P1012, P1016, and P1025.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-05 10:18:39 -05:00
Zhao Chenhui
c1fc2d4fc2 powerpc/85xx: don't init SDRAM when CONFIG_SYS_RAMBOOT
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Acked-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-05 10:18:39 -05:00
Laurentiu TUDOR
33e683541e powerpc/85xx: Fix setting of LIODN prop in PCIe nodes on P3041/P5020
We utilize the compatible string to find the node to add fsl,liodn
property to.  However P3041 & P5020 don't have "fsl,p4080-pcie"
compatible for their PCIe controllers as they aren't backwards compatible.

Allow the macro's to specify the PCIe compatible to use to allow SoC
uniqueness.  On P3041 & P5020 we utilize "fsl,qoriq-pcie-v2.2" for the
PCIe controllers.

Signed-off-by: Laurentiu TUDOR <Laurentiu.Tudor@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:43 -05:00
Kumar Gala
b5c8753fa1 powerpc/85xx: Fixup determining PME, FMan freq
On CoreNet based SoCs (P2040, P3041, P4080, P5020) we have some
additional rules to determining the various frequencies that PME & FMan
IP blocks run at.

We need to take into account:
* Reduced number of Core Complex PLL clusters
* HWA_ASYNC_DIV (allows for /2 or /4 options)

On P2040/P3041/P5020 we only have 2 Core Complex PLLs and in such SoCs
the PME & FMan blocks utilize the second Core Complex PLL.  On SoCs
like p4080 with 4 Core Complex PLLs we utilize the third Core Complex
PLL for PME & FMan blocks.

On P2040/P3041/P5020 we have the added feature that we can divide the
PLL down further by either /2 or /4 based on HWA_ASYNC_DIV.  On P4080
this options doesn't exist, however HWA_ASYNC_DIV field in RCW should be
set to 0 and this gets a backward compatiable /2 behavior.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:43 -05:00
Kumar Gala
c657d898bc powerpc/85xx: Specify CONFIG_SYS_FM_MURAM_SIZE
CONFIG_SYS_FM_MURAM_SIZE varies from SoC to SoC to specify it in
config_mpc85xx.h for those parts with a Frame Manager.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:42 -05:00
Poonam Aggrwal
1fbf3483b7 powerpc/85xx: Adds some P1010/P1014 SoC configuration defines
Add defines for FSL_SATA_V2, # of DDR controllers, reset value of CCSRBAR
and SDHC erratum.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:42 -05:00
Kumar Gala
093cffbe9a powerpc/85xx: Support for Freescale P1024/P1025 processor
Add Support for Freescale P1024/P1025 (dual core) and
P1015/P1016 (single core) processors.

P1024 is a variant of P1020 processor with a core frequency from
400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA

P1025 is a variant of P1021 processor with a core frequency from
400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA

P1015 is a variant of P1024 processor with single core and P1016 is a
variant of P1025 processor with single core.

Added comments in config_mpc85xx.h to denote single core versions of
processors.

Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:42 -05:00
Poonam Aggrwal
0b3b1766b7 fsl_ddr: Adds 16 bit DDR Data width option
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:41 -05:00
Prabhakar Kushwaha
b6ccd2c9de fsl_pci: Add support for FSL PCIe controllers v2.x
FSL PCIe controller v2.1:
	- New MSI inbound window
	- Same Inbound windows address as PCIe controller v1.x

Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window

FSL PCIe controller v2.2 and v2.3:
	- Different addresses for PCIe inbound window 3,2,1
	- Exposed PCIe inbound window 0
	- New PCIe interrupt status register

Added new Interrupt Status register to struct ccsr_pci & updated pit_t array
size to reflect the 4 inbound windows.

To maintain backward compatiblilty, on V2.2 or greater controllers we
start with inbound window 1 and leave inbound 0 with its default value
(which maps to CCSRBAR).

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:41 -05:00
Haiying Wang
24995d829a powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs
There are some differences between CoreNet (P2040, P3041, P5020, P4080)
and and non-CoreNet (P1017, P1023) based SoCs in what features exist and
the memory maps.

* Rename various immap defines to remove _CORENET_ if they are shared
* Added P1023/P1017 specific memory offsets
* Only setup LIODNs or LIODN related code on CORENET based SoCs
  (features doesn't exist on P1023/P1017)

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:41 -05:00
Roy Zang
67a719da2e powerpc/85xx: Add support for Freescale P1023/P1017 Processors
Add P1023 (dual core) & P1017 (single core) specific information:
* SERDES Table
* Added P1023/P1017 to cpu_type_list and SVR list
  (fixed issue with P1013 not being sorted correctly).
* Added P1023/P1027 to config_mpc85xx.h
* Added new LAW type introduced on P1023/P1017
* Updated a few immap register/defines unique to P1023/P1017

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:41 -05:00
Kumar Gala
fdb4dad31e powerpc/85xx: Cleanup some QE related defines
Move some processor specific QE defines into config_mpc85xx.h and use
QE_MURAM_SIZE to cleanup some ifdef mess in the QE immap struct.

Also fixed up some comment style issues in immap_qe.h

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:41 -05:00
Kumar Gala
fbee0f7f09 powerpc/85xx: Add some defines for P2040, P3041, P5010, P5020
Specify the number of DDR controllers, number of frame managers, number
of 1g and 10g ports.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:40 -05:00
Kumar Gala
f0f899432e powerpc/85xx: Declare fsl_ddr_set_memctl_regs in <asm/fsl_ddr_sdram.h>
Remove declerations of fsl_ddr_set_memctl_regs in board files with and
place it into a common header.

Based on patch from Poonam Aggrwal.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:40 -05:00
Dipen Dudhat
d789b5f5bc powerpc/85xx: Add support for Integrated Flash Controller (IFC)
The Integrated Flash Controller (IFC) is used to access the external
NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip
selects are provided in IFC so that maximum of four Flash devices can be
hooked, but only one can be accessed at a given time.

Features supported by IFC are,
        - Functional muxing of pins between NAND, NOR and GPCM
        - Support memory banks of size 64KByte to 4 GBytes
        - Write protection capability (only for NAND and NOR)
        - Provision of Software Reset
        - Flexible Timing programmability for every chip select
        - NAND Machine
                - x8/ x16 NAND Flash Interface
                - SLC and MLC NAND Flash devices support with
                  configurable
                  page sizes of upto 4KB
                - Internal SRAM of 9KB which is directly mapped and
                  availble at
                  boot time for NAND Boot
                - Configurable block size
                - Boot chip select (CS0) available at system reset
        - NOR Machine
                - Data bus width of 8/16/32
                - Compatible with asynchronous NOR Flash
                - Directly memory mapped
                - Supports address data multiplexed (ADM) NOR device
                - Boot chip select (CS0) available at system reset
        - GPCM Machine (NORMAL GPCM Mode)
                - Support for x8/16/32 bit device
                - Compatible with general purpose addressable device
                  e.g. SRAM, ROM
                - External clock is supported with programmable division
                  ratio
        - GPCM Machine (Generic ASIC Mode)
                - Support for x8/16/32 bit device
                - Address and Data are shared on I/O bus
                - Following Address and Data sequences can be supported
                  on I/O bus
                       - 32 bit I/O: AD
                       - 16 bit I/O: AADD
                       - 8 bit I/O : AAAADDDD
                - Configurable Even/Odd Parity on Address/Data bus
                  supported

Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:40 -05:00
Prabhakar Kushwaha
28747f9bb1 powerpc/85xx: Add SERDES support for P1010/P1014
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are only
ever connected on SERDES.

Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:40 -05:00
Prabhakar Kushwaha
b03a466d6c powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs
The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe.  Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-29 07:41:37 -05:00
Jiang Yutang
2d7534a344 powerpc/85xx: Enable various errata on P1022/P1013 SoCs
Enable workaround for errata ELBC A001, ESDHC 111 & SATA A001 on
P1022/P1013 SoCs.

Also updated P1022DS config to properly enable CONFIG_FSL_SATA_V2.

Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-28 09:04:26 -05:00
York Sun
08b3f7599f powerpc/mpc8xxx: fix recognition of DIMMs with ECC and Address Parity
To recognize DIMMs with ECC capability by testing ECC bit only. Not to be
confused by Address Parity bit.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-24 09:20:49 -05:00
Wolfgang Denk
fced09ae38 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2011-02-09 20:50:26 +01:00
Dirk Eibach
2da0fc0d0f ppc4xx: Add DLVision-10G board support
Board support for the Guntermann & Drunck DLVision-10G.
Adds support for multiple FPGAs per board for gdsys 405ep
architecture.
Adds support for dual link osd hardware for gdsys 405ep.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2011-02-07 11:13:16 +01:00
York Sun
91671913f7 powerpc/mpc85xx: implement workaround for errata DDR111 and DDR134
Workaround for the following errata:
DDR111 - MCKE signal may not function correctly at assertion of HRESET
DDR134 - The automatic CAS-to-Preamble feature of the DDR controller can
         calibrate to incorrect values

These two workarounds must be implemented together because they touch
common registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-03 02:46:13 -06:00
York Sun
eb0aff77c8 powerpc/85xx: Rename MPC8572 DDR erratum to DDR115
Use unique erratum number instead of platform number.
Enable command that reports errata on MPC8572DS.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-03 02:46:13 -06:00
Kumar Gala
5103a03a0b fsl_esdhc: Add the workaround for erratum ESDHC-A001 (enable on P2020)
Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 4, 8,
and 12. Program one more than the desired value: 4 -> 5, 8 -> 9, 12 -> 13.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-03 02:46:12 -06:00
Kumar Gala
6e7f0bc0ce powerpc/85xx: Enable ESDHC111 Erratum on P2010/P2020 SoCs
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-03 02:46:12 -06:00
Wolfgang Denk
d1a24f0618 Minor Coding Style Cleanup.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-02-02 22:36:10 +01:00
York Sun
6b06d7dc07 corenet_ds: Extend board specific parameters
Extend board specific parameters to include cpo, write leveling override
Extend write leveling sample to 0xf
Adding rcw overrid for quad-rank RDIMMs

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:24 -06:00
York Sun
fa8d23c0ee mpc85xx: Implement workaround for erratum DDR-A003
Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM.
Also adding polling after enabling DDR controller to ensure completion.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:24 -06:00
York Sun
e1fd16b6f5 mpc85xx: Enable unique mode registers and dynamic ODT for DDR3
Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version
(major, minor, errata) to determine if unique mode registers are available.
If true, always use unique mode registers. Dynamic ODT is enabled if needed.
The table is documented in doc/README.fsl-ddr. This function may also need
to be extend for future other platforms if such a feature exists.

Enable address parity and RCW by default for RDIMMs.

Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for
quad-rank RDIMMs.

Use a formula to calculate rodt_on for timing_cfg_5.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00
York Sun
d2a9568c57 mpc85xx: Adding more registers and options
This patch exposes more registers which can be used by the DDR drivers or
interactive debugging. U-boot doesn't use all the registers in DDRC.
When advanced tuning is required, writing to those registers is needed.

Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers
Add options to override rcw, address parity to RDIMMs.
Use array for debug registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00
Kumar Gala
243be8e296 powerpc/8xxx: Introduce 85xx, 86xx, QorIQ config headers
Add new headers that capture common defines for a given SoC/processor
rather than duplicating that information in board config.h and random
other places.

Eventually this should be handled by Kconfig & defconfigs

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
2011-01-19 22:58:23 -06:00
Kumar Gala
f193e3da98 powerpc/p2040: Add various p2040 specific information
Add P2040 SoC specific information:
* SERDES Table
* Added p2040 to cpu_type_list and SVR list
* Added number of LAWs for p2040
* Set CONFIG_MAX_CPUS to 4 for p2040

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00
Poonam Aggrwal
b5debec5b5 powerpc/85xx: Add Support for Freescale P1014 Processor
The P1014 is similar to the P1010 processor with the following differences:

- 16bit DDR with ECC. (P1010 has 32bit DDR w/o ECC)
- no eCAN interface. (P1010 has 2 eCAN interfaces)
- Two SGMII interface (P1010 has 3 SGMII)
- No secure boot

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00
Poonam Aggrwal
b8cdd01462 powerpc/85xx: Add Support for Freescale P1010 Processor
Key Features include of the P1010:
* e500v2 core frequency operation of 500 to 800 MHz
* Power consumption less than 5.0 W at 800 MHz core speed
* Dual SATA 3 Gbps controllers with integrated PHY
* Dual PCI Express controllers
* Three 10/100/1000 Mbps enhanced triple-speed Ethernet controllers (eTSECs)
	* TCP/IP acceleration and classification capabilities
	* IEEE 1588 support
	* Lossless flow control
	* RGMII, SGMII
* DDR3 with support for a 32-bit data interface (40 bits including ECC),
  up to 800 MHz data rate 32/16-bit DDR3 memory controller
* Dedicated security engine featuring trusted boot
* TDM interface
* Dual controller area networks (FlexCAN) controller
* SD/MMC card controller supporting booting from Flash cards
* USB 2.0 host and device controller with an on-chip, high-speed PHY
* Integrated Flash controller (IFC)
* Power Management Controller (PMC)
* Four-channel, general-purpose DMA controller
* I2C controller
* Serial peripheral interface (SPI) controller with master and slave support
* System timers including a periodic interrupt timer, real-time clock,
  software watchdog timer, and four general-purpose timers
* Dual DUARTs

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:23 -06:00
Prabhakar
17028be238 Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR
CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as
CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET.
It should be as
CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2011-01-19 22:58:23 -06:00
Kumar Gala
f133796da8 powerpc/85xx: Add the workaround for erratum ELBC-A001 (enable on P4080)
Simultaneous FCM and GPCM or UPM operation may erroneously trigger bus
monitor timeout.  Set timeout to maximum to avoid.

Based on a patch from Lan Chunhe <b25806@freescale.com>

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:22 -06:00
Kumar Gala
868da5936e powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080)
CoreNet Platform Cache single-bit data error scrubbing will cause data
corruption.  Disable the feature to workaround the issue.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:22 -06:00
Kumar Gala
1d2c2a62e3 powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080)
CoreNet Platform Cache single-bit tag error scrubbing will cause tag
corruption.  Disable the feature to workaround the issue.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:22 -06:00
Kumar Gala
3dbd5d7d7e powerpc/8xxx: Move fsl_is_spd() into generic 8xxx ddr code
Move the parsing of hwconfig to determine if to use spd into common code
so we can share it across all boards instead of duplicating it
everywhere.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:22 -06:00
Kumar Gala
5655136208 powerpc/86xx: Enable common SRIO init code
Add the needed defines and code to utilize the common 8xxx srio init
code to setup LAWs and modify device tree if we have SRIO enabled on a
board.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:21 -06:00
Kumar Gala
a09b9b68d4 powerpc/8xxx: Refactor SRIO initialization into common code
Moved the SRIO init out of corenet_ds and into common code for
8xxx/QorIQ processors that have SRIO.  We mimic what we do with PCIe
controllers for SRIO.

We utilize the fact that SRIO is over serdes to determine if its
configured or not and thus can setup the LAWs needed for it dynamically.

We additionally update the device tree (to remove the SRIO nodes) if the
board doesn't have SRIO enabled.

Introduced the following standard defines for board config.h:

CONFIG_SYS_SRIO - Chip has SRIO or not
CONFIG_SRIO1 - Board has SRIO 1 port available
CONFIG_SRIO2 - Board has SRIO 2 port available

(where 'n' is the port #)
CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot
CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup)
CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)

[ These mimic what we have for PCI and PCIe controllers ]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
2011-01-14 01:32:21 -06:00
Peter Tyser
213ac73e2c fsl_pci: Update PCIe boot ouput
This change does the following:
- Adds printing of negotiated link width.  This information can be
  useful when debugging PCIe issues.
- Makes it optional for boards to implement board_serdes_name().
  Previously boards that did not implement it would print unsightly
  output such as "PCIE1: Connected to <NULL>..."
- Rewords the PCIe boot output to reduce line length and to make it
  clear that the "base address XYZ" value refers to the base address of
  the internal processor PCIe registers and not a standard PCI BAR
  value.
- Changes "PCIE" output to the standard "PCIe"

Before change:
PCIE1: connected to <NULL> as Root Complex (base addr ef008000)
  01:00.0     - 10b5:8518 - Bridge device
   02:01.0    - 10b5:8518 - Bridge device
   02:02.0    - 10b5:8518 - Bridge device
   02:03.0    - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 05
PCIE2: connected to <NULL> as Endpoint (base addr ef009000)
PCIE2: Bus 06 - 06

After change:
PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000
  01:00.0     - 10b5:8518 - Bridge device
   02:01.0    - 10b5:8518 - Bridge device
   02:02.0    - 10b5:8518 - Bridge device
   02:03.0    - 10b5:8518 - Bridge device
PCIe1: Bus 00 - 05
PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000
PCIe2: Bus 06 - 06

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:21 -06:00
Kumar Gala
a4aafcc990 powerpc/fsl-pci: Add generic code to setup PCIe controllers
Since all the PCIe controllers are connected over SERDES on the SoCs we
can utilize is_serdes_configured() to determine if a controller is
enabled.  After which we can setup the ATMUs and LAWs for the controller
in a common fashion and allow board code to specify what the controller
is connected to for reporting reasons.

We also provide a per controller (rather than all) for some systems that
may have special requirements.

Finally, we refactor the code used by the P1022DS to utilize the new
generic code.

Based on patch by: Li Yang <leoli@freescale.com>

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:19 -06:00
Kumar Gala
3a0e3c27a5 powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup
Previously we passed in a specifically named struct pci_controller to
determine if we had setup the particular PCI bus.  Now we can search for
the struct so we dont have to depend on the name or the struct being
statically allocated.

Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct
back by searching for it means we can do things like dynamically allocate
them or not have to expose the static structures to all users.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
2011-01-14 01:32:19 -06:00
Becky Bruce
70961ba414 mpc85xx: rename sdram_init() lbc_sdram_init()
sdram_init() is used to initialize sdram on the lbc.  Rename it
accordingly.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:19 -06:00
Becky Bruce
38dba0c2ff mpc85xx boards: initdram() cleanup/bugfix
Correct initdram to use phys_size_t to represent the size of
dram; instead of changing this all over the place, and correcting
all the other random errors I've noticed, create a
common initdram that is used by all non-corenet 85xx parts.  Most
of the initdram() functions were identical, with 2 common differences:

1) DDR tlbs for the fixed_sdram case were set up in initdram() on
some boards, and were part of the tlb_table on others.  I have
changed them all over to the initdram() method - we shouldn't
be accessing dram before this point so they don't need to be
done sooner, and this seems cleaner.

2) Parts that require the DDR11 erratum workaround had different
implementations - I have adopted the version from the Freescale
errata document.  It also looks like some of the versions were
buggy, and, depending on timing, could have resulted in the
DDR controller being disabled.  This seems bad.

The xpedite boards had a common/fsl_8xxx_ddr.c; with this
change only the 517 board uses this so I have moved the ddr code
into that board's directory in xpedite517x.c

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:19 -06:00
Kumar Gala
5d27e02c04 powerpc/8xxx: Replace is_fsl_pci_cfg with is_serdes_configured
Now that we have serdes support for all 85xx/86xx/Pxxx chips we can
replace the is_fsl_pci_cfg() code with the is_serdes_configured().

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:19 -06:00
Piergiorgio Beruto
afabe4b94e powerpc/85xx: Fix wrong SVR value for MPC8567 and MPC8567E processors
Signed-off-by: Piergiorgio Beruto <piergiorgio.beruto@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-14 01:32:18 -06:00
Wolfgang Denk
2e5167ccad Replace CONFIG_RELOC_FIXUP_WORKS by CONFIG_NEEDS_MANUAL_RELOC
By now, the majority of architectures have working relocation
support, so the few remaining architectures have become exceptions.
To make this more obvious, we make working relocation now the default
case, and flag the remaining cases with CONFIG_NEEDS_MANUAL_RELOC.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
Tested-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2010-10-29 21:32:07 +02:00
Wolfgang Denk
25ddd1fb0a Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not
being able to use "sizeof(struct global_data)" in assembler files.
Recent experience has shown that manual synchronization is not
reliable enough.  This patch renames CONFIG_SYS_GBL_DATA_SIZE into
GENERATED_GBL_DATA_SIZE which gets automatically generated by the
asm-offsets tool.  In the result, all definitions of this value can be
deleted from the board config files.  We have to make sure that all
files that reference such data include the new <asm-offsets.h> file.

No other changes have been done yet, but it is obvious that similar
changes / simplifications can be done for other, related macro
definitions as well.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2010-10-26 21:05:30 +02:00
York Sun
28a966715b Adding fixed sdram setting for cornet_ds board
800, 900, 1000, 1200MT/s data rate parameters are added for fixed sdram
setting. SPD based parameters and fixed parameters can be toggled by hwconfig.
To use fixed parameters,

hwconfig=fsl_ddr:sdram=fixed

To use SPD parameters,

hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-10-20 02:38:39 -05:00
Kumar Gala
a1964ea5c2 powerpc/8xxx: Add fdt_fixup_phy_connection helper
Add a common helper that will set the PHY connection type based on enum.
We use this on eTSEC, UCC, and will with Fman in the future.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-10-20 02:27:18 -05:00
Kumar Gala
f8c42495e0 powerpc/fsl: Introduce common enum for PHY types
Have a common enum for phy types that we use in the UCC driver.  We will
also use this enum for dealing with phy connection fixup in the device
tree.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-10-20 02:27:18 -05:00
John Rigby
fca43cc801 boot: change some arch ifdefs to feature ifdefs
The routines boot_ramdisk_high, boot_get_cmdline and boot_get_kbd
are currently enabled by various combinations of CONFIG_M68K,
CONFIG_POWERPC and CONFIG_SPARC.

Use CONFIG_SYS_BOOT_<FEATURE> defines instead.

CONFIG_SYS_BOOT_RAMDISK_HIGH
CONFIG_SYS_BOOT_GET_CMDLINE
CONFIG_SYS_BOOT_GET_KBD

Define these as appropriate in arch/include/asm/config.h files.

Signed-off-by: John Rigby <john.rigby@linaro.org>
Acked-by: Wolfgang Denk <wd@denx.de>
2010-10-18 22:53:32 +02:00
Peter Tyser
d98b0523cf powerpc: Cleanup BOOTFLAG_* references
Now that warm booting is not supported, there isn't a need for the
BOOTFLAG_COLD and BOOTFLAG_WARM defines, so remove them.

Note that this change makes the board info bd_bootflags field useless.
It will always be set to 0, but we leave it around so that we don't
break the board info structure that some OSes are expecting to be passed
from U-Boot.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-10-18 22:38:56 +02:00
Damien Dusha
29c6fbe047 MPC5121: Add USB EHCI support
Signed-off-by: Francesco Rendine <francesco.rendine@valueteam.com>
Signed-off-by: Damien Dusha <d.dusha@gmail.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>

Coding style cleanup; slight file restructuring.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Remy Bohmer <linux@bohmer.net>
2010-10-18 22:33:32 +02:00
Kumar Gala
3c6a22b962 powerpc/p4080: Add new CPC register - HDBCR0
Manual was updated to add a new register for disabling CDQ speculation.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-10-07 09:49:47 -05:00
Stefan Roese
eb011d27aa ppc4xx: Remove some testing hacks from ppc4xx.h
I accidentally left these hacks in the code while doing the big header
cleanup. Let's remove it now.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-10-04 11:20:11 +02:00
Stefan Roese
c96be63aab ppc4xx: Add defines for COM3 & COM4 (UART2 & UART3) on 440EPx/GRx
Signed-off-by: Stefan Roese <sr@denx.de>
2010-10-04 11:19:43 +02:00
Tirumala Marri
1b8fec1393 APM821xx: Add CPU support
APM821XX is a new line of SoCs which are derivatives of
PPC44X family of processors. This patch adds support of CPU, cache,
tlb, 32k ocm, bootstraps, PLB and AHB bus.

Signed-off-by: Tirumala R Marri <tmarri@apm.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2010-10-04 11:15:02 +02:00
Stefan Roese
550650ddd0 ppc4xx: Use common NS16550 driver for PPC4xx UART
This patch removes the PPC4xx UART driver. Instead the common NS16550
driver is used, since all PPC4xx SoC's use this peripheral device.

The file 4xx_uart.c now only implements the UART clock calculation
function which also sets the SoC internal UART divisors.

All PPC4xx board config headers are changed to use this common NS16550
driver now.

Tested on these boards:
acadia, canyonlands, katmai, kilauea, sequoia, zeus

Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-23 09:02:05 +02:00
Stefan Roese
afabb498b7 ppc4xx: Big header cleanup part 2, mostly PPC405 related
This cleanup is done by creating header files for all SoC versions and
moving the SoC specific defines into these special headers. This way the
common header ppc405.h and ppc440.h can be cleaned up finally.

As a part from this cleanup, the GPIO definitions for PPC405EP are
corrected. The high and low parts of the registers (for example
CONFIG_SYS_GPIO0_OSRL vs. CONFIG_SYS_GPIO0_OSRH) have been defined in
the wrong order. This patch now fixes this issue by switching these
xxxH and xxxL values. This brings the GPIO 405EP port in sync with all
other PPC4xx ports.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-23 09:02:05 +02:00
Stefan Roese
5e7abce991 ppc4xx: Big header cleanup, mostly PPC440 related
This patch starts a bit PPC4xx header cleanup. First patch mostly
touches PPC440 files. A later patch will touch the PPC405 files as well.

This cleanup is done by creating header files for all SoC versions and
moving the SoC specific defines into these special headers. This way the
common header ppc405.h and ppc440.h can be cleaned up finally.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-23 09:02:05 +02:00
Stefan Roese
0988776288 ppc4xx: Move gpio.h to ppc4xx-gpio.h since its ppc4xx specific
Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-23 09:02:05 +02:00
Stefan Roese
b36df56115 ppc4xx: Move ppc4xx headers to powerpc include directory
This patch moves some ppc4xx related headers from the common include
directory (include/) to the powerpc specific one
(arch/powerpc/include/asm/). This way to common include directory is not
so cluttered with files.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-23 09:02:05 +02:00
Wolfgang Denk
ea882baf9c New implementation for internal handling of environment variables.
Motivation:

* Old environment code used a pessimizing implementation:
  - variable lookup used linear search => slow
  - changed/added variables were added at the end, i. e. most
    frequently used variables had the slowest access times => slow
  - each setenv() would calculate the CRC32 checksum over the whole
    environment block => slow
* "redundant" envrionment was locked down to two copies
* No easy way to implement features like "reset to factory defaults",
  or to select one out of several pre-defined (previously saved) sets
  of environment settings ("profiles")
* No easy way to import or export environment settings

======================================================================

API Changes:

- Variable names starting with '#' are no longer allowed

  I didn't find any such variable names being used; it is highly
  recommended to follow standard conventions and start variable names
  with an alphanumeric character

- "printenv" will now print a backslash at the end of all but the last
  lines of a multi-line variable value.

  Multi-line variables have never been formally defined, allthough
  there is no reason not to use them. Now we define rules how to deal
  with them, allowing for import and export.

- Function forceenv() and the related code in saveenv() was removed.
  At the moment this is causing build problems for the only user of
  this code (schmoogie - which has no entry in MAINTAINERS); may be
  fixed later by implementing the "env set -f" feature.

Inconsistencies:

- "printenv" will '\\'-escape the '\n' in multi-line variables, while
  "printenv var" will not do that.

======================================================================

Advantages:

- "printenv" output much better readable (sorted)
- faster!
- extendable (additional variable properties can be added)
- new, powerful features like "factory reset" or easy switching
  between several different environment settings ("profiles")

Disadvantages:

- Image size grows by typically 5...7 KiB (might shrink a bit again on
  systems with redundant environment with a following patch series)

======================================================================

Implemented:

- env command with subcommands:

  - env print [arg ...]

    same as "printenv": print environment

  - env set [-f] name [arg ...]

    same as "setenv": set (and delete) environment variables

    ["-f" - force setting even for read-only variables - not
    implemented yet.]

  - end delete [-f] name

    not implemented yet

    ["-f" - force delete even for read-only variables]

  - env save

    same as "saveenv": save environment

  - env export [-t | -b | -c] addr [size]

    export internal representation (hash table) in formats usable for
    persistent storage or processing:

	-t:	export as text format; if size is given, data will be
		padded with '\0' bytes; if not, one terminating '\0'
		will be added (which is included in the "filesize"
		setting so you can for exmple copy this to flash and
		keep the termination).
	-b:	export as binary format (name=value pairs separated by
		'\0', list end marked by double "\0\0")
	-c:	export as checksum protected environment format as
		used for example by "saveenv" command
	addr:	memory address where environment gets stored
	size:	size of output buffer

	With "-c" and size is NOT given, then the export command will
	format the data as currently used for the persistent storage,
	i. e. it will use CONFIG_ENV_SECT_SIZE as output block size and
	prepend a valid CRC32 checksum and, in case of resundant
	environment, a "current" redundancy flag. If size is given, this
	value will be used instead of CONFIG_ENV_SECT_SIZE; again, CRC32
	checksum and redundancy flag will be inserted.

	With "-b" and "-t", always only the real data (including a
	terminating '\0' byte) will be written; here the optional size
	argument will be used to make sure not to overflow the user
	provided buffer; the command will abort if the size is not
	sufficient. Any remainign space will be '\0' padded.

        On successful return, the variable "filesize" will be set.
        Note that filesize includes the trailing/terminating '\0'
        byte(s).

        Usage szenario: create a text snapshot/backup of the current
	settings:

		=> env export -t 100000
		=> era ${backup_addr} +${filesize}
		=> cp.b 100000 ${backup_addr} ${filesize}

	Re-import this snapshot, deleting all other settings:

		=> env import -d -t ${backup_addr}

  - env import [-d] [-t | -b | -c] addr [size]

    import external format (text or binary) into hash table,
    optionally deleting existing values:

	-d:	delete existing environment before importing;
		otherwise overwrite / append to existion definitions
	-t:	assume text format; either "size" must be given or the
		text data must be '\0' terminated
	-b:	assume binary format ('\0' separated, "\0\0" terminated)
	-c:	assume checksum protected environment format
	addr:	memory address to read from
	size:	length of input data; if missing, proper '\0'
		termination is mandatory

  - env default -f

    reset default environment: drop all environment settings and load
    default environment

  - env ask name [message] [size]

    same as "askenv": ask for environment variable

  - env edit name

    same as "editenv": edit environment variable

  - env run

    same as "run": run commands in an environment variable

======================================================================

TODO:

- drop default env as implemented now; provide a text file based
  initialization instead (eventually using several text files to
  incrementally build it from common blocks) and a tool to convert it
  into a binary blob / object file.

- It would be nice if we could add wildcard support for environment
  variables; this is needed for variable name auto-completion,
  but it would also be nice to be able to say "printenv ip*" or
  "printenv *addr*"

- Some boards don't link any more due to the grown code size:
  DU405, canyonlands, sequoia, socrates.

	=> cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>,
	       Stefan Roese <sr@denx.de>,
	       Heiko Schocher <hs@denx.de>

- Dropping forceenv() causes build problems on schmoogie

	=> cc: Sergey Kubushyn <ksi@koi8.net>

- Build tested on PPC and ARM only; runtime tested with NOR and NAND
  flash only => needs testing!!

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>,
Cc: Stefan Roese <sr@denx.de>,
Cc: Heiko Schocher <hs@denx.de>
Cc: Sergey Kubushyn <ksi@koi8.net>
2010-09-19 19:29:48 +02:00
Wolfgang Denk
91a76751a0 Make getenv() work before relocation.
So far, getenv() would work before relocation is most cases, even
though it was not intended to be used that way.  When switching to a
hash table based implementation, this would break a number of boards.

For convenience, we make getenv() check if it's running before
relocation and, if so, use getenv_f() internally.

Note that this is limited to simple cases, as we use a small static
buffer (32 bytes) in the global data for this purpose.

For this reason, it is also not a good idea to convert all current
uses of getenv_f() into getenv() - some of the existing use cases need
to be able to deal with longer variable values, so getenv_f() is still
needed and recommended for use before relocation.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-09-19 19:29:48 +02:00
Kumar Gala
ed062e0f6c powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs
Official docs call it the Job Ring not Job Queue for the p4080 security
block.  Match the docs to reduce confusion.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-08-19 02:06:13 -05:00
Kim Phillips
680c613a5c powerpc/8xxx: share PIC defines among 85xx and 86xx
fixes breakeage introduced by commit
a37c36f4e7 "powerpc/8xxx: query
feature reporting register for num cores on unknown cpus"

Reported-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-08-19 02:06:13 -05:00
Wolfgang Denk
fe8d63c8c7 Merge branch 'master' of git://git.denx.de/u-boot-marvell 2010-08-10 22:37:27 +02:00
Albert Aribaud
f2a37fcd9b ide: add configuration
CONFIG_IDE_SWAP_IO

This configuration option replaces a complex conditional
in cmd_ide.c with an explicit define to be added to SoC or
board configs.

Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
2010-08-08 05:17:05 +05:30
Kim Phillips
a37c36f4e7 powerpc/8xxx: query feature reporting register for num cores on unknown cpus
doing so helps avant garde users, such as those using simulators that
allow users to configure the number of cores, so as to not have to
manually adjust u-boot sources.  h/w should also be reliably setting
FRR NCPU in the future.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-08-01 11:18:45 -05:00
york
9490ff4864 powerpc/8xxx: Enable DDR3 RDIMM support
Enabled registered DIMMs using data from SPD. RDIMMs have registers
which need to be configured before using. The register configuration
words are stored in SPD byte 60~116 (JEDEC standard No.21-C). Software
should read those RCWs and put into DDR controller before initialization.

Signed-off-by: York Sun <yorksun@freescale.com>
2010-07-26 13:16:10 -05:00
york
7fd101c97b powerpc/8xxx: Enabled address hashing for 85xx
For 85xx silicon which supports address hashing, it can be activated by
hwconfig.

Signed-off-by: York Sun <yorksun@freescale.com>
2010-07-26 13:16:09 -05:00
york
5800e7ab32 powerpc/8xxx: Enable quad-rank DIMMs.
Previous code presumes each DIMM has up to two rank (chip select). Newer
DDR controller supports up to four chip select on one DIMM.

Signed-off-by: York Sun <yorksun@freescale.com>
2010-07-26 13:16:09 -05:00
Kumar Gala
fd3c9befa8 powerpc/p4080: Add workaround for erratum CPU22
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26 13:07:57 -05:00
Kumar Gala
34a8258fea powerpc/p4080: Add support for initializing SERDES
Add support for initializing the SERDES blocks on CoreNet style QoriQ
devices and the p4080 specific SERDES tables to know which actual
componetns are enabled.

Additionally, split out the Frame Manger (FMAN) into its specific ethernet
ports instead of gross level of the full FMAN.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26 13:07:57 -05:00