Commit graph

44080 commits

Author SHA1 Message Date
Michal Simek
e05d50584c Kconfig: Add description for CMD_POWEROFF
Add poweroff description to Kconfig to make it selectable
via menuconfig.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-09 20:34:54 -04:00
tnishinaga.dev@gmail.com
8f079cccb3 armv7m: Disable D-cache when booting nommu(ARMv7M) Linux kernel
Disable D-Cache is required when booting nommu Linux kernel.
(please see Linux kernel source "arch/arm/kernel/head-nommu.S")

U-Boot is enabled D-cache and I-Cache at startup.
However, it does not disable D-Cache before
booting nommu Linux kernel.
Therefore, I call dcache_disable()
when the CPU is ARMv7M to fix this problem.

Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
2017-06-09 20:34:54 -04:00
Semen Protsenko
00bbe96eba arm: omap: Unify get_device_type() function
Refactor OMAP3/4/5 code so that we have only one get_device_type()
function for all platforms.

Details:
 - Add ctrl variable for AM33xx and OMAP3 platforms (like it's done for
   OMAP4/5), so we can obtain status register in common way
 - For now ctrl structure for AM33xx/OMAP3 contains only status register
   address
 - Run hw_data_init() in order to assign ctrl to proper structure
 - Remove DEVICE_MASK and DEVICE_GP definitions as they are not used
   (DEVICE_TYPE_MASK and GP_DEVICE are used instead)
 - Guard structs in omap_common.h with #ifdefs, because otherwise
   including omap_common.h on non-omap4/5 board files breaks compilation

Buildman script was run for all OMAP boards. Result output:
    arm: (for 38/616 boards)
        all +352.5
        bss -1.4
        data +3.5
        rodata +300.0
        spl/u-boot-spl:all +284.7
        spl/u-boot-spl:data +2.2
        spl/u-boot-spl:rodata +252.0
        spl/u-boot-spl:text +30.5
        text +50.4
    (no errors to report)

Tested on AM57x EVM and BeagleBoard xM.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Rework the guards as to not break TI81xx]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-09 20:34:53 -04:00
Tom Rini
f2d78c1ced am33xx: Finish migration of CONFIG_AM33XX/AM43XX
Almost all users of CONFIG_AM33XX/AM43XX have been migrated.  Finish
moving the last few over to Kconfig, and put all of the boards under the
appropriate Kconfig chocie now.  This board choice is non-optional, so
remove that keyword on am33xx.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-09 20:34:09 -04:00
Sekhar Nori
264e420f36 davinci: omapl138_lcdk: fix tXSNR DDR2 timing value
As per the datasheet[1] available for DDR2 part on board
the OMAP-L138 LCDK, the tXSNR (exit self refresh to a
non-read command) is 137.5 ns. This corresponds to a
value of 20 to be written to T_XSNR register field of
OMAP-L138's DDR configuration. The DDR2 is at 150 MHz.

Fix this. The correct value also appears on the initialization
scripts (called CCS GEL files) available on TI's wiki pages[2]

[1] http://www.samsung.com/global/business/semiconductor/file/product/ds_k4t1gxx4qf_rev12-0.pdf
[2] http://processors.wiki.ti.com/index.php/L138/C6748_Development_Kit_(LCDK)#CCS_XML_.26_GEL_Files

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-06-09 11:24:01 -04:00
Siva Durga Prasad Paladugu
314f6362c4 cmd: jffs2: Rename command ls to fsls
Rename command ls to fsls as its conflicting with
generic file systesm command ls and this is causing
compilation failure as below, if both are enabled
and this patch fixes it.

cmd/jffs2.o:(.u_boot_list_2_cmd_2_ls+0x0):
multiple definition of `_u_boot_list_2_cmd_2_ls'
cmd/fs.o:(.u_boot_list_2_cmd_2_ls+0x0):first defined here
scripts/Makefile.build:359: recipe for target 'cmd/built-in.o'
failed
make[1]: *** [cmd/built-in.o] Error 1

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-09 11:24:01 -04:00
Chris Packham
2bd3cab335 rtc: ds1337: drop "SYS" from config variables
There is some inconsistency between uses of CONFIG_RTC_DS13xx and
CONFIG_SYS_RTC_DS13xx. Address this by dropping the "SYS" from
these variables.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-09 11:24:01 -04:00
Vikas Manocha
1a73bd842e spl: stm32f7: configure for xip booting
With xip booting configuration, we don't need to copy the next image
(U-Boot or linux xipimage) from flash to sdram area.

Flash memory organization is like this:
	spl-U-Boot:	u-boot-spl.bin 	: 0x0800_0000
	U-Boot :	u-boot-dtb.bin	: 0x0800_8000
	linux :		xipImage	: 0x0800_8000

It is also possible to have U-Boot binary & linux binaries configured at
different addresses of flash memory like U-Boot at 0x0800_8000 & linux
xipImage at 0x0800_4000. But in any case, spl-U-Boot needs to be compiled for
U-Boot as next binary with SPL_OS_BOOT option disabled.
By default, spl is configured to boot linux xipImage.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-06-09 11:24:00 -04:00
Vikas Manocha
55a3ef714f spl: stm32f7: add kernel boot support
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-06-09 11:24:00 -04:00
Vikas Manocha
6c0c3ce8aa serial: stm32f7: disable overrun
With overrun enabled, serial port console freezes & stops receiving data with
overun error if we keep sending data.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-06-09 11:23:59 -04:00
Vikas Manocha
c6d9e9dbc3 SPL: Add XIP booting support
Enable support for XIP (execute in place) of U-Boot or kernel image. There is
no need to copy image from flash to ram if flash supports execute in place.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Alexandru Gagniuc <alex.g@adaptrum.com>
2017-06-09 11:23:59 -04:00
Vikas Manocha
b97476965b stm32: stm32f7: add spl build support
This commit supports booting from stm32 internal nor flash. spl U-Boot
initializes the sdram memory, copies next image (e.g. standard U-Boot)
to sdram & then jumps to entry point.

Here are the flash memory addresses for U-Boot-spl & standard U-Boot:
	- spl U-Boot		: 0x0800_0000
	- standard U-Boot	: 0x0800_8000

To compile u-boot without spl: Remove SUPPORT_SPL configuration
(arch/arm/mach-stm32/Kconfig)

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
[trini: Rework Kconfig logic a bit]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-09 11:23:55 -04:00
Vikas Manocha
ea744fca0e stm32f7: remove duplicate configs
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-06-08 21:00:27 -04:00
Vikas Manocha
6bcdd66d1c spl: armv7m: to keep ARM v7M in thumb mode before booting next image
On ARM v7M, the processor will return to ARM mode when executing blx
instruction with bit 0 of the address == 0. Always set it to 1 to stay in thumb
mode.

At present, it is applied only for raw U-Boot. This patch moves it to just
before booting next image. This way armv7m will be in thumb mode for any image
like raw or image with header like zImage or standard U-Boot.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-06-08 21:00:27 -04:00
Tom Rini
156d64fa55 Merge git://git.denx.de/u-boot-rockchip
Here is additional rk3368 and rk3399 support, rv1108 support,
refactoring HDMI video (brought in from Anatolij's tree to resolve
conflicts), some mkimage fixes and a few other things.
2017-06-08 12:14:11 -04:00
Philipp Tomsich
6c53d680c6 rockchip: board: puma_rk3399: enable BMP_16BPP, BMP_24BPP and BMP_32BPP
With video output support for the RK3399-Q7 (Puma) available, we want
CMD_BMP enabled and the support for 16bit, 24bit and 32bit BMPs
defined.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Version-changes: 2
- enable SYS_WHITE_ON_BLACK via defconfig
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:50 -06:00
Philipp Tomsich
64199d4ead rockchip: video: rk_vop: add grf field
The last set of rebases had dropped the 'grf' field from the common
rk_vop.  Add this back to un-break the build (and driver).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-07 21:30:50 -06:00
Philipp Tomsich
ca562b630e rockchip: video: rk3399: add HDMI TX support on the RK3399
This commit enables the RK3399 HDMI TX, which is very similar to the
one found on the RK3288.  As requested by Simon, this splits the HDMI
driver into a SOC-specific portion (rk3399_hdmi.c, rk3288_hdmi.c) and
a common portion (rk_hdmi.c).

Note that the I2C communication for reading the EDID works well with
the default settings, but does not with the alternate settings used on
the RK3288... this configuration aspect is reflected by the driverdata
for the RK3399 driver.

Having some sort of DTS-based configuration for the regulator
dependencies would be nice for the future, but for now we simply use
lists of regulator names (also via driverdata) that we probe.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:50 -06:00
Philipp Tomsich
147fd3ac5a rockchip: video: split RK3288-specific part off from rk_hdmi
To prepare for the addition of RK3399 HDMI support, the HDMI driver is
refactored and broken into a chip-specific and a generic part.  This
change adds the internal interfaces, makes common/reusable functions
externally visible and splits the RK3288 driver into a separate file.

For the probing of regulators, we reuse the infrastructure created
during the VOP refactoring... i.e. we simply call into the helper
function defined for the VOP.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:50 -06:00
Philipp Tomsich
f210e5574f rockchip: video: add mpixelclock settings from Linux driver
The Linux driver now supports higher mpixelclock settings.
Add these to rockchip_phy_config[] and rockchip_mpll_cfg[].

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:50 -06:00
Philipp Tomsich
cc75afc5d7 rockchip: video: rk3399: enable HDMI output (from the rk_vop) for the RK3399
This commit adds a driver for the RK3399 VOPs capable and all the
necessary plumbing to feed the HDMI encoder. For the VOP-big, this
correctly tracks the ability to feed 10bit RGB data to the encoder.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:49 -06:00
Philipp Tomsich
d46d40474a rockchip: video: refactor rk_vop and split RK3288-specific code off
To prepare for adding the RK3399 VOP driver (which shares most of its
registers and config logic with the RK3228 VOP), this change refactors
the driver and splits the RK3288-specific driver off.

The changes in detail are:
- introduces a data-structure for chip-specific drivers to register
  features/callbacks with the common driver: at this time, this is
  limited to a callback for setting the pin polarities (between the
  VOP and the encoder modules) and a flag to signal 10bit RGB
  capability
- refactors the probing of regulators into a helper function that
  can take a list of regulator names to probe and autoset
- moves the priv data-structure into a (common) header file to be
  used by the chip-specific drivers to provide base addresses to
  the common driver
- uses a callback into the chip-specific driver to set pin polarities
  (replacing the direct register accesses previously used)
- splits enabling the output (towards an encoder) into a separate
  help function withint the common driver

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:49 -06:00
Philipp Tomsich
89b2b6186d rockchip: video: Kconfig: set MAX_XRES and MAX_YRES via Kconfig
This introduces two new Kconfig options that configure the maximum
allowable framebuffer size (i.e. the memory reservation/allocation for
the framebuffer):
 - VIDEO_ROCKCHIP_MAX_XRES
 - VIDEO_ROCKCHIP_MAX_YRES
The resulting memory allocation will cover 4 byte per pixel for these
resolutions.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:49 -06:00
Philipp Tomsich
d4bee08419 rockchip: video: Kconfig: reformat help for VIDEO_ROCKCHIP
For consistency sake (and as we are about to add new options to this
file), reformat the help for VIDEO_ROCKCHIP.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:49 -06:00
Philipp Tomsich
4dcd53d0d7 rockchip: defconfig: puma-rk3399: enable SPL_BOARD_INIT
For the RK3399-Q7, we need spl_board_init to be called during SPL
startup to set up the pinmux for the debug UART. Enable SPL_BOARD_INIT
via defconfig to ensure this function is in fact called.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-07 21:30:49 -06:00
Romain Perier
fefe9d06bd rockchip: rk3288: grf: Fix shift for RK3288_TXCLK_DLY_ENA_GMAC_ENABLE
RK3288_TXCLK_DLY_ENA_GMAC_ENABLE, in GRF_SOC_CON3, is supposed to be bit
0xe and not 0xf. Otherwise, it is RGMII RX clock delayline enable and
introduces random delays and data lose.

This commit fixes the issue by replacing RK3288_TXCLK_DLY_ENA_GMAC_ENABLE
with the right shift.

Signed-off-by: Romain Perier <romain.perier@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:48 -06:00
Philipp Tomsich
cf35242a3e rockchip: dts: rk3399-puma: add DTS for the DDR3-1866 timing
This adds the DDR3-1866 timing via its own DTS and wires it up.  This
(currently) is not the default timing for the RK3399-Q7 and should be
selected explicitly via the config (CONFIG_DEFAULT_DEVICE_TREE).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:48 -06:00
Philipp Tomsich
6608cf0fbe rockchip: dts: rk3399-puma: add DTS for the DDR3-1333 timing
This adds the DDR3-1333 timing via its own DTS and wires it up.  This
is not the default timing for the RK3399-Q7 and should be selected
explicitly via the config (CONFIG_DEFAULT_DEVICE_TREE).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:48 -06:00
Philipp Tomsich
3a29ae8e6f rockchip: dts: rk3399-puma: refactor and rename (default) DDR3-1600 DTS
To better support different RAM timings (DDR3-1333 and DDR3-1866 are
assembly options for the RK3399-Q7), this refactors the DTS support
and renames the default DTS variant from rk3399-puma to
rk3399-puma-ddr1600:
- changes the rk3399-puma DTS into a board-specific DTSI by removing
  the inclusion of the DRAM timings
- adds a new rk3399-puma-ddr1600.dts, which includes the (new) common
  board DTSI and the DDR3-1600 timing DTSI
- wires this up from arch/arm/dts/Makefile and configs/puma-rk3399_defconfig

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:48 -06:00
Philipp Tomsich
f592edd920 rockchip: dts: rk3399-puma: sync DTS with Linux tree
The Linux DTS for the RK3399-Q7 has moved with the times... resync
against it to ensure a consistent configuration.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:48 -06:00
Philipp Tomsich
876c1d0fb1 rockchip: dts: rk3399: enable HDMI output in the DTS
This commit enables HDMI output in the DTS by adding the necessary
nodes to vopl/vopb and by adding the HDMI node.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:48 -06:00
Philipp Tomsich
92693b5a4f usb: dwc2-otg: make regs_otg (in platdata) a uintptr_t
The regs_otg field in uintptr_t of the platform data structure for
dwc2-otg has thus far been an unsigned int, but will eventually be
casted into a void*.

This raises the following error with GCC 6.3 and buildman:
  ../drivers/usb/gadget/dwc2_udc_otg.c: In function 'dwc2_udc_probe':
  ../drivers/usb/gadget/dwc2_udc_otg.c:821:8: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    reg = (struct dwc2_usbotg_reg *)pdata->regs_otg;
          ^

This changes regs_otg to a uintptr_t to ensure that it is large enough
to hold any valid pointer (and fix the associated warning).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-07 21:30:48 -06:00
Philipp Tomsich
5a403a27b0 rockchip: defconfig: puma-rk3399: update defconfig with video-support
With HDMI output for the RK3399 working, this update the RK3399-Q7
(Puma) defconfig for the new functionality:
1. enables PMIC command (to check if the HDMI voltages are correct)
      +CONFIG_CMD_PMIC=y
      +CONFIG_CMD_REGULATOR=y
2. enables video-output (via HDMI)
      +CONFIG_DM_VIDEO=y
      +CONFIG_DISPLAY=y
      +CONFIG_VIDEO_ROCKCHIP=y
      +CONFIG_DISPLAY_ROCKCHIP_HDMI=y
3. turns on the 'dcache'-command (for a dcache flush) for our QA to
   fill the framebuffer using 'mw.l'
      +CONFIG_CMD_CACHE=y
4. turns on the 'bmp'-command
      +CONFIG_CMD_BMP=y

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:47 -06:00
Philipp Tomsich
1208523935 rockchip: video: rk_hdmi: fix implicit definition warnings
When enabling CONFIG_DISPLAY_ROCKCHIP_HDMI, compile-time warning for
the following implicitly defined functions are raised due to a missing
include directive:

  drivers/video/rockchip/rk_hdmi.c: In function 'rk_hdmi_probe':
  drivers/video/rockchip/rk_hdmi.c:150:2: warning: implicit declaration of function 'rk_setreg' [-Wimplicit-function-declaration]
    rk_setreg(&priv->grf->soc_con6, 1 << 15);
    ^~~~~~~~~
  drivers/video/rockchip/rk_hdmi.c:153:2: warning: implicit declaration of function 'rk_clrsetreg' [-Wimplicit-function-declaration]
    rk_clrsetreg(&priv->grf->soc_con6, 1 << 4,
    ^~~~~~~~~~~~

This change fixes this by including <asm/hardware.h> in rk_hdmi.c.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:47 -06:00
Philipp Tomsich
a6b08c9677 rockchip: rk3328: don't implement usb_gadget_handle_interrupts twice
The usb_gadget_handle_interrupts()-function is already implemented by
drivers/usb/gadget/dwc2_udc_otg.c, so we need to avoid defining it
in the evb-rk3328.c board-specific file.

This change fixes the following build error (from buildman):
  drivers/usb/gadget/built-in.o: In function `usb_gadget_handle_interrupts':
  build/../drivers/usb/gadget/dwc2_udc_otg.c:850: multiple definition of `usb_gadget_handle_interrupts'
  board/rockchip/evb_rk3328/built-in.o:build/../board/rockchip/evb_rk3328/evb-rk3328.c:37: first defined here
  make[1]: *** [u-boot] Error 1

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:12:52 -06:00
Meng Dongyang
d3cb14b910 rockchip: usb: host: xhci-rockchip: add support for rk3328
Add the compatible "rockchip,rk3328-xhci" in match table
for rk3328 to probe xhci controller. Use fixed regulator
to control the voltage of vbus and turn off vbus when
usb stop.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:25 -06:00
Andy Yan
2d1951fec6 rockchip: Add basic support for evb-rv1108 board
Add basic support for rv1108 evb, whith this patch we
can boot into u-boot console.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:25 -06:00
Andy Yan
2c1e11dd52 rockchip: Add core Soc start-up code for rv1108
RV1108 is embedded with an ARM Cortex-A7 single core and a DSP core
from Rockchip. It is designed for varies application scenario such
as car DVR, sports DV, secure camera and UAV camera.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:25 -06:00
Andy Yan
bae2f282a9 rockchip: clk: Add rv1108 clock driver
Add clock driver support for Rockchip rv1108 soc

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:25 -06:00
Andy Yan
09aa7c468c rockchip: pinctrl: Add rv1108 pinctrl driver
Add pinctrl support for Rockchip rv1108 soc

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:24 -06:00
Andy Yan
79fa157387 rockchip: mkimage: Add support for RV1108
Add support to mkimage for rv1108 soc, the max
spl code size for rv1108 is 6kb, and the spl
code should be packed by rksd, wether boot from
emmc or spi nor flash.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:24 -06:00
Philipp Tomsich
6f2d1d7df6 rockchip: defconfig: puma-rk3399: do not filter clock-names for SPL
For the RK3399-Q7 module, we use full OF_CONTROL (i.e. not
OF_PLATDATA) for SPL.  In this configuration, the rockchip_dw_mmc
driver retrieves one of its clocks via clk_get_by_name and fails if
this is not possible.  For this reason, we can not filter clock-names
from the device-tree nodes used for the configuration of the SPL
stage.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:24 -06:00
Philipp Tomsich
c5d905ff0a rockchip: defconfig: puma-rk3399: enable I2C
The RK3399-Q7 exposes I2C on its edge connector and uses it as one of
the interfaces towards the on-module STM32 (for the emulated RTC and
fan-controller).

Enable I2C and CMD_I2C support in the defconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:24 -06:00
Philipp Tomsich
73dc80a622 rockchip: defconfig: puma-rk3399: enable CONFIG_PHY_MICREL_KSZ9031
The RK3399-Q7 has a KSZ9031 GbE PHY. Enable support for it in defconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:24 -06:00
Philipp Tomsich
e785e7f69a rockchip: defconfig: puma-rk3399: enable RK808 support
On the RK3399-Q7, we need PMIC support (for the RK808) to enable HDMI
output, as one of the required powerrails is not enabled on boot.
For this, we need to enable the RK808 driver.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Version-changes: 3
- With the recent upstream changes to the RK808 (PMIC) driver, the
  associated configuration options have been renamed to RK8XX.  Track
  this change in the RK3399-Q7 defconfig.
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:24 -06:00
Klaus Goger
a4264b4d14 rockchip: dts: rk3399-puma: set spl-payload-offset
defines the spl-payload to 256k (0x40000)

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:23 -06:00
Philipp Tomsich
2dd2c011e8 rockchip: dts: rk3399-puma: release reset of on-module USB3 hub via vbus-gpio
On the RK3399-Q7, the on-module USB3 hub is held in reset at boot-up
to save power and needs to be woken up using GPIO4A3.

Note that this is not a negated reset-signal (due to a level shifter
being needed for this signal anyway), but a negated enable-signal:
to enable, we need to output LOW (i.e. 0)... so we mark this as an
ACTIVE_LOW signal.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:23 -06:00
Philipp Tomsich
4411cd054b rockchip: dts: rk3399-puma: make the debug serial dm-pre-reloc
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:23 -06:00
Philipp Tomsich
3b89461b40 rockchip: dts: rk3399-puma: Add DDR3-1866 timings
With the validation done for DDR3-1866 (i.e. 933 MHz bus clock), we
can now add the timings (rk3399-sdram-ddr3-1866.dtsi) for boards built
with the DDR3-1866 option.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:23 -06:00
Philipp Tomsich
fcb2158516 rockchip: arm64: rk3399: support DDR3-1866 (i.e. 933MHz clock)
The RK3399 is capable of driving DDR3 at 933MHz (i.e. DDR3-1866),
if the PCB layout permits and appropriate memory timings are used.

This changes the sanity checks to allow a DTS to request DDR3-1866
operation.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2017-06-07 07:29:23 -06:00